0001 ########################################################################
0002 # Implement fast SHA-512 with SSSE3 instructions. (x86_64)
0003 #
0004 # Copyright (C) 2013 Intel Corporation.
0005 #
0006 # Authors:
0007 # James Guilford <james.guilford@intel.com>
0008 # Kirk Yap <kirk.s.yap@intel.com>
0009 # David Cote <david.m.cote@intel.com>
0010 # Tim Chen <tim.c.chen@linux.intel.com>
0011 #
0012 # This software is available to you under a choice of one of two
0013 # licenses. You may choose to be licensed under the terms of the GNU
0014 # General Public License (GPL) Version 2, available from the file
0015 # COPYING in the main directory of this source tree, or the
0016 # OpenIB.org BSD license below:
0017 #
0018 # Redistribution and use in source and binary forms, with or
0019 # without modification, are permitted provided that the following
0020 # conditions are met:
0021 #
0022 # - Redistributions of source code must retain the above
0023 # copyright notice, this list of conditions and the following
0024 # disclaimer.
0025 #
0026 # - Redistributions in binary form must reproduce the above
0027 # copyright notice, this list of conditions and the following
0028 # disclaimer in the documentation and/or other materials
0029 # provided with the distribution.
0030 #
0031 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0032 # EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0033 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0034 # NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0035 # BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0036 # ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0037 # CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0038 # SOFTWARE.
0039 #
0040 ########################################################################
0041 #
0042 # This code is described in an Intel White-Paper:
0043 # "Fast SHA-512 Implementations on Intel Architecture Processors"
0044 #
0045 # To find it, surf to http://www.intel.com/p/en_US/embedded
0046 # and search for that title.
0047 #
0048 ########################################################################
0049
0050 #include <linux/linkage.h>
0051
0052 .text
0053
0054 # Virtual Registers
0055 # ARG1
0056 digest = %rdi
0057 # ARG2
0058 msg = %rsi
0059 # ARG3
0060 msglen = %rdx
0061 T1 = %rcx
0062 T2 = %r8
0063 a_64 = %r9
0064 b_64 = %r10
0065 c_64 = %r11
0066 d_64 = %r12
0067 e_64 = %r13
0068 f_64 = %r14
0069 g_64 = %r15
0070 h_64 = %rbx
0071 tmp0 = %rax
0072
0073 # Local variables (stack frame)
0074
0075 W_SIZE = 80*8
0076 WK_SIZE = 2*8
0077
0078 frame_W = 0
0079 frame_WK = frame_W + W_SIZE
0080 frame_size = frame_WK + WK_SIZE
0081
0082 # Useful QWORD "arrays" for simpler memory references
0083 # MSG, DIGEST, K_t, W_t are arrays
0084 # WK_2(t) points to 1 of 2 qwords at frame.WK depdending on t being odd/even
0085
0086 # Input message (arg1)
0087 #define MSG(i) 8*i(msg)
0088
0089 # Output Digest (arg2)
0090 #define DIGEST(i) 8*i(digest)
0091
0092 # SHA Constants (static mem)
0093 #define K_t(i) 8*i+K512(%rip)
0094
0095 # Message Schedule (stack frame)
0096 #define W_t(i) 8*i+frame_W(%rsp)
0097
0098 # W[t]+K[t] (stack frame)
0099 #define WK_2(i) 8*((i%2))+frame_WK(%rsp)
0100
0101 .macro RotateState
0102 # Rotate symbols a..h right
0103 TMP = h_64
0104 h_64 = g_64
0105 g_64 = f_64
0106 f_64 = e_64
0107 e_64 = d_64
0108 d_64 = c_64
0109 c_64 = b_64
0110 b_64 = a_64
0111 a_64 = TMP
0112 .endm
0113
0114 .macro SHA512_Round rnd
0115
0116 # Compute Round %%t
0117 mov f_64, T1 # T1 = f
0118 mov e_64, tmp0 # tmp = e
0119 xor g_64, T1 # T1 = f ^ g
0120 ror $23, tmp0 # 41 # tmp = e ror 23
0121 and e_64, T1 # T1 = (f ^ g) & e
0122 xor e_64, tmp0 # tmp = (e ror 23) ^ e
0123 xor g_64, T1 # T1 = ((f ^ g) & e) ^ g = CH(e,f,g)
0124 idx = \rnd
0125 add WK_2(idx), T1 # W[t] + K[t] from message scheduler
0126 ror $4, tmp0 # 18 # tmp = ((e ror 23) ^ e) ror 4
0127 xor e_64, tmp0 # tmp = (((e ror 23) ^ e) ror 4) ^ e
0128 mov a_64, T2 # T2 = a
0129 add h_64, T1 # T1 = CH(e,f,g) + W[t] + K[t] + h
0130 ror $14, tmp0 # 14 # tmp = ((((e ror23)^e)ror4)^e)ror14 = S1(e)
0131 add tmp0, T1 # T1 = CH(e,f,g) + W[t] + K[t] + S1(e)
0132 mov a_64, tmp0 # tmp = a
0133 xor c_64, T2 # T2 = a ^ c
0134 and c_64, tmp0 # tmp = a & c
0135 and b_64, T2 # T2 = (a ^ c) & b
0136 xor tmp0, T2 # T2 = ((a ^ c) & b) ^ (a & c) = Maj(a,b,c)
0137 mov a_64, tmp0 # tmp = a
0138 ror $5, tmp0 # 39 # tmp = a ror 5
0139 xor a_64, tmp0 # tmp = (a ror 5) ^ a
0140 add T1, d_64 # e(next_state) = d + T1
0141 ror $6, tmp0 # 34 # tmp = ((a ror 5) ^ a) ror 6
0142 xor a_64, tmp0 # tmp = (((a ror 5) ^ a) ror 6) ^ a
0143 lea (T1, T2), h_64 # a(next_state) = T1 + Maj(a,b,c)
0144 ror $28, tmp0 # 28 # tmp = ((((a ror5)^a)ror6)^a)ror28 = S0(a)
0145 add tmp0, h_64 # a(next_state) = T1 + Maj(a,b,c) S0(a)
0146 RotateState
0147 .endm
0148
0149 .macro SHA512_2Sched_2Round_sse rnd
0150
0151 # Compute rounds t-2 and t-1
0152 # Compute message schedule QWORDS t and t+1
0153
0154 # Two rounds are computed based on the values for K[t-2]+W[t-2] and
0155 # K[t-1]+W[t-1] which were previously stored at WK_2 by the message
0156 # scheduler.
0157 # The two new schedule QWORDS are stored at [W_t(%%t)] and [W_t(%%t+1)].
0158 # They are then added to their respective SHA512 constants at
0159 # [K_t(%%t)] and [K_t(%%t+1)] and stored at dqword [WK_2(%%t)]
0160 # For brievity, the comments following vectored instructions only refer to
0161 # the first of a pair of QWORDS.
0162 # Eg. XMM2=W[t-2] really means XMM2={W[t-2]|W[t-1]}
0163 # The computation of the message schedule and the rounds are tightly
0164 # stitched to take advantage of instruction-level parallelism.
0165 # For clarity, integer instructions (for the rounds calculation) are indented
0166 # by one tab. Vectored instructions (for the message scheduler) are indented
0167 # by two tabs.
0168
0169 mov f_64, T1
0170 idx = \rnd -2
0171 movdqa W_t(idx), %xmm2 # XMM2 = W[t-2]
0172 xor g_64, T1
0173 and e_64, T1
0174 movdqa %xmm2, %xmm0 # XMM0 = W[t-2]
0175 xor g_64, T1
0176 idx = \rnd
0177 add WK_2(idx), T1
0178 idx = \rnd - 15
0179 movdqu W_t(idx), %xmm5 # XMM5 = W[t-15]
0180 mov e_64, tmp0
0181 ror $23, tmp0 # 41
0182 movdqa %xmm5, %xmm3 # XMM3 = W[t-15]
0183 xor e_64, tmp0
0184 ror $4, tmp0 # 18
0185 psrlq $61-19, %xmm0 # XMM0 = W[t-2] >> 42
0186 xor e_64, tmp0
0187 ror $14, tmp0 # 14
0188 psrlq $(8-7), %xmm3 # XMM3 = W[t-15] >> 1
0189 add tmp0, T1
0190 add h_64, T1
0191 pxor %xmm2, %xmm0 # XMM0 = (W[t-2] >> 42) ^ W[t-2]
0192 mov a_64, T2
0193 xor c_64, T2
0194 pxor %xmm5, %xmm3 # XMM3 = (W[t-15] >> 1) ^ W[t-15]
0195 and b_64, T2
0196 mov a_64, tmp0
0197 psrlq $(19-6), %xmm0 # XMM0 = ((W[t-2]>>42)^W[t-2])>>13
0198 and c_64, tmp0
0199 xor tmp0, T2
0200 psrlq $(7-1), %xmm3 # XMM3 = ((W[t-15]>>1)^W[t-15])>>6
0201 mov a_64, tmp0
0202 ror $5, tmp0 # 39
0203 pxor %xmm2, %xmm0 # XMM0 = (((W[t-2]>>42)^W[t-2])>>13)^W[t-2]
0204 xor a_64, tmp0
0205 ror $6, tmp0 # 34
0206 pxor %xmm5, %xmm3 # XMM3 = (((W[t-15]>>1)^W[t-15])>>6)^W[t-15]
0207 xor a_64, tmp0
0208 ror $28, tmp0 # 28
0209 psrlq $6, %xmm0 # XMM0 = ((((W[t-2]>>42)^W[t-2])>>13)^W[t-2])>>6
0210 add tmp0, T2
0211 add T1, d_64
0212 psrlq $1, %xmm3 # XMM3 = (((W[t-15]>>1)^W[t-15])>>6)^W[t-15]>>1
0213 lea (T1, T2), h_64
0214 RotateState
0215 movdqa %xmm2, %xmm1 # XMM1 = W[t-2]
0216 mov f_64, T1
0217 xor g_64, T1
0218 movdqa %xmm5, %xmm4 # XMM4 = W[t-15]
0219 and e_64, T1
0220 xor g_64, T1
0221 psllq $(64-19)-(64-61) , %xmm1 # XMM1 = W[t-2] << 42
0222 idx = \rnd + 1
0223 add WK_2(idx), T1
0224 mov e_64, tmp0
0225 psllq $(64-1)-(64-8), %xmm4 # XMM4 = W[t-15] << 7
0226 ror $23, tmp0 # 41
0227 xor e_64, tmp0
0228 pxor %xmm2, %xmm1 # XMM1 = (W[t-2] << 42)^W[t-2]
0229 ror $4, tmp0 # 18
0230 xor e_64, tmp0
0231 pxor %xmm5, %xmm4 # XMM4 = (W[t-15]<<7)^W[t-15]
0232 ror $14, tmp0 # 14
0233 add tmp0, T1
0234 psllq $(64-61), %xmm1 # XMM1 = ((W[t-2] << 42)^W[t-2])<<3
0235 add h_64, T1
0236 mov a_64, T2
0237 psllq $(64-8), %xmm4 # XMM4 = ((W[t-15]<<7)^W[t-15])<<56
0238 xor c_64, T2
0239 and b_64, T2
0240 pxor %xmm1, %xmm0 # XMM0 = s1(W[t-2])
0241 mov a_64, tmp0
0242 and c_64, tmp0
0243 idx = \rnd - 7
0244 movdqu W_t(idx), %xmm1 # XMM1 = W[t-7]
0245 xor tmp0, T2
0246 pxor %xmm4, %xmm3 # XMM3 = s0(W[t-15])
0247 mov a_64, tmp0
0248 paddq %xmm3, %xmm0 # XMM0 = s1(W[t-2]) + s0(W[t-15])
0249 ror $5, tmp0 # 39
0250 idx =\rnd-16
0251 paddq W_t(idx), %xmm0 # XMM0 = s1(W[t-2]) + s0(W[t-15]) + W[t-16]
0252 xor a_64, tmp0
0253 paddq %xmm1, %xmm0 # XMM0 = s1(W[t-2]) + W[t-7] + s0(W[t-15]) + W[t-16]
0254 ror $6, tmp0 # 34
0255 movdqa %xmm0, W_t(\rnd) # Store scheduled qwords
0256 xor a_64, tmp0
0257 paddq K_t(\rnd), %xmm0 # Compute W[t]+K[t]
0258 ror $28, tmp0 # 28
0259 idx = \rnd
0260 movdqa %xmm0, WK_2(idx) # Store W[t]+K[t] for next rounds
0261 add tmp0, T2
0262 add T1, d_64
0263 lea (T1, T2), h_64
0264 RotateState
0265 .endm
0266
0267 ########################################################################
0268 ## void sha512_transform_ssse3(struct sha512_state *state, const u8 *data,
0269 ## int blocks);
0270 # (struct sha512_state is assumed to begin with u64 state[8])
0271 # Purpose: Updates the SHA512 digest stored at "state" with the message
0272 # stored in "data".
0273 # The size of the message pointed to by "data" must be an integer multiple
0274 # of SHA512 message blocks.
0275 # "blocks" is the message length in SHA512 blocks.
0276 ########################################################################
0277 SYM_FUNC_START(sha512_transform_ssse3)
0278
0279 test msglen, msglen
0280 je nowork
0281
0282 # Save GPRs
0283 push %rbx
0284 push %r12
0285 push %r13
0286 push %r14
0287 push %r15
0288
0289 # Allocate Stack Space
0290 push %rbp
0291 mov %rsp, %rbp
0292 sub $frame_size, %rsp
0293 and $~(0x20 - 1), %rsp
0294
0295 updateblock:
0296
0297 # Load state variables
0298 mov DIGEST(0), a_64
0299 mov DIGEST(1), b_64
0300 mov DIGEST(2), c_64
0301 mov DIGEST(3), d_64
0302 mov DIGEST(4), e_64
0303 mov DIGEST(5), f_64
0304 mov DIGEST(6), g_64
0305 mov DIGEST(7), h_64
0306
0307 t = 0
0308 .rept 80/2 + 1
0309 # (80 rounds) / (2 rounds/iteration) + (1 iteration)
0310 # +1 iteration because the scheduler leads hashing by 1 iteration
0311 .if t < 2
0312 # BSWAP 2 QWORDS
0313 movdqa XMM_QWORD_BSWAP(%rip), %xmm1
0314 movdqu MSG(t), %xmm0
0315 pshufb %xmm1, %xmm0 # BSWAP
0316 movdqa %xmm0, W_t(t) # Store Scheduled Pair
0317 paddq K_t(t), %xmm0 # Compute W[t]+K[t]
0318 movdqa %xmm0, WK_2(t) # Store into WK for rounds
0319 .elseif t < 16
0320 # BSWAP 2 QWORDS# Compute 2 Rounds
0321 movdqu MSG(t), %xmm0
0322 pshufb %xmm1, %xmm0 # BSWAP
0323 SHA512_Round t-2 # Round t-2
0324 movdqa %xmm0, W_t(t) # Store Scheduled Pair
0325 paddq K_t(t), %xmm0 # Compute W[t]+K[t]
0326 SHA512_Round t-1 # Round t-1
0327 movdqa %xmm0, WK_2(t) # Store W[t]+K[t] into WK
0328 .elseif t < 79
0329 # Schedule 2 QWORDS# Compute 2 Rounds
0330 SHA512_2Sched_2Round_sse t
0331 .else
0332 # Compute 2 Rounds
0333 SHA512_Round t-2
0334 SHA512_Round t-1
0335 .endif
0336 t = t+2
0337 .endr
0338
0339 # Update digest
0340 add a_64, DIGEST(0)
0341 add b_64, DIGEST(1)
0342 add c_64, DIGEST(2)
0343 add d_64, DIGEST(3)
0344 add e_64, DIGEST(4)
0345 add f_64, DIGEST(5)
0346 add g_64, DIGEST(6)
0347 add h_64, DIGEST(7)
0348
0349 # Advance to next message block
0350 add $16*8, msg
0351 dec msglen
0352 jnz updateblock
0353
0354 # Restore Stack Pointer
0355 mov %rbp, %rsp
0356 pop %rbp
0357
0358 # Restore GPRs
0359 pop %r15
0360 pop %r14
0361 pop %r13
0362 pop %r12
0363 pop %rbx
0364
0365 nowork:
0366 RET
0367 SYM_FUNC_END(sha512_transform_ssse3)
0368
0369 ########################################################################
0370 ### Binary Data
0371
0372 .section .rodata.cst16.XMM_QWORD_BSWAP, "aM", @progbits, 16
0373 .align 16
0374 # Mask for byte-swapping a couple of qwords in an XMM register using (v)pshufb.
0375 XMM_QWORD_BSWAP:
0376 .octa 0x08090a0b0c0d0e0f0001020304050607
0377
0378 # Mergeable 640-byte rodata section. This allows linker to merge the table
0379 # with other, exactly the same 640-byte fragment of another rodata section
0380 # (if such section exists).
0381 .section .rodata.cst640.K512, "aM", @progbits, 640
0382 .align 64
0383 # K[t] used in SHA512 hashing
0384 K512:
0385 .quad 0x428a2f98d728ae22,0x7137449123ef65cd
0386 .quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
0387 .quad 0x3956c25bf348b538,0x59f111f1b605d019
0388 .quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118
0389 .quad 0xd807aa98a3030242,0x12835b0145706fbe
0390 .quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
0391 .quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1
0392 .quad 0x9bdc06a725c71235,0xc19bf174cf692694
0393 .quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3
0394 .quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
0395 .quad 0x2de92c6f592b0275,0x4a7484aa6ea6e483
0396 .quad 0x5cb0a9dcbd41fbd4,0x76f988da831153b5
0397 .quad 0x983e5152ee66dfab,0xa831c66d2db43210
0398 .quad 0xb00327c898fb213f,0xbf597fc7beef0ee4
0399 .quad 0xc6e00bf33da88fc2,0xd5a79147930aa725
0400 .quad 0x06ca6351e003826f,0x142929670a0e6e70
0401 .quad 0x27b70a8546d22ffc,0x2e1b21385c26c926
0402 .quad 0x4d2c6dfc5ac42aed,0x53380d139d95b3df
0403 .quad 0x650a73548baf63de,0x766a0abb3c77b2a8
0404 .quad 0x81c2c92e47edaee6,0x92722c851482353b
0405 .quad 0xa2bfe8a14cf10364,0xa81a664bbc423001
0406 .quad 0xc24b8b70d0f89791,0xc76c51a30654be30
0407 .quad 0xd192e819d6ef5218,0xd69906245565a910
0408 .quad 0xf40e35855771202a,0x106aa07032bbd1b8
0409 .quad 0x19a4c116b8d2d0c8,0x1e376c085141ab53
0410 .quad 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8
0411 .quad 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb
0412 .quad 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3
0413 .quad 0x748f82ee5defb2fc,0x78a5636f43172f60
0414 .quad 0x84c87814a1f0ab72,0x8cc702081a6439ec
0415 .quad 0x90befffa23631e28,0xa4506cebde82bde9
0416 .quad 0xbef9a3f7b2c67915,0xc67178f2e372532b
0417 .quad 0xca273eceea26619c,0xd186b8c721c0c207
0418 .quad 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178
0419 .quad 0x06f067aa72176fba,0x0a637dc5a2c898a6
0420 .quad 0x113f9804bef90dae,0x1b710b35131c471b
0421 .quad 0x28db77f523047d84,0x32caab7b40c72493
0422 .quad 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c
0423 .quad 0x4cc5d4becb3e42b6,0x597f299cfc657e2a
0424 .quad 0x5fcb6fab3ad6faec,0x6c44198c4a475817
