0001 ########################################################################
0002 # Implement fast SHA-512 with AVX instructions. (x86_64)
0003 #
0004 # Copyright (C) 2013 Intel Corporation.
0005 #
0006 # Authors:
0007 # James Guilford <james.guilford@intel.com>
0008 # Kirk Yap <kirk.s.yap@intel.com>
0009 # David Cote <david.m.cote@intel.com>
0010 # Tim Chen <tim.c.chen@linux.intel.com>
0011 #
0012 # This software is available to you under a choice of one of two
0013 # licenses. You may choose to be licensed under the terms of the GNU
0014 # General Public License (GPL) Version 2, available from the file
0015 # COPYING in the main directory of this source tree, or the
0016 # OpenIB.org BSD license below:
0017 #
0018 # Redistribution and use in source and binary forms, with or
0019 # without modification, are permitted provided that the following
0020 # conditions are met:
0021 #
0022 # - Redistributions of source code must retain the above
0023 # copyright notice, this list of conditions and the following
0024 # disclaimer.
0025 #
0026 # - Redistributions in binary form must reproduce the above
0027 # copyright notice, this list of conditions and the following
0028 # disclaimer in the documentation and/or other materials
0029 # provided with the distribution.
0030 #
0031 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0032 # EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0033 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0034 # NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0035 # BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0036 # ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0037 # CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0038 # SOFTWARE.
0039 #
0040 ########################################################################
0041 #
0042 # This code is described in an Intel White-Paper:
0043 # "Fast SHA-512 Implementations on Intel Architecture Processors"
0044 #
0045 # To find it, surf to http://www.intel.com/p/en_US/embedded
0046 # and search for that title.
0047 #
0048 ########################################################################
0049
0050 #include <linux/linkage.h>
0051
0052 .text
0053
0054 # Virtual Registers
0055 # ARG1
0056 digest = %rdi
0057 # ARG2
0058 msg = %rsi
0059 # ARG3
0060 msglen = %rdx
0061 T1 = %rcx
0062 T2 = %r8
0063 a_64 = %r9
0064 b_64 = %r10
0065 c_64 = %r11
0066 d_64 = %r12
0067 e_64 = %r13
0068 f_64 = %r14
0069 g_64 = %r15
0070 h_64 = %rbx
0071 tmp0 = %rax
0072
0073 # Local variables (stack frame)
0074
0075 # Message Schedule
0076 W_SIZE = 80*8
0077 # W[t] + K[t] | W[t+1] + K[t+1]
0078 WK_SIZE = 2*8
0079
0080 frame_W = 0
0081 frame_WK = frame_W + W_SIZE
0082 frame_size = frame_WK + WK_SIZE
0083
0084 # Useful QWORD "arrays" for simpler memory references
0085 # MSG, DIGEST, K_t, W_t are arrays
0086 # WK_2(t) points to 1 of 2 qwords at frame.WK depdending on t being odd/even
0087
0088 # Input message (arg1)
0089 #define MSG(i) 8*i(msg)
0090
0091 # Output Digest (arg2)
0092 #define DIGEST(i) 8*i(digest)
0093
0094 # SHA Constants (static mem)
0095 #define K_t(i) 8*i+K512(%rip)
0096
0097 # Message Schedule (stack frame)
0098 #define W_t(i) 8*i+frame_W(%rsp)
0099
0100 # W[t]+K[t] (stack frame)
0101 #define WK_2(i) 8*((i%2))+frame_WK(%rsp)
0102
0103 .macro RotateState
0104 # Rotate symbols a..h right
0105 TMP = h_64
0106 h_64 = g_64
0107 g_64 = f_64
0108 f_64 = e_64
0109 e_64 = d_64
0110 d_64 = c_64
0111 c_64 = b_64
0112 b_64 = a_64
0113 a_64 = TMP
0114 .endm
0115
0116 .macro RORQ p1 p2
0117 # shld is faster than ror on Sandybridge
0118 shld $(64-\p2), \p1, \p1
0119 .endm
0120
0121 .macro SHA512_Round rnd
0122 # Compute Round %%t
0123 mov f_64, T1 # T1 = f
0124 mov e_64, tmp0 # tmp = e
0125 xor g_64, T1 # T1 = f ^ g
0126 RORQ tmp0, 23 # 41 # tmp = e ror 23
0127 and e_64, T1 # T1 = (f ^ g) & e
0128 xor e_64, tmp0 # tmp = (e ror 23) ^ e
0129 xor g_64, T1 # T1 = ((f ^ g) & e) ^ g = CH(e,f,g)
0130 idx = \rnd
0131 add WK_2(idx), T1 # W[t] + K[t] from message scheduler
0132 RORQ tmp0, 4 # 18 # tmp = ((e ror 23) ^ e) ror 4
0133 xor e_64, tmp0 # tmp = (((e ror 23) ^ e) ror 4) ^ e
0134 mov a_64, T2 # T2 = a
0135 add h_64, T1 # T1 = CH(e,f,g) + W[t] + K[t] + h
0136 RORQ tmp0, 14 # 14 # tmp = ((((e ror23)^e)ror4)^e)ror14 = S1(e)
0137 add tmp0, T1 # T1 = CH(e,f,g) + W[t] + K[t] + S1(e)
0138 mov a_64, tmp0 # tmp = a
0139 xor c_64, T2 # T2 = a ^ c
0140 and c_64, tmp0 # tmp = a & c
0141 and b_64, T2 # T2 = (a ^ c) & b
0142 xor tmp0, T2 # T2 = ((a ^ c) & b) ^ (a & c) = Maj(a,b,c)
0143 mov a_64, tmp0 # tmp = a
0144 RORQ tmp0, 5 # 39 # tmp = a ror 5
0145 xor a_64, tmp0 # tmp = (a ror 5) ^ a
0146 add T1, d_64 # e(next_state) = d + T1
0147 RORQ tmp0, 6 # 34 # tmp = ((a ror 5) ^ a) ror 6
0148 xor a_64, tmp0 # tmp = (((a ror 5) ^ a) ror 6) ^ a
0149 lea (T1, T2), h_64 # a(next_state) = T1 + Maj(a,b,c)
0150 RORQ tmp0, 28 # 28 # tmp = ((((a ror5)^a)ror6)^a)ror28 = S0(a)
0151 add tmp0, h_64 # a(next_state) = T1 + Maj(a,b,c) S0(a)
0152 RotateState
0153 .endm
0154
0155 .macro SHA512_2Sched_2Round_avx rnd
0156 # Compute rounds t-2 and t-1
0157 # Compute message schedule QWORDS t and t+1
0158
0159 # Two rounds are computed based on the values for K[t-2]+W[t-2] and
0160 # K[t-1]+W[t-1] which were previously stored at WK_2 by the message
0161 # scheduler.
0162 # The two new schedule QWORDS are stored at [W_t(t)] and [W_t(t+1)].
0163 # They are then added to their respective SHA512 constants at
0164 # [K_t(t)] and [K_t(t+1)] and stored at dqword [WK_2(t)]
0165 # For brievity, the comments following vectored instructions only refer to
0166 # the first of a pair of QWORDS.
0167 # Eg. XMM4=W[t-2] really means XMM4={W[t-2]|W[t-1]}
0168 # The computation of the message schedule and the rounds are tightly
0169 # stitched to take advantage of instruction-level parallelism.
0170
0171 idx = \rnd - 2
0172 vmovdqa W_t(idx), %xmm4 # XMM4 = W[t-2]
0173 idx = \rnd - 15
0174 vmovdqu W_t(idx), %xmm5 # XMM5 = W[t-15]
0175 mov f_64, T1
0176 vpsrlq $61, %xmm4, %xmm0 # XMM0 = W[t-2]>>61
0177 mov e_64, tmp0
0178 vpsrlq $1, %xmm5, %xmm6 # XMM6 = W[t-15]>>1
0179 xor g_64, T1
0180 RORQ tmp0, 23 # 41
0181 vpsrlq $19, %xmm4, %xmm1 # XMM1 = W[t-2]>>19
0182 and e_64, T1
0183 xor e_64, tmp0
0184 vpxor %xmm1, %xmm0, %xmm0 # XMM0 = W[t-2]>>61 ^ W[t-2]>>19
0185 xor g_64, T1
0186 idx = \rnd
0187 add WK_2(idx), T1#
0188 vpsrlq $8, %xmm5, %xmm7 # XMM7 = W[t-15]>>8
0189 RORQ tmp0, 4 # 18
0190 vpsrlq $6, %xmm4, %xmm2 # XMM2 = W[t-2]>>6
0191 xor e_64, tmp0
0192 mov a_64, T2
0193 add h_64, T1
0194 vpxor %xmm7, %xmm6, %xmm6 # XMM6 = W[t-15]>>1 ^ W[t-15]>>8
0195 RORQ tmp0, 14 # 14
0196 add tmp0, T1
0197 vpsrlq $7, %xmm5, %xmm8 # XMM8 = W[t-15]>>7
0198 mov a_64, tmp0
0199 xor c_64, T2
0200 vpsllq $(64-61), %xmm4, %xmm3 # XMM3 = W[t-2]<<3
0201 and c_64, tmp0
0202 and b_64, T2
0203 vpxor %xmm3, %xmm2, %xmm2 # XMM2 = W[t-2]>>6 ^ W[t-2]<<3
0204 xor tmp0, T2
0205 mov a_64, tmp0
0206 vpsllq $(64-1), %xmm5, %xmm9 # XMM9 = W[t-15]<<63
0207 RORQ tmp0, 5 # 39
0208 vpxor %xmm9, %xmm8, %xmm8 # XMM8 = W[t-15]>>7 ^ W[t-15]<<63
0209 xor a_64, tmp0
0210 add T1, d_64
0211 RORQ tmp0, 6 # 34
0212 xor a_64, tmp0
0213 vpxor %xmm8, %xmm6, %xmm6 # XMM6 = W[t-15]>>1 ^ W[t-15]>>8 ^
0214 # W[t-15]>>7 ^ W[t-15]<<63
0215 lea (T1, T2), h_64
0216 RORQ tmp0, 28 # 28
0217 vpsllq $(64-19), %xmm4, %xmm4 # XMM4 = W[t-2]<<25
0218 add tmp0, h_64
0219 RotateState
0220 vpxor %xmm4, %xmm0, %xmm0 # XMM0 = W[t-2]>>61 ^ W[t-2]>>19 ^
0221 # W[t-2]<<25
0222 mov f_64, T1
0223 vpxor %xmm2, %xmm0, %xmm0 # XMM0 = s1(W[t-2])
0224 mov e_64, tmp0
0225 xor g_64, T1
0226 idx = \rnd - 16
0227 vpaddq W_t(idx), %xmm0, %xmm0 # XMM0 = s1(W[t-2]) + W[t-16]
0228 idx = \rnd - 7
0229 vmovdqu W_t(idx), %xmm1 # XMM1 = W[t-7]
0230 RORQ tmp0, 23 # 41
0231 and e_64, T1
0232 xor e_64, tmp0
0233 xor g_64, T1
0234 vpsllq $(64-8), %xmm5, %xmm5 # XMM5 = W[t-15]<<56
0235 idx = \rnd + 1
0236 add WK_2(idx), T1
0237 vpxor %xmm5, %xmm6, %xmm6 # XMM6 = s0(W[t-15])
0238 RORQ tmp0, 4 # 18
0239 vpaddq %xmm6, %xmm0, %xmm0 # XMM0 = s1(W[t-2]) + W[t-16] + s0(W[t-15])
0240 xor e_64, tmp0
0241 vpaddq %xmm1, %xmm0, %xmm0 # XMM0 = W[t] = s1(W[t-2]) + W[t-7] +
0242 # s0(W[t-15]) + W[t-16]
0243 mov a_64, T2
0244 add h_64, T1
0245 RORQ tmp0, 14 # 14
0246 add tmp0, T1
0247 idx = \rnd
0248 vmovdqa %xmm0, W_t(idx) # Store W[t]
0249 vpaddq K_t(idx), %xmm0, %xmm0 # Compute W[t]+K[t]
0250 vmovdqa %xmm0, WK_2(idx) # Store W[t]+K[t] for next rounds
0251 mov a_64, tmp0
0252 xor c_64, T2
0253 and c_64, tmp0
0254 and b_64, T2
0255 xor tmp0, T2
0256 mov a_64, tmp0
0257 RORQ tmp0, 5 # 39
0258 xor a_64, tmp0
0259 add T1, d_64
0260 RORQ tmp0, 6 # 34
0261 xor a_64, tmp0
0262 lea (T1, T2), h_64
0263 RORQ tmp0, 28 # 28
0264 add tmp0, h_64
0265 RotateState
0266 .endm
0267
0268 ########################################################################
0269 # void sha512_transform_avx(sha512_state *state, const u8 *data, int blocks)
0270 # Purpose: Updates the SHA512 digest stored at "state" with the message
0271 # stored in "data".
0272 # The size of the message pointed to by "data" must be an integer multiple
0273 # of SHA512 message blocks.
0274 # "blocks" is the message length in SHA512 blocks
0275 ########################################################################
0276 SYM_FUNC_START(sha512_transform_avx)
0277 test msglen, msglen
0278 je nowork
0279
0280 # Save GPRs
0281 push %rbx
0282 push %r12
0283 push %r13
0284 push %r14
0285 push %r15
0286
0287 # Allocate Stack Space
0288 push %rbp
0289 mov %rsp, %rbp
0290 sub $frame_size, %rsp
0291 and $~(0x20 - 1), %rsp
0292
0293 updateblock:
0294
0295 # Load state variables
0296 mov DIGEST(0), a_64
0297 mov DIGEST(1), b_64
0298 mov DIGEST(2), c_64
0299 mov DIGEST(3), d_64
0300 mov DIGEST(4), e_64
0301 mov DIGEST(5), f_64
0302 mov DIGEST(6), g_64
0303 mov DIGEST(7), h_64
0304
0305 t = 0
0306 .rept 80/2 + 1
0307 # (80 rounds) / (2 rounds/iteration) + (1 iteration)
0308 # +1 iteration because the scheduler leads hashing by 1 iteration
0309 .if t < 2
0310 # BSWAP 2 QWORDS
0311 vmovdqa XMM_QWORD_BSWAP(%rip), %xmm1
0312 vmovdqu MSG(t), %xmm0
0313 vpshufb %xmm1, %xmm0, %xmm0 # BSWAP
0314 vmovdqa %xmm0, W_t(t) # Store Scheduled Pair
0315 vpaddq K_t(t), %xmm0, %xmm0 # Compute W[t]+K[t]
0316 vmovdqa %xmm0, WK_2(t) # Store into WK for rounds
0317 .elseif t < 16
0318 # BSWAP 2 QWORDS# Compute 2 Rounds
0319 vmovdqu MSG(t), %xmm0
0320 vpshufb %xmm1, %xmm0, %xmm0 # BSWAP
0321 SHA512_Round t-2 # Round t-2
0322 vmovdqa %xmm0, W_t(t) # Store Scheduled Pair
0323 vpaddq K_t(t), %xmm0, %xmm0 # Compute W[t]+K[t]
0324 SHA512_Round t-1 # Round t-1
0325 vmovdqa %xmm0, WK_2(t)# Store W[t]+K[t] into WK
0326 .elseif t < 79
0327 # Schedule 2 QWORDS# Compute 2 Rounds
0328 SHA512_2Sched_2Round_avx t
0329 .else
0330 # Compute 2 Rounds
0331 SHA512_Round t-2
0332 SHA512_Round t-1
0333 .endif
0334 t = t+2
0335 .endr
0336
0337 # Update digest
0338 add a_64, DIGEST(0)
0339 add b_64, DIGEST(1)
0340 add c_64, DIGEST(2)
0341 add d_64, DIGEST(3)
0342 add e_64, DIGEST(4)
0343 add f_64, DIGEST(5)
0344 add g_64, DIGEST(6)
0345 add h_64, DIGEST(7)
0346
0347 # Advance to next message block
0348 add $16*8, msg
0349 dec msglen
0350 jnz updateblock
0351
0352 # Restore Stack Pointer
0353 mov %rbp, %rsp
0354 pop %rbp
0355
0356 # Restore GPRs
0357 pop %r15
0358 pop %r14
0359 pop %r13
0360 pop %r12
0361 pop %rbx
0362
0363 nowork:
0364 RET
0365 SYM_FUNC_END(sha512_transform_avx)
0366
0367 ########################################################################
0368 ### Binary Data
0369
0370 .section .rodata.cst16.XMM_QWORD_BSWAP, "aM", @progbits, 16
0371 .align 16
0372 # Mask for byte-swapping a couple of qwords in an XMM register using (v)pshufb.
0373 XMM_QWORD_BSWAP:
0374 .octa 0x08090a0b0c0d0e0f0001020304050607
0375
0376 # Mergeable 640-byte rodata section. This allows linker to merge the table
0377 # with other, exactly the same 640-byte fragment of another rodata section
0378 # (if such section exists).
0379 .section .rodata.cst640.K512, "aM", @progbits, 640
0380 .align 64
0381 # K[t] used in SHA512 hashing
0382 K512:
0383 .quad 0x428a2f98d728ae22,0x7137449123ef65cd
0384 .quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
0385 .quad 0x3956c25bf348b538,0x59f111f1b605d019
0386 .quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118
0387 .quad 0xd807aa98a3030242,0x12835b0145706fbe
0388 .quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
0389 .quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1
0390 .quad 0x9bdc06a725c71235,0xc19bf174cf692694
0391 .quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3
0392 .quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
0393 .quad 0x2de92c6f592b0275,0x4a7484aa6ea6e483
0394 .quad 0x5cb0a9dcbd41fbd4,0x76f988da831153b5
0395 .quad 0x983e5152ee66dfab,0xa831c66d2db43210
0396 .quad 0xb00327c898fb213f,0xbf597fc7beef0ee4
0397 .quad 0xc6e00bf33da88fc2,0xd5a79147930aa725
0398 .quad 0x06ca6351e003826f,0x142929670a0e6e70
0399 .quad 0x27b70a8546d22ffc,0x2e1b21385c26c926
0400 .quad 0x4d2c6dfc5ac42aed,0x53380d139d95b3df
0401 .quad 0x650a73548baf63de,0x766a0abb3c77b2a8
0402 .quad 0x81c2c92e47edaee6,0x92722c851482353b
0403 .quad 0xa2bfe8a14cf10364,0xa81a664bbc423001
0404 .quad 0xc24b8b70d0f89791,0xc76c51a30654be30
0405 .quad 0xd192e819d6ef5218,0xd69906245565a910
0406 .quad 0xf40e35855771202a,0x106aa07032bbd1b8
0407 .quad 0x19a4c116b8d2d0c8,0x1e376c085141ab53
0408 .quad 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8
0409 .quad 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb
0410 .quad 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3
0411 .quad 0x748f82ee5defb2fc,0x78a5636f43172f60
0412 .quad 0x84c87814a1f0ab72,0x8cc702081a6439ec
0413 .quad 0x90befffa23631e28,0xa4506cebde82bde9
0414 .quad 0xbef9a3f7b2c67915,0xc67178f2e372532b
0415 .quad 0xca273eceea26619c,0xd186b8c721c0c207
0416 .quad 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178
0417 .quad 0x06f067aa72176fba,0x0a637dc5a2c898a6
0418 .quad 0x113f9804bef90dae,0x1b710b35131c471b
0419 .quad 0x28db77f523047d84,0x32caab7b40c72493
0420 .quad 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c
0421 .quad 0x4cc5d4becb3e42b6,0x597f299cfc657e2a
0422 .quad 0x5fcb6fab3ad6faec,0x6c44198c4a475817
