x86/boot/cpuflags.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <linux/types.h>
0003 #include "bitops.h"
0004
0005 #include <asm/processor-flags.h>
0006 #include <asm/required-features.h>
0007 #include <asm/msr-index.h>
0008 #include "cpuflags.h"
0009
0010 struct cpu_features cpu;
0011 u32 cpu_vendor[3];
0012
0013 static bool loaded_flags;
0014
0015 static int has_fpu(void)
0016 {
0017     u16 fcw = -1, fsw = -1;
0018     unsigned long cr0;
0019
0020     asm volatile("mov %%cr0,%0" : "=r" (cr0));
0021     if (cr0 & (X86_CR0_EM|X86_CR0_TS)) {
0022         cr0 &= ~(X86_CR0_EM|X86_CR0_TS);
0023         asm volatile("mov %0,%%cr0" : : "r" (cr0));
0024     }
0025
0026     asm volatile("fninit ; fnstsw %0 ; fnstcw %1"
0027              : "+m" (fsw), "+m" (fcw));
0028
0029     return fsw == 0 && (fcw & 0x103f) == 0x003f;
0030 }
0031
0032 /*
0033  * For building the 16-bit code we want to explicitly specify 32-bit
0034  * push/pop operations, rather than just saying 'pushf' or 'popf' and
0035  * letting the compiler choose. But this is also included from the
0036  * compressed/ directory where it may be 64-bit code, and thus needs
0037  * to be 'pushfq' or 'popfq' in that case.
0038  */
0039 #ifdef __x86_64__
0040 #define PUSHF "pushfq"
0041 #define POPF "popfq"
0042 #else
0043 #define PUSHF "pushfl"
0044 #define POPF "popfl"
0045 #endif
0046
0047 int has_eflag(unsigned long mask)
0048 {
0049     unsigned long f0, f1;
0050
0051     asm volatile(PUSHF "    \n\t"
0052              PUSHF "    \n\t"
0053              "pop %0    \n\t"
0054              "mov %0,%1 \n\t"
0055              "xor %2,%1 \n\t"
0056              "push %1   \n\t"
0057              POPF " \n\t"
0058              PUSHF "    \n\t"
0059              "pop %1    \n\t"
0060              POPF
0061              : "=&r" (f0), "=&r" (f1)
0062              : "ri" (mask));
0063
0064     return !!((f0^f1) & mask);
0065 }
0066
0067 /* Handle x86_32 PIC using ebx. */
0068 #if defined(__i386__) && defined(__PIC__)
0069 # define EBX_REG "=r"
0070 #else
0071 # define EBX_REG "=b"
0072 #endif
0073
0074 void cpuid_count(u32 id, u32 count, u32 *a, u32 *b, u32 *c, u32 *d)
0075 {
0076     asm volatile(".ifnc %%ebx,%3 ; movl  %%ebx,%3 ; .endif  \n\t"
0077              "cpuid                 \n\t"
0078              ".ifnc %%ebx,%3 ; xchgl %%ebx,%3 ; .endif  \n\t"
0079             : "=a" (*a), "=c" (*c), "=d" (*d), EBX_REG (*b)
0080             : "a" (id), "c" (count)
0081     );
0082 }
0083
0084 #define cpuid(id, a, b, c, d) cpuid_count(id, 0, a, b, c, d)
0085
0086 void get_cpuflags(void)
0087 {
0088     u32 max_intel_level, max_amd_level;
0089     u32 tfms;
0090     u32 ignored;
0091
0092     if (loaded_flags)
0093         return;
0094     loaded_flags = true;
0095
0096     if (has_fpu())
0097         set_bit(X86_FEATURE_FPU, cpu.flags);
0098
0099     if (has_eflag(X86_EFLAGS_ID)) {
0100         cpuid(0x0, &max_intel_level, &cpu_vendor[0], &cpu_vendor[2],
0101               &cpu_vendor[1]);
0102
0103         if (max_intel_level >= 0x00000001 &&
0104             max_intel_level <= 0x0000ffff) {
0105             cpuid(0x1, &tfms, &ignored, &cpu.flags[4],
0106                   &cpu.flags[0]);
0107             cpu.level = (tfms >> 8) & 15;
0108             cpu.family = cpu.level;
0109             cpu.model = (tfms >> 4) & 15;
0110             if (cpu.level >= 6)
0111                 cpu.model += ((tfms >> 16) & 0xf) << 4;
0112         }
0113
0114         if (max_intel_level >= 0x00000007) {
0115             cpuid_count(0x00000007, 0, &ignored, &ignored,
0116                     &cpu.flags[16], &ignored);
0117         }
0118
0119         cpuid(0x80000000, &max_amd_level, &ignored, &ignored,
0120               &ignored);
0121
0122         if (max_amd_level >= 0x80000001 &&
0123             max_amd_level <= 0x8000ffff) {
0124             cpuid(0x80000001, &ignored, &ignored, &cpu.flags[6],
0125                   &cpu.flags[1]);
0126         }
0127     }
0128 }