include/asm/cache.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __UM_CACHE_H
0003 #define __UM_CACHE_H
0004
0005
0006 #if defined(CONFIG_UML_X86) && !defined(CONFIG_64BIT)
0007 # define L1_CACHE_SHIFT     (CONFIG_X86_L1_CACHE_SHIFT)
0008 #elif defined(CONFIG_UML_X86) /* 64-bit */
0009 # define L1_CACHE_SHIFT     6 /* Should be 7 on Intel */
0010 #else
0011 /* XXX: this was taken from x86, now it's completely random. Luckily only
0012  * affects SMP padding. */
0013 # define L1_CACHE_SHIFT     5
0014 #endif
0015
0016 #define L1_CACHE_BYTES      (1 << L1_CACHE_SHIFT)
0017
0018 #endif