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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * viking.S: High speed Viking cache/mmu operations
0004  *
0005  * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
0006  * Copyright (C) 1997,1998,1999  Jakub Jelinek  (jj@ultra.linux.cz)
0007  * Copyright (C) 1999  Pavel Semerad  (semerad@ss1000.ms.mff.cuni.cz)
0008  */
0009 
0010 #include <asm/ptrace.h>
0011 #include <asm/psr.h>
0012 #include <asm/asm-offsets.h>
0013 #include <asm/asi.h>
0014 #include <asm/mxcc.h>
0015 #include <asm/page.h>
0016 #include <asm/pgtable.h>
0017 #include <asm/pgtsrmmu.h>
0018 #include <asm/viking.h>
0019 
0020 #ifdef CONFIG_SMP
0021     .data
0022     .align  4
0023 sun4dsmp_flush_tlb_spin:
0024     .word   0
0025 #endif
0026 
0027     .text
0028     .align  4
0029 
0030     .globl  viking_flush_cache_all, viking_flush_cache_mm
0031     .globl  viking_flush_cache_range, viking_flush_cache_page
0032     .globl  viking_flush_page, viking_mxcc_flush_page
0033     .globl  viking_flush_page_for_dma, viking_flush_page_to_ram
0034     .globl  viking_flush_sig_insns
0035     .globl  viking_flush_tlb_all, viking_flush_tlb_mm
0036     .globl  viking_flush_tlb_range, viking_flush_tlb_page
0037 
0038 viking_flush_page:
0039     sethi   %hi(PAGE_OFFSET), %g2
0040     sub %o0, %g2, %g3
0041     srl %g3, 12, %g1        ! ppage >> 12
0042 
0043     clr %o1         ! set counter, 0 - 127
0044     sethi   %hi(PAGE_OFFSET + PAGE_SIZE - 0x80000000), %o3
0045     sethi   %hi(0x80000000), %o4
0046     sethi   %hi(VIKING_PTAG_VALID), %o5
0047     sethi   %hi(2*PAGE_SIZE), %o0
0048     sethi   %hi(PAGE_SIZE), %g7
0049     clr %o2         ! block counter, 0 - 3
0050 5:
0051     sll %o1, 5, %g4
0052     or  %g4, %o4, %g4       ! 0x80000000 | (set << 5)
0053 
0054     sll %o2, 26, %g5        ! block << 26
0055 6:
0056     or  %g5, %g4, %g5
0057     ldda    [%g5] ASI_M_DATAC_TAG, %g2
0058     cmp %g3, %g1        ! ptag == ppage?
0059     bne 7f
0060      inc    %o2
0061 
0062     andcc   %g2, %o5, %g0       ! ptag VALID?
0063     be  7f
0064      add    %g4, %o3, %g2       ! (PAGE_OFFSET + PAGE_SIZE) | (set << 5)
0065     ld  [%g2], %g3
0066     ld  [%g2 + %g7], %g3
0067     add %g2, %o0, %g2
0068     ld  [%g2], %g3
0069     ld  [%g2 + %g7], %g3
0070     add %g2, %o0, %g2
0071     ld  [%g2], %g3
0072     ld  [%g2 + %g7], %g3
0073     add %g2, %o0, %g2
0074     ld  [%g2], %g3
0075     b   8f
0076      ld [%g2 + %g7], %g3
0077 
0078 7:
0079     cmp %o2, 3
0080     ble 6b
0081      sll    %o2, 26, %g5            ! block << 26
0082 
0083 8:  inc %o1
0084     cmp %o1, 0x7f
0085     ble 5b
0086      clr    %o2
0087 
0088 9:  retl
0089      nop
0090 
0091 viking_mxcc_flush_page:
0092     sethi   %hi(PAGE_OFFSET), %g2
0093     sub %o0, %g2, %g3
0094     sub %g3, -PAGE_SIZE, %g3        ! ppage + PAGE_SIZE
0095     sethi   %hi(MXCC_SRCSTREAM), %o3    ! assume %hi(MXCC_SRCSTREAM) == %hi(MXCC_DESTSTREAM)
0096     mov 0x10, %g2           ! set cacheable bit
0097     or  %o3, %lo(MXCC_SRCSTREAM), %o2
0098     or  %o3, %lo(MXCC_DESSTREAM), %o3
0099     sub %g3, MXCC_STREAM_SIZE, %g3
0100 6:
0101     stda    %g2, [%o2] ASI_M_MXCC
0102     stda    %g2, [%o3] ASI_M_MXCC
0103     andncc  %g3, PAGE_MASK, %g0
0104     bne 6b
0105      sub    %g3, MXCC_STREAM_SIZE, %g3
0106 
0107 9:  retl
0108      nop
0109 
0110 viking_flush_cache_page:
0111 viking_flush_cache_range:
0112 #ifndef CONFIG_SMP
0113     ld  [%o0 + VMA_VM_MM], %o0
0114 #endif
0115 viking_flush_cache_mm:
0116 #ifndef CONFIG_SMP
0117     ld  [%o0 + AOFF_mm_context], %g1
0118     cmp %g1, -1
0119     bne viking_flush_cache_all
0120      nop
0121     b,a viking_flush_cache_out
0122 #endif
0123 viking_flush_cache_all:
0124     WINDOW_FLUSH(%g4, %g5)
0125 viking_flush_cache_out:
0126     retl
0127      nop
0128 
0129 viking_flush_tlb_all:
0130     mov 0x400, %g1
0131     retl
0132      sta    %g0, [%g1] ASI_M_FLUSH_PROBE
0133 
0134 viking_flush_tlb_mm:
0135     mov SRMMU_CTX_REG, %g1
0136     ld  [%o0 + AOFF_mm_context], %o1
0137     lda [%g1] ASI_M_MMUREGS, %g5
0138 #ifndef CONFIG_SMP
0139     cmp %o1, -1
0140     be  1f
0141 #endif
0142     mov 0x300, %g2
0143     sta %o1, [%g1] ASI_M_MMUREGS
0144     sta %g0, [%g2] ASI_M_FLUSH_PROBE
0145     retl
0146      sta    %g5, [%g1] ASI_M_MMUREGS
0147 #ifndef CONFIG_SMP
0148 1:  retl
0149      nop
0150 #endif
0151 
0152 viking_flush_tlb_range:
0153     ld  [%o0 + VMA_VM_MM], %o0
0154     mov SRMMU_CTX_REG, %g1
0155     ld  [%o0 + AOFF_mm_context], %o3
0156     lda [%g1] ASI_M_MMUREGS, %g5
0157 #ifndef CONFIG_SMP
0158     cmp %o3, -1
0159     be  2f
0160 #endif
0161     sethi   %hi(~((1 << PGDIR_SHIFT) - 1)), %o4
0162     sta %o3, [%g1] ASI_M_MMUREGS
0163     and %o1, %o4, %o1
0164     add %o1, 0x200, %o1
0165     sta %g0, [%o1] ASI_M_FLUSH_PROBE
0166 1:  sub %o1, %o4, %o1
0167     cmp %o1, %o2
0168     blu,a   1b
0169      sta    %g0, [%o1] ASI_M_FLUSH_PROBE
0170     retl
0171      sta    %g5, [%g1] ASI_M_MMUREGS
0172 #ifndef CONFIG_SMP
0173 2:  retl
0174      nop
0175 #endif
0176 
0177 viking_flush_tlb_page:
0178     ld  [%o0 + VMA_VM_MM], %o0
0179     mov SRMMU_CTX_REG, %g1
0180     ld  [%o0 + AOFF_mm_context], %o3
0181     lda [%g1] ASI_M_MMUREGS, %g5
0182 #ifndef CONFIG_SMP
0183     cmp %o3, -1
0184     be  1f
0185 #endif
0186     and %o1, PAGE_MASK, %o1
0187     sta %o3, [%g1] ASI_M_MMUREGS
0188     sta %g0, [%o1] ASI_M_FLUSH_PROBE
0189     retl
0190      sta    %g5, [%g1] ASI_M_MMUREGS
0191 #ifndef CONFIG_SMP
0192 1:  retl
0193      nop
0194 #endif
0195 
0196 viking_flush_page_to_ram:
0197 viking_flush_page_for_dma:
0198 viking_flush_sig_insns:
0199     retl
0200      nop
0201 
0202 #ifdef CONFIG_SMP
0203     .globl  sun4dsmp_flush_tlb_all, sun4dsmp_flush_tlb_mm
0204     .globl  sun4dsmp_flush_tlb_range, sun4dsmp_flush_tlb_page
0205 sun4dsmp_flush_tlb_all:
0206     sethi   %hi(sun4dsmp_flush_tlb_spin), %g3
0207 1:  ldstub  [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
0208     tst %g5
0209     bne 2f
0210      mov    0x400, %g1
0211     sta %g0, [%g1] ASI_M_FLUSH_PROBE
0212     retl
0213      stb    %g0, [%g3 + %lo(sun4dsmp_flush_tlb_spin)]
0214 2:  tst %g5
0215     bne,a   2b
0216      ldub   [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
0217     b,a 1b
0218 
0219 sun4dsmp_flush_tlb_mm:
0220     sethi   %hi(sun4dsmp_flush_tlb_spin), %g3
0221 1:  ldstub  [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
0222     tst %g5
0223     bne 2f
0224      mov    SRMMU_CTX_REG, %g1
0225     ld  [%o0 + AOFF_mm_context], %o1
0226     lda [%g1] ASI_M_MMUREGS, %g5
0227     mov 0x300, %g2
0228     sta %o1, [%g1] ASI_M_MMUREGS
0229     sta %g0, [%g2] ASI_M_FLUSH_PROBE
0230     sta %g5, [%g1] ASI_M_MMUREGS
0231     retl
0232      stb    %g0, [%g3 + %lo(sun4dsmp_flush_tlb_spin)]
0233 2:  tst %g5
0234     bne,a   2b
0235      ldub   [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
0236     b,a 1b
0237 
0238 sun4dsmp_flush_tlb_range:
0239     sethi   %hi(sun4dsmp_flush_tlb_spin), %g3
0240 1:  ldstub  [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
0241     tst %g5
0242     bne 3f
0243      mov    SRMMU_CTX_REG, %g1
0244     ld  [%o0 + VMA_VM_MM], %o0
0245     ld  [%o0 + AOFF_mm_context], %o3
0246     lda [%g1] ASI_M_MMUREGS, %g5
0247     sethi   %hi(~((1 << PGDIR_SHIFT) - 1)), %o4
0248     sta %o3, [%g1] ASI_M_MMUREGS
0249     and %o1, %o4, %o1
0250     add %o1, 0x200, %o1
0251     sta %g0, [%o1] ASI_M_FLUSH_PROBE
0252 2:  sub %o1, %o4, %o1
0253     cmp %o1, %o2
0254     blu,a   2b
0255      sta    %g0, [%o1] ASI_M_FLUSH_PROBE
0256     sta %g5, [%g1] ASI_M_MMUREGS
0257     retl
0258      stb    %g0, [%g3 + %lo(sun4dsmp_flush_tlb_spin)]
0259 3:  tst %g5
0260     bne,a   3b
0261      ldub   [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
0262     b,a 1b
0263 
0264 sun4dsmp_flush_tlb_page:
0265     sethi   %hi(sun4dsmp_flush_tlb_spin), %g3
0266 1:  ldstub  [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
0267     tst %g5
0268     bne 2f
0269      mov    SRMMU_CTX_REG, %g1
0270     ld  [%o0 + VMA_VM_MM], %o0
0271     ld  [%o0 + AOFF_mm_context], %o3
0272     lda [%g1] ASI_M_MMUREGS, %g5
0273     and %o1, PAGE_MASK, %o1
0274     sta %o3, [%g1] ASI_M_MMUREGS
0275     sta %g0, [%o1] ASI_M_FLUSH_PROBE
0276     sta %g5, [%g1] ASI_M_MMUREGS
0277     retl
0278      stb    %g0, [%g3 + %lo(sun4dsmp_flush_tlb_spin)]
0279 2:  tst %g5
0280     bne,a   2b
0281      ldub   [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
0282     b,a 1b
0283      nop
0284 #endif
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