sparc/mm/tsunami.S

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * tsunami.S: High speed MicroSparc-I mmu/cache operations.
0004  *
0005  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
0006  */
0007
0008 #include <asm/ptrace.h>
0009 #include <asm/asm-offsets.h>
0010 #include <asm/psr.h>
0011 #include <asm/asi.h>
0012 #include <asm/page.h>
0013 #include <asm/pgtsrmmu.h>
0014
0015     .text
0016     .align  4
0017
0018     .globl  tsunami_flush_cache_all, tsunami_flush_cache_mm
0019     .globl  tsunami_flush_cache_range, tsunami_flush_cache_page
0020     .globl  tsunami_flush_page_to_ram, tsunami_flush_page_for_dma
0021     .globl  tsunami_flush_sig_insns
0022     .globl  tsunami_flush_tlb_all, tsunami_flush_tlb_mm
0023     .globl  tsunami_flush_tlb_range, tsunami_flush_tlb_page
0024
0025     /* Sliiick... */
0026 tsunami_flush_cache_page:
0027 tsunami_flush_cache_range:
0028     ld  [%o0 + VMA_VM_MM], %o0
0029 tsunami_flush_cache_mm:
0030     ld  [%o0 + AOFF_mm_context], %g2
0031     cmp %g2, -1
0032     be  tsunami_flush_cache_out
0033 tsunami_flush_cache_all:
0034     WINDOW_FLUSH(%g4, %g5)
0035 tsunami_flush_page_for_dma:
0036     sta %g0, [%g0] ASI_M_IC_FLCLEAR
0037     sta %g0, [%g0] ASI_M_DC_FLCLEAR
0038 tsunami_flush_cache_out:
0039 tsunami_flush_page_to_ram:
0040     retl
0041      nop
0042
0043 tsunami_flush_sig_insns:
0044     flush   %o1
0045     retl
0046      flush  %o1 + 4
0047
0048     /* More slick stuff... */
0049 tsunami_flush_tlb_range:
0050     ld  [%o0 + VMA_VM_MM], %o0
0051 tsunami_flush_tlb_mm:
0052     ld  [%o0 + AOFF_mm_context], %g2
0053     cmp %g2, -1
0054     be  tsunami_flush_tlb_out
0055 tsunami_flush_tlb_all:
0056      mov    0x400, %o1
0057     sta %g0, [%o1] ASI_M_FLUSH_PROBE
0058     nop
0059     nop
0060     nop
0061     nop
0062     nop
0063 tsunami_flush_tlb_out:
0064     retl
0065      nop
0066
0067     /* This one can be done in a fine grained manner... */
0068 tsunami_flush_tlb_page:
0069     ld  [%o0 + VMA_VM_MM], %o0
0070     mov SRMMU_CTX_REG, %g1
0071     ld  [%o0 + AOFF_mm_context], %o3
0072     andn    %o1, (PAGE_SIZE - 1), %o1
0073     cmp %o3, -1
0074     be  tsunami_flush_tlb_page_out
0075      lda    [%g1] ASI_M_MMUREGS, %g5
0076     sta %o3, [%g1] ASI_M_MMUREGS
0077     sta %g0, [%o1] ASI_M_FLUSH_PROBE
0078     nop
0079     nop
0080     nop
0081     nop
0082     nop
0083 tsunami_flush_tlb_page_out:
0084     retl
0085      sta    %g5, [%g1] ASI_M_MMUREGS
0086
0087 #define MIRROR_BLOCK(dst, src, offset, t0, t1, t2, t3) \
0088     ldd [src + offset + 0x18], t0; \
0089     std t0, [dst + offset + 0x18]; \
0090     ldd [src + offset + 0x10], t2; \
0091     std t2, [dst + offset + 0x10]; \
0092     ldd [src + offset + 0x08], t0; \
0093     std t0, [dst + offset + 0x08]; \
0094     ldd [src + offset + 0x00], t2; \
0095     std t2, [dst + offset + 0x00];
0096
0097 tsunami_copy_1page:
0098 /* NOTE: This routine has to be shorter than 70insns --jj */
0099     or  %g0, (PAGE_SIZE >> 8), %g1
0100 1:
0101     MIRROR_BLOCK(%o0, %o1, 0x00, %o2, %o3, %o4, %o5)
0102     MIRROR_BLOCK(%o0, %o1, 0x20, %o2, %o3, %o4, %o5)
0103     MIRROR_BLOCK(%o0, %o1, 0x40, %o2, %o3, %o4, %o5)
0104     MIRROR_BLOCK(%o0, %o1, 0x60, %o2, %o3, %o4, %o5)
0105     MIRROR_BLOCK(%o0, %o1, 0x80, %o2, %o3, %o4, %o5)
0106     MIRROR_BLOCK(%o0, %o1, 0xa0, %o2, %o3, %o4, %o5)
0107     MIRROR_BLOCK(%o0, %o1, 0xc0, %o2, %o3, %o4, %o5)
0108     MIRROR_BLOCK(%o0, %o1, 0xe0, %o2, %o3, %o4, %o5)
0109     subcc   %g1, 1, %g1
0110     add %o0, 0x100, %o0
0111     bne 1b
0112      add    %o1, 0x100, %o1
0113
0114     .globl  tsunami_setup_blockops
0115 tsunami_setup_blockops:
0116     sethi   %hi(__copy_1page), %o0
0117     or  %o0, %lo(__copy_1page), %o0
0118     sethi   %hi(tsunami_copy_1page), %o1
0119     or  %o1, %lo(tsunami_copy_1page), %o1
0120     sethi   %hi(tsunami_setup_blockops), %o2
0121     or  %o2, %lo(tsunami_setup_blockops), %o2
0122     ld  [%o1], %o4
0123 1:  add %o1, 4, %o1
0124     st  %o4, [%o0]
0125     add %o0, 4, %o0
0126     cmp %o1, %o2
0127     bne 1b
0128     ld  [%o1], %o4
0129     sta %g0, [%g0] ASI_M_IC_FLCLEAR
0130     sta %g0, [%g0] ASI_M_DC_FLCLEAR
0131     retl
0132      nop