sparc/mm/swift.S

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * swift.S: MicroSparc-II mmu/cache operations.
0004  *
0005  * Copyright (C) 1999 David S. Miller (davem@redhat.com)
0006  */
0007
0008 #include <asm/psr.h>
0009 #include <asm/asi.h>
0010 #include <asm/page.h>
0011 #include <asm/pgtsrmmu.h>
0012 #include <asm/asm-offsets.h>
0013
0014     .text
0015     .align  4
0016
0017 #if 1   /* XXX screw this, I can't get the VAC flushes working
0018      * XXX reliably... -DaveM
0019      */
0020     .globl  swift_flush_cache_all, swift_flush_cache_mm
0021     .globl  swift_flush_cache_range, swift_flush_cache_page
0022     .globl  swift_flush_page_for_dma
0023     .globl  swift_flush_page_to_ram
0024
0025 swift_flush_cache_all:
0026 swift_flush_cache_mm:
0027 swift_flush_cache_range:
0028 swift_flush_cache_page:
0029 swift_flush_page_for_dma:
0030 swift_flush_page_to_ram:
0031     sethi   %hi(0x2000), %o0
0032 1:  subcc   %o0, 0x10, %o0
0033     add %o0, %o0, %o1
0034     sta %g0, [%o0] ASI_M_DATAC_TAG
0035     bne 1b
0036      sta    %g0, [%o1] ASI_M_TXTC_TAG
0037     retl
0038      nop
0039 #else
0040
0041     .globl  swift_flush_cache_all
0042 swift_flush_cache_all:
0043     WINDOW_FLUSH(%g4, %g5)
0044
0045     /* Just clear out all the tags. */
0046     sethi   %hi(16 * 1024), %o0
0047 1:  subcc   %o0, 16, %o0
0048     sta %g0, [%o0] ASI_M_TXTC_TAG
0049     bne 1b
0050      sta    %g0, [%o0] ASI_M_DATAC_TAG
0051     retl
0052      nop
0053
0054     .globl  swift_flush_cache_mm
0055 swift_flush_cache_mm:
0056     ld  [%o0 + AOFF_mm_context], %g2
0057     cmp %g2, -1
0058     be  swift_flush_cache_mm_out
0059     WINDOW_FLUSH(%g4, %g5)
0060     rd  %psr, %g1
0061     andn    %g1, PSR_ET, %g3
0062     wr  %g3, 0x0, %psr
0063     nop
0064     nop
0065     mov SRMMU_CTX_REG, %g7
0066     lda [%g7] ASI_M_MMUREGS, %g5
0067     sta %g2, [%g7] ASI_M_MMUREGS
0068
0069 #if 1
0070     sethi   %hi(0x2000), %o0
0071 1:  subcc   %o0, 0x10, %o0
0072     sta %g0, [%o0] ASI_M_FLUSH_CTX
0073     bne 1b
0074      nop
0075 #else
0076     clr %o0
0077     or  %g0, 2048, %g7
0078     or  %g0, 2048, %o1
0079     add %o1, 2048, %o2
0080     add %o2, 2048, %o3
0081     mov 16, %o4
0082     add %o4, 2048, %o5
0083     add %o5, 2048, %g2
0084     add %g2, 2048, %g3
0085 1:  sta %g0, [%o0      ] ASI_M_FLUSH_CTX
0086     sta %g0, [%o0 + %o1] ASI_M_FLUSH_CTX
0087     sta %g0, [%o0 + %o2] ASI_M_FLUSH_CTX
0088     sta %g0, [%o0 + %o3] ASI_M_FLUSH_CTX
0089     sta %g0, [%o0 + %o4] ASI_M_FLUSH_CTX
0090     sta %g0, [%o0 + %o5] ASI_M_FLUSH_CTX
0091     sta %g0, [%o0 + %g2] ASI_M_FLUSH_CTX
0092     sta %g0, [%o0 + %g3] ASI_M_FLUSH_CTX
0093     subcc   %g7, 32, %g7
0094     bne 1b
0095      add    %o0, 32, %o0
0096 #endif
0097
0098     mov SRMMU_CTX_REG, %g7
0099     sta %g5, [%g7] ASI_M_MMUREGS
0100     wr  %g1, 0x0, %psr
0101     nop
0102     nop
0103 swift_flush_cache_mm_out:
0104     retl
0105      nop
0106
0107     .globl  swift_flush_cache_range
0108 swift_flush_cache_range:
0109     ld  [%o0 + VMA_VM_MM], %o0
0110     sub %o2, %o1, %o2
0111     sethi   %hi(4096), %o3
0112     cmp %o2, %o3
0113     bgu swift_flush_cache_mm
0114      nop
0115     b   70f
0116      nop
0117
0118     .globl  swift_flush_cache_page
0119 swift_flush_cache_page:
0120     ld  [%o0 + VMA_VM_MM], %o0
0121 70:
0122     ld  [%o0 + AOFF_mm_context], %g2
0123     cmp %g2, -1
0124     be  swift_flush_cache_page_out
0125     WINDOW_FLUSH(%g4, %g5)
0126     rd  %psr, %g1
0127     andn    %g1, PSR_ET, %g3
0128     wr  %g3, 0x0, %psr
0129     nop
0130     nop
0131     mov SRMMU_CTX_REG, %g7
0132     lda [%g7] ASI_M_MMUREGS, %g5
0133     sta %g2, [%g7] ASI_M_MMUREGS
0134
0135     andn    %o1, (PAGE_SIZE - 1), %o1
0136 #if 1
0137     sethi   %hi(0x1000), %o0
0138 1:  subcc   %o0, 0x10, %o0
0139     sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
0140     bne 1b
0141      nop
0142 #else
0143     or  %g0, 512, %g7
0144     or  %g0, 512, %o0
0145     add %o0, 512, %o2
0146     add %o2, 512, %o3
0147     add %o3, 512, %o4
0148     add %o4, 512, %o5
0149     add %o5, 512, %g3
0150     add %g3, 512, %g4
0151 1:  sta %g0, [%o1      ] ASI_M_FLUSH_PAGE
0152     sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
0153     sta %g0, [%o1 + %o2] ASI_M_FLUSH_PAGE
0154     sta %g0, [%o1 + %o3] ASI_M_FLUSH_PAGE
0155     sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
0156     sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
0157     sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
0158     sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
0159     subcc   %g7, 16, %g7
0160     bne 1b
0161      add    %o1, 16, %o1
0162 #endif
0163
0164     mov SRMMU_CTX_REG, %g7
0165     sta %g5, [%g7] ASI_M_MMUREGS
0166     wr  %g1, 0x0, %psr
0167     nop
0168     nop
0169 swift_flush_cache_page_out:
0170     retl
0171      nop
0172
0173     /* Swift is write-thru, however it is not
0174      * I/O nor TLB-walk coherent.  Also it has
0175      * caches which are virtually indexed and tagged.
0176      */
0177     .globl  swift_flush_page_for_dma
0178     .globl  swift_flush_page_to_ram
0179 swift_flush_page_for_dma:
0180 swift_flush_page_to_ram:
0181     andn    %o0, (PAGE_SIZE - 1), %o1
0182 #if 1
0183     sethi   %hi(0x1000), %o0
0184 1:  subcc   %o0, 0x10, %o0
0185     sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
0186     bne 1b
0187      nop
0188 #else
0189     or  %g0, 512, %g7
0190     or  %g0, 512, %o0
0191     add %o0, 512, %o2
0192     add %o2, 512, %o3
0193     add %o3, 512, %o4
0194     add %o4, 512, %o5
0195     add %o5, 512, %g3
0196     add %g3, 512, %g4
0197 1:  sta %g0, [%o1      ] ASI_M_FLUSH_PAGE
0198     sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
0199     sta %g0, [%o1 + %o2] ASI_M_FLUSH_PAGE
0200     sta %g0, [%o1 + %o3] ASI_M_FLUSH_PAGE
0201     sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
0202     sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
0203     sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
0204     sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
0205     subcc   %g7, 16, %g7
0206     bne 1b
0207      add    %o1, 16, %o1
0208 #endif
0209     retl
0210      nop
0211 #endif
0212
0213     .globl  swift_flush_sig_insns
0214 swift_flush_sig_insns:
0215     flush   %o1
0216     retl
0217      flush  %o1 + 4
0218
0219     .globl  swift_flush_tlb_mm
0220     .globl  swift_flush_tlb_range
0221     .globl  swift_flush_tlb_all
0222 swift_flush_tlb_range:
0223     ld  [%o0 + VMA_VM_MM], %o0
0224 swift_flush_tlb_mm:
0225     ld  [%o0 + AOFF_mm_context], %g2
0226     cmp %g2, -1
0227     be  swift_flush_tlb_all_out
0228 swift_flush_tlb_all:
0229     mov 0x400, %o1
0230     sta %g0, [%o1] ASI_M_FLUSH_PROBE
0231 swift_flush_tlb_all_out:
0232     retl
0233      nop
0234
0235     .globl  swift_flush_tlb_page
0236 swift_flush_tlb_page:
0237     ld  [%o0 + VMA_VM_MM], %o0
0238     mov SRMMU_CTX_REG, %g1
0239     ld  [%o0 + AOFF_mm_context], %o3
0240     andn    %o1, (PAGE_SIZE - 1), %o1
0241     cmp %o3, -1
0242     be  swift_flush_tlb_page_out
0243      nop
0244 #if 1
0245     mov 0x400, %o1
0246     sta %g0, [%o1] ASI_M_FLUSH_PROBE
0247 #else
0248     lda [%g1] ASI_M_MMUREGS, %g5
0249     sta %o3, [%g1] ASI_M_MMUREGS
0250     sta %g0, [%o1] ASI_M_FLUSH_PAGE /* rem. virt. cache. prot. */
0251     sta %g0, [%o1] ASI_M_FLUSH_PROBE
0252     sta %g5, [%g1] ASI_M_MMUREGS
0253 #endif
0254 swift_flush_tlb_page_out:
0255     retl
0256      nop