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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * srmmu.c:  SRMMU specific routines for memory management.
0004  *
0005  * Copyright (C) 1995 David S. Miller  (davem@caip.rutgers.edu)
0006  * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
0007  * Copyright (C) 1996 Eddie C. Dost    (ecd@skynet.be)
0008  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
0009  * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
0010  */
0011 
0012 #include <linux/seq_file.h>
0013 #include <linux/spinlock.h>
0014 #include <linux/memblock.h>
0015 #include <linux/pagemap.h>
0016 #include <linux/vmalloc.h>
0017 #include <linux/kdebug.h>
0018 #include <linux/export.h>
0019 #include <linux/kernel.h>
0020 #include <linux/init.h>
0021 #include <linux/log2.h>
0022 #include <linux/gfp.h>
0023 #include <linux/fs.h>
0024 #include <linux/mm.h>
0025 
0026 #include <asm/mmu_context.h>
0027 #include <asm/cacheflush.h>
0028 #include <asm/tlbflush.h>
0029 #include <asm/io-unit.h>
0030 #include <asm/pgalloc.h>
0031 #include <asm/pgtable.h>
0032 #include <asm/bitext.h>
0033 #include <asm/vaddrs.h>
0034 #include <asm/cache.h>
0035 #include <asm/traps.h>
0036 #include <asm/oplib.h>
0037 #include <asm/mbus.h>
0038 #include <asm/page.h>
0039 #include <asm/asi.h>
0040 #include <asm/smp.h>
0041 #include <asm/io.h>
0042 
0043 /* Now the cpu specific definitions. */
0044 #include <asm/turbosparc.h>
0045 #include <asm/tsunami.h>
0046 #include <asm/viking.h>
0047 #include <asm/swift.h>
0048 #include <asm/leon.h>
0049 #include <asm/mxcc.h>
0050 #include <asm/ross.h>
0051 
0052 #include "mm_32.h"
0053 
0054 enum mbus_module srmmu_modtype;
0055 static unsigned int hwbug_bitmask;
0056 int vac_cache_size;
0057 EXPORT_SYMBOL(vac_cache_size);
0058 int vac_line_size;
0059 
0060 extern struct resource sparc_iomap;
0061 
0062 extern unsigned long last_valid_pfn;
0063 
0064 static pgd_t *srmmu_swapper_pg_dir;
0065 
0066 const struct sparc32_cachetlb_ops *sparc32_cachetlb_ops;
0067 EXPORT_SYMBOL(sparc32_cachetlb_ops);
0068 
0069 #ifdef CONFIG_SMP
0070 const struct sparc32_cachetlb_ops *local_ops;
0071 
0072 #define FLUSH_BEGIN(mm)
0073 #define FLUSH_END
0074 #else
0075 #define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) {
0076 #define FLUSH_END   }
0077 #endif
0078 
0079 int flush_page_for_dma_global = 1;
0080 
0081 char *srmmu_name;
0082 
0083 ctxd_t *srmmu_ctx_table_phys;
0084 static ctxd_t *srmmu_context_table;
0085 
0086 int viking_mxcc_present;
0087 static DEFINE_SPINLOCK(srmmu_context_spinlock);
0088 
0089 static int is_hypersparc;
0090 
0091 static int srmmu_cache_pagetables;
0092 
0093 /* these will be initialized in srmmu_nocache_calcsize() */
0094 static unsigned long srmmu_nocache_size;
0095 static unsigned long srmmu_nocache_end;
0096 
0097 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
0098 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
0099 
0100 /* The context table is a nocache user with the biggest alignment needs. */
0101 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
0102 
0103 void *srmmu_nocache_pool;
0104 static struct bit_map srmmu_nocache_map;
0105 
0106 static inline int srmmu_pmd_none(pmd_t pmd)
0107 { return !(pmd_val(pmd) & 0xFFFFFFF); }
0108 
0109 /* XXX should we hyper_flush_whole_icache here - Anton */
0110 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
0111 {
0112     pte_t pte;
0113 
0114     pte = __pte((SRMMU_ET_PTD | (__nocache_pa(pgdp) >> 4)));
0115     set_pte((pte_t *)ctxp, pte);
0116 }
0117 
0118 /*
0119  * Locations of MSI Registers.
0120  */
0121 #define MSI_MBUS_ARBEN  0xe0001008  /* MBus Arbiter Enable register */
0122 
0123 /*
0124  * Useful bits in the MSI Registers.
0125  */
0126 #define MSI_ASYNC_MODE  0x80000000  /* Operate the MSI asynchronously */
0127 
0128 static void msi_set_sync(void)
0129 {
0130     __asm__ __volatile__ ("lda [%0] %1, %%g3\n\t"
0131                   "andn %%g3, %2, %%g3\n\t"
0132                   "sta %%g3, [%0] %1\n\t" : :
0133                   "r" (MSI_MBUS_ARBEN),
0134                   "i" (ASI_M_CTL), "r" (MSI_ASYNC_MODE) : "g3");
0135 }
0136 
0137 void pmd_set(pmd_t *pmdp, pte_t *ptep)
0138 {
0139     unsigned long ptp = __nocache_pa(ptep) >> 4;
0140     set_pte((pte_t *)&pmd_val(*pmdp), __pte(SRMMU_ET_PTD | ptp));
0141 }
0142 
0143 /*
0144  * size: bytes to allocate in the nocache area.
0145  * align: bytes, number to align at.
0146  * Returns the virtual address of the allocated area.
0147  */
0148 static void *__srmmu_get_nocache(int size, int align)
0149 {
0150     int offset, minsz = 1 << SRMMU_NOCACHE_BITMAP_SHIFT;
0151     unsigned long addr;
0152 
0153     if (size < minsz) {
0154         printk(KERN_ERR "Size 0x%x too small for nocache request\n",
0155                size);
0156         size = minsz;
0157     }
0158     if (size & (minsz - 1)) {
0159         printk(KERN_ERR "Size 0x%x unaligned in nocache request\n",
0160                size);
0161         size += minsz - 1;
0162     }
0163     BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
0164 
0165     offset = bit_map_string_get(&srmmu_nocache_map,
0166                     size >> SRMMU_NOCACHE_BITMAP_SHIFT,
0167                     align >> SRMMU_NOCACHE_BITMAP_SHIFT);
0168     if (offset == -1) {
0169         printk(KERN_ERR "srmmu: out of nocache %d: %d/%d\n",
0170                size, (int) srmmu_nocache_size,
0171                srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
0172         return NULL;
0173     }
0174 
0175     addr = SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT);
0176     return (void *)addr;
0177 }
0178 
0179 void *srmmu_get_nocache(int size, int align)
0180 {
0181     void *tmp;
0182 
0183     tmp = __srmmu_get_nocache(size, align);
0184 
0185     if (tmp)
0186         memset(tmp, 0, size);
0187 
0188     return tmp;
0189 }
0190 
0191 void srmmu_free_nocache(void *addr, int size)
0192 {
0193     unsigned long vaddr;
0194     int offset;
0195 
0196     vaddr = (unsigned long)addr;
0197     if (vaddr < SRMMU_NOCACHE_VADDR) {
0198         printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
0199             vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
0200         BUG();
0201     }
0202     if (vaddr + size > srmmu_nocache_end) {
0203         printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
0204             vaddr, srmmu_nocache_end);
0205         BUG();
0206     }
0207     if (!is_power_of_2(size)) {
0208         printk("Size 0x%x is not a power of 2\n", size);
0209         BUG();
0210     }
0211     if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
0212         printk("Size 0x%x is too small\n", size);
0213         BUG();
0214     }
0215     if (vaddr & (size - 1)) {
0216         printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
0217         BUG();
0218     }
0219 
0220     offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
0221     size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
0222 
0223     bit_map_clear(&srmmu_nocache_map, offset, size);
0224 }
0225 
0226 static void srmmu_early_allocate_ptable_skeleton(unsigned long start,
0227                          unsigned long end);
0228 
0229 /* Return how much physical memory we have.  */
0230 static unsigned long __init probe_memory(void)
0231 {
0232     unsigned long total = 0;
0233     int i;
0234 
0235     for (i = 0; sp_banks[i].num_bytes; i++)
0236         total += sp_banks[i].num_bytes;
0237 
0238     return total;
0239 }
0240 
0241 /*
0242  * Reserve nocache dynamically proportionally to the amount of
0243  * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
0244  */
0245 static void __init srmmu_nocache_calcsize(void)
0246 {
0247     unsigned long sysmemavail = probe_memory() / 1024;
0248     int srmmu_nocache_npages;
0249 
0250     srmmu_nocache_npages =
0251         sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
0252 
0253  /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
0254     // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
0255     if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
0256         srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
0257 
0258     /* anything above 1280 blows up */
0259     if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
0260         srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
0261 
0262     srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
0263     srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
0264 }
0265 
0266 static void __init srmmu_nocache_init(void)
0267 {
0268     void *srmmu_nocache_bitmap;
0269     unsigned int bitmap_bits;
0270     pgd_t *pgd;
0271     p4d_t *p4d;
0272     pud_t *pud;
0273     pmd_t *pmd;
0274     pte_t *pte;
0275     unsigned long paddr, vaddr;
0276     unsigned long pteval;
0277 
0278     bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
0279 
0280     srmmu_nocache_pool = memblock_alloc(srmmu_nocache_size,
0281                         SRMMU_NOCACHE_ALIGN_MAX);
0282     if (!srmmu_nocache_pool)
0283         panic("%s: Failed to allocate %lu bytes align=0x%x\n",
0284               __func__, srmmu_nocache_size, SRMMU_NOCACHE_ALIGN_MAX);
0285     memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
0286 
0287     srmmu_nocache_bitmap =
0288         memblock_alloc(BITS_TO_LONGS(bitmap_bits) * sizeof(long),
0289                    SMP_CACHE_BYTES);
0290     if (!srmmu_nocache_bitmap)
0291         panic("%s: Failed to allocate %zu bytes\n", __func__,
0292               BITS_TO_LONGS(bitmap_bits) * sizeof(long));
0293     bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
0294 
0295     srmmu_swapper_pg_dir = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
0296     memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
0297     init_mm.pgd = srmmu_swapper_pg_dir;
0298 
0299     srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
0300 
0301     paddr = __pa((unsigned long)srmmu_nocache_pool);
0302     vaddr = SRMMU_NOCACHE_VADDR;
0303 
0304     while (vaddr < srmmu_nocache_end) {
0305         pgd = pgd_offset_k(vaddr);
0306         p4d = p4d_offset(pgd, vaddr);
0307         pud = pud_offset(p4d, vaddr);
0308         pmd = pmd_offset(__nocache_fix(pud), vaddr);
0309         pte = pte_offset_kernel(__nocache_fix(pmd), vaddr);
0310 
0311         pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
0312 
0313         if (srmmu_cache_pagetables)
0314             pteval |= SRMMU_CACHE;
0315 
0316         set_pte(__nocache_fix(pte), __pte(pteval));
0317 
0318         vaddr += PAGE_SIZE;
0319         paddr += PAGE_SIZE;
0320     }
0321 
0322     flush_cache_all();
0323     flush_tlb_all();
0324 }
0325 
0326 pgd_t *get_pgd_fast(void)
0327 {
0328     pgd_t *pgd = NULL;
0329 
0330     pgd = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
0331     if (pgd) {
0332         pgd_t *init = pgd_offset_k(0);
0333         memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
0334         memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
0335                         (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
0336     }
0337 
0338     return pgd;
0339 }
0340 
0341 /*
0342  * Hardware needs alignment to 256 only, but we align to whole page size
0343  * to reduce fragmentation problems due to the buddy principle.
0344  * XXX Provide actual fragmentation statistics in /proc.
0345  *
0346  * Alignments up to the page size are the same for physical and virtual
0347  * addresses of the nocache area.
0348  */
0349 pgtable_t pte_alloc_one(struct mm_struct *mm)
0350 {
0351     pte_t *ptep;
0352     struct page *page;
0353 
0354     if (!(ptep = pte_alloc_one_kernel(mm)))
0355         return NULL;
0356     page = pfn_to_page(__nocache_pa((unsigned long)ptep) >> PAGE_SHIFT);
0357     spin_lock(&mm->page_table_lock);
0358     if (page_ref_inc_return(page) == 2 && !pgtable_pte_page_ctor(page)) {
0359         page_ref_dec(page);
0360         ptep = NULL;
0361     }
0362     spin_unlock(&mm->page_table_lock);
0363 
0364     return ptep;
0365 }
0366 
0367 void pte_free(struct mm_struct *mm, pgtable_t ptep)
0368 {
0369     struct page *page;
0370 
0371     page = pfn_to_page(__nocache_pa((unsigned long)ptep) >> PAGE_SHIFT);
0372     spin_lock(&mm->page_table_lock);
0373     if (page_ref_dec_return(page) == 1)
0374         pgtable_pte_page_dtor(page);
0375     spin_unlock(&mm->page_table_lock);
0376 
0377     srmmu_free_nocache(ptep, SRMMU_PTE_TABLE_SIZE);
0378 }
0379 
0380 /* context handling - a dynamically sized pool is used */
0381 #define NO_CONTEXT  -1
0382 
0383 struct ctx_list {
0384     struct ctx_list *next;
0385     struct ctx_list *prev;
0386     unsigned int ctx_number;
0387     struct mm_struct *ctx_mm;
0388 };
0389 
0390 static struct ctx_list *ctx_list_pool;
0391 static struct ctx_list ctx_free;
0392 static struct ctx_list ctx_used;
0393 
0394 /* At boot time we determine the number of contexts */
0395 static int num_contexts;
0396 
0397 static inline void remove_from_ctx_list(struct ctx_list *entry)
0398 {
0399     entry->next->prev = entry->prev;
0400     entry->prev->next = entry->next;
0401 }
0402 
0403 static inline void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry)
0404 {
0405     entry->next = head;
0406     (entry->prev = head->prev)->next = entry;
0407     head->prev = entry;
0408 }
0409 #define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry)
0410 #define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry)
0411 
0412 
0413 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
0414 {
0415     struct ctx_list *ctxp;
0416 
0417     ctxp = ctx_free.next;
0418     if (ctxp != &ctx_free) {
0419         remove_from_ctx_list(ctxp);
0420         add_to_used_ctxlist(ctxp);
0421         mm->context = ctxp->ctx_number;
0422         ctxp->ctx_mm = mm;
0423         return;
0424     }
0425     ctxp = ctx_used.next;
0426     if (ctxp->ctx_mm == old_mm)
0427         ctxp = ctxp->next;
0428     if (ctxp == &ctx_used)
0429         panic("out of mmu contexts");
0430     flush_cache_mm(ctxp->ctx_mm);
0431     flush_tlb_mm(ctxp->ctx_mm);
0432     remove_from_ctx_list(ctxp);
0433     add_to_used_ctxlist(ctxp);
0434     ctxp->ctx_mm->context = NO_CONTEXT;
0435     ctxp->ctx_mm = mm;
0436     mm->context = ctxp->ctx_number;
0437 }
0438 
0439 static inline void free_context(int context)
0440 {
0441     struct ctx_list *ctx_old;
0442 
0443     ctx_old = ctx_list_pool + context;
0444     remove_from_ctx_list(ctx_old);
0445     add_to_free_ctxlist(ctx_old);
0446 }
0447 
0448 static void __init sparc_context_init(int numctx)
0449 {
0450     int ctx;
0451     unsigned long size;
0452 
0453     size = numctx * sizeof(struct ctx_list);
0454     ctx_list_pool = memblock_alloc(size, SMP_CACHE_BYTES);
0455     if (!ctx_list_pool)
0456         panic("%s: Failed to allocate %lu bytes\n", __func__, size);
0457 
0458     for (ctx = 0; ctx < numctx; ctx++) {
0459         struct ctx_list *clist;
0460 
0461         clist = (ctx_list_pool + ctx);
0462         clist->ctx_number = ctx;
0463         clist->ctx_mm = NULL;
0464     }
0465     ctx_free.next = ctx_free.prev = &ctx_free;
0466     ctx_used.next = ctx_used.prev = &ctx_used;
0467     for (ctx = 0; ctx < numctx; ctx++)
0468         add_to_free_ctxlist(ctx_list_pool + ctx);
0469 }
0470 
0471 void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
0472            struct task_struct *tsk)
0473 {
0474     unsigned long flags;
0475 
0476     if (mm->context == NO_CONTEXT) {
0477         spin_lock_irqsave(&srmmu_context_spinlock, flags);
0478         alloc_context(old_mm, mm);
0479         spin_unlock_irqrestore(&srmmu_context_spinlock, flags);
0480         srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
0481     }
0482 
0483     if (sparc_cpu_model == sparc_leon)
0484         leon_switch_mm();
0485 
0486     if (is_hypersparc)
0487         hyper_flush_whole_icache();
0488 
0489     srmmu_set_context(mm->context);
0490 }
0491 
0492 /* Low level IO area allocation on the SRMMU. */
0493 static inline void srmmu_mapioaddr(unsigned long physaddr,
0494                    unsigned long virt_addr, int bus_type)
0495 {
0496     pgd_t *pgdp;
0497     p4d_t *p4dp;
0498     pud_t *pudp;
0499     pmd_t *pmdp;
0500     pte_t *ptep;
0501     unsigned long tmp;
0502 
0503     physaddr &= PAGE_MASK;
0504     pgdp = pgd_offset_k(virt_addr);
0505     p4dp = p4d_offset(pgdp, virt_addr);
0506     pudp = pud_offset(p4dp, virt_addr);
0507     pmdp = pmd_offset(pudp, virt_addr);
0508     ptep = pte_offset_kernel(pmdp, virt_addr);
0509     tmp = (physaddr >> 4) | SRMMU_ET_PTE;
0510 
0511     /* I need to test whether this is consistent over all
0512      * sun4m's.  The bus_type represents the upper 4 bits of
0513      * 36-bit physical address on the I/O space lines...
0514      */
0515     tmp |= (bus_type << 28);
0516     tmp |= SRMMU_PRIV;
0517     __flush_page_to_ram(virt_addr);
0518     set_pte(ptep, __pte(tmp));
0519 }
0520 
0521 void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
0522               unsigned long xva, unsigned int len)
0523 {
0524     while (len != 0) {
0525         len -= PAGE_SIZE;
0526         srmmu_mapioaddr(xpa, xva, bus);
0527         xva += PAGE_SIZE;
0528         xpa += PAGE_SIZE;
0529     }
0530     flush_tlb_all();
0531 }
0532 
0533 static inline void srmmu_unmapioaddr(unsigned long virt_addr)
0534 {
0535     pgd_t *pgdp;
0536     p4d_t *p4dp;
0537     pud_t *pudp;
0538     pmd_t *pmdp;
0539     pte_t *ptep;
0540 
0541 
0542     pgdp = pgd_offset_k(virt_addr);
0543     p4dp = p4d_offset(pgdp, virt_addr);
0544     pudp = pud_offset(p4dp, virt_addr);
0545     pmdp = pmd_offset(pudp, virt_addr);
0546     ptep = pte_offset_kernel(pmdp, virt_addr);
0547 
0548     /* No need to flush uncacheable page. */
0549     __pte_clear(ptep);
0550 }
0551 
0552 void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
0553 {
0554     while (len != 0) {
0555         len -= PAGE_SIZE;
0556         srmmu_unmapioaddr(virt_addr);
0557         virt_addr += PAGE_SIZE;
0558     }
0559     flush_tlb_all();
0560 }
0561 
0562 /* tsunami.S */
0563 extern void tsunami_flush_cache_all(void);
0564 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
0565 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
0566 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
0567 extern void tsunami_flush_page_to_ram(unsigned long page);
0568 extern void tsunami_flush_page_for_dma(unsigned long page);
0569 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
0570 extern void tsunami_flush_tlb_all(void);
0571 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
0572 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
0573 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
0574 extern void tsunami_setup_blockops(void);
0575 
0576 /* swift.S */
0577 extern void swift_flush_cache_all(void);
0578 extern void swift_flush_cache_mm(struct mm_struct *mm);
0579 extern void swift_flush_cache_range(struct vm_area_struct *vma,
0580                     unsigned long start, unsigned long end);
0581 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
0582 extern void swift_flush_page_to_ram(unsigned long page);
0583 extern void swift_flush_page_for_dma(unsigned long page);
0584 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
0585 extern void swift_flush_tlb_all(void);
0586 extern void swift_flush_tlb_mm(struct mm_struct *mm);
0587 extern void swift_flush_tlb_range(struct vm_area_struct *vma,
0588                   unsigned long start, unsigned long end);
0589 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
0590 
0591 #if 0  /* P3: deadwood to debug precise flushes on Swift. */
0592 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
0593 {
0594     int cctx, ctx1;
0595 
0596     page &= PAGE_MASK;
0597     if ((ctx1 = vma->vm_mm->context) != -1) {
0598         cctx = srmmu_get_context();
0599 /* Is context # ever different from current context? P3 */
0600         if (cctx != ctx1) {
0601             printk("flush ctx %02x curr %02x\n", ctx1, cctx);
0602             srmmu_set_context(ctx1);
0603             swift_flush_page(page);
0604             __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
0605                     "r" (page), "i" (ASI_M_FLUSH_PROBE));
0606             srmmu_set_context(cctx);
0607         } else {
0608              /* Rm. prot. bits from virt. c. */
0609             /* swift_flush_cache_all(); */
0610             /* swift_flush_cache_page(vma, page); */
0611             swift_flush_page(page);
0612 
0613             __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
0614                 "r" (page), "i" (ASI_M_FLUSH_PROBE));
0615             /* same as above: srmmu_flush_tlb_page() */
0616         }
0617     }
0618 }
0619 #endif
0620 
0621 /*
0622  * The following are all MBUS based SRMMU modules, and therefore could
0623  * be found in a multiprocessor configuration.  On the whole, these
0624  * chips seems to be much more touchy about DVMA and page tables
0625  * with respect to cache coherency.
0626  */
0627 
0628 /* viking.S */
0629 extern void viking_flush_cache_all(void);
0630 extern void viking_flush_cache_mm(struct mm_struct *mm);
0631 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
0632                      unsigned long end);
0633 extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
0634 extern void viking_flush_page_to_ram(unsigned long page);
0635 extern void viking_flush_page_for_dma(unsigned long page);
0636 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
0637 extern void viking_flush_page(unsigned long page);
0638 extern void viking_mxcc_flush_page(unsigned long page);
0639 extern void viking_flush_tlb_all(void);
0640 extern void viking_flush_tlb_mm(struct mm_struct *mm);
0641 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
0642                    unsigned long end);
0643 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
0644                   unsigned long page);
0645 extern void sun4dsmp_flush_tlb_all(void);
0646 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
0647 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
0648                    unsigned long end);
0649 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
0650                   unsigned long page);
0651 
0652 /* hypersparc.S */
0653 extern void hypersparc_flush_cache_all(void);
0654 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
0655 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
0656 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
0657 extern void hypersparc_flush_page_to_ram(unsigned long page);
0658 extern void hypersparc_flush_page_for_dma(unsigned long page);
0659 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
0660 extern void hypersparc_flush_tlb_all(void);
0661 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
0662 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
0663 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
0664 extern void hypersparc_setup_blockops(void);
0665 
0666 /*
0667  * NOTE: All of this startup code assumes the low 16mb (approx.) of
0668  *       kernel mappings are done with one single contiguous chunk of
0669  *       ram.  On small ram machines (classics mainly) we only get
0670  *       around 8mb mapped for us.
0671  */
0672 
0673 static void __init early_pgtable_allocfail(char *type)
0674 {
0675     prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
0676     prom_halt();
0677 }
0678 
0679 static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
0680                             unsigned long end)
0681 {
0682     pgd_t *pgdp;
0683     p4d_t *p4dp;
0684     pud_t *pudp;
0685     pmd_t *pmdp;
0686     pte_t *ptep;
0687 
0688     while (start < end) {
0689         pgdp = pgd_offset_k(start);
0690         p4dp = p4d_offset(pgdp, start);
0691         pudp = pud_offset(p4dp, start);
0692         if (pud_none(*__nocache_fix(pudp))) {
0693             pmdp = __srmmu_get_nocache(
0694                 SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
0695             if (pmdp == NULL)
0696                 early_pgtable_allocfail("pmd");
0697             memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
0698             pud_set(__nocache_fix(pudp), pmdp);
0699         }
0700         pmdp = pmd_offset(__nocache_fix(pudp), start);
0701         if (srmmu_pmd_none(*__nocache_fix(pmdp))) {
0702             ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
0703             if (ptep == NULL)
0704                 early_pgtable_allocfail("pte");
0705             memset(__nocache_fix(ptep), 0, PTE_SIZE);
0706             pmd_set(__nocache_fix(pmdp), ptep);
0707         }
0708         if (start > (0xffffffffUL - PMD_SIZE))
0709             break;
0710         start = (start + PMD_SIZE) & PMD_MASK;
0711     }
0712 }
0713 
0714 static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
0715                           unsigned long end)
0716 {
0717     pgd_t *pgdp;
0718     p4d_t *p4dp;
0719     pud_t *pudp;
0720     pmd_t *pmdp;
0721     pte_t *ptep;
0722 
0723     while (start < end) {
0724         pgdp = pgd_offset_k(start);
0725         p4dp = p4d_offset(pgdp, start);
0726         pudp = pud_offset(p4dp, start);
0727         if (pud_none(*pudp)) {
0728             pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
0729             if (pmdp == NULL)
0730                 early_pgtable_allocfail("pmd");
0731             memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
0732             pud_set((pud_t *)pgdp, pmdp);
0733         }
0734         pmdp = pmd_offset(pudp, start);
0735         if (srmmu_pmd_none(*pmdp)) {
0736             ptep = __srmmu_get_nocache(PTE_SIZE,
0737                                  PTE_SIZE);
0738             if (ptep == NULL)
0739                 early_pgtable_allocfail("pte");
0740             memset(ptep, 0, PTE_SIZE);
0741             pmd_set(pmdp, ptep);
0742         }
0743         if (start > (0xffffffffUL - PMD_SIZE))
0744             break;
0745         start = (start + PMD_SIZE) & PMD_MASK;
0746     }
0747 }
0748 
0749 /* These flush types are not available on all chips... */
0750 static inline unsigned long srmmu_probe(unsigned long vaddr)
0751 {
0752     unsigned long retval;
0753 
0754     if (sparc_cpu_model != sparc_leon) {
0755 
0756         vaddr &= PAGE_MASK;
0757         __asm__ __volatile__("lda [%1] %2, %0\n\t" :
0758                      "=r" (retval) :
0759                      "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
0760     } else {
0761         retval = leon_swprobe(vaddr, NULL);
0762     }
0763     return retval;
0764 }
0765 
0766 /*
0767  * This is much cleaner than poking around physical address space
0768  * looking at the prom's page table directly which is what most
0769  * other OS's do.  Yuck... this is much better.
0770  */
0771 static void __init srmmu_inherit_prom_mappings(unsigned long start,
0772                            unsigned long end)
0773 {
0774     unsigned long probed;
0775     unsigned long addr;
0776     pgd_t *pgdp;
0777     p4d_t *p4dp;
0778     pud_t *pudp;
0779     pmd_t *pmdp;
0780     pte_t *ptep;
0781     int what; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
0782 
0783     while (start <= end) {
0784         if (start == 0)
0785             break; /* probably wrap around */
0786         if (start == 0xfef00000)
0787             start = KADB_DEBUGGER_BEGVM;
0788         probed = srmmu_probe(start);
0789         if (!probed) {
0790             /* continue probing until we find an entry */
0791             start += PAGE_SIZE;
0792             continue;
0793         }
0794 
0795         /* A red snapper, see what it really is. */
0796         what = 0;
0797         addr = start - PAGE_SIZE;
0798 
0799         if (!(start & ~(PMD_MASK))) {
0800             if (srmmu_probe(addr + PMD_SIZE) == probed)
0801                 what = 1;
0802         }
0803 
0804         if (!(start & ~(PGDIR_MASK))) {
0805             if (srmmu_probe(addr + PGDIR_SIZE) == probed)
0806                 what = 2;
0807         }
0808 
0809         pgdp = pgd_offset_k(start);
0810         p4dp = p4d_offset(pgdp, start);
0811         pudp = pud_offset(p4dp, start);
0812         if (what == 2) {
0813             *__nocache_fix(pgdp) = __pgd(probed);
0814             start += PGDIR_SIZE;
0815             continue;
0816         }
0817         if (pud_none(*__nocache_fix(pudp))) {
0818             pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE,
0819                            SRMMU_PMD_TABLE_SIZE);
0820             if (pmdp == NULL)
0821                 early_pgtable_allocfail("pmd");
0822             memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
0823             pud_set(__nocache_fix(pudp), pmdp);
0824         }
0825         pmdp = pmd_offset(__nocache_fix(pudp), start);
0826         if (what == 1) {
0827             *(pmd_t *)__nocache_fix(pmdp) = __pmd(probed);
0828             start += PMD_SIZE;
0829             continue;
0830         }
0831         if (srmmu_pmd_none(*__nocache_fix(pmdp))) {
0832             ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
0833             if (ptep == NULL)
0834                 early_pgtable_allocfail("pte");
0835             memset(__nocache_fix(ptep), 0, PTE_SIZE);
0836             pmd_set(__nocache_fix(pmdp), ptep);
0837         }
0838         ptep = pte_offset_kernel(__nocache_fix(pmdp), start);
0839         *__nocache_fix(ptep) = __pte(probed);
0840         start += PAGE_SIZE;
0841     }
0842 }
0843 
0844 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
0845 
0846 /* Create a third-level SRMMU 16MB page mapping. */
0847 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
0848 {
0849     pgd_t *pgdp = pgd_offset_k(vaddr);
0850     unsigned long big_pte;
0851 
0852     big_pte = KERNEL_PTE(phys_base >> 4);
0853     *__nocache_fix(pgdp) = __pgd(big_pte);
0854 }
0855 
0856 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
0857 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
0858 {
0859     unsigned long pstart = (sp_banks[sp_entry].base_addr & PGDIR_MASK);
0860     unsigned long vstart = (vbase & PGDIR_MASK);
0861     unsigned long vend = PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
0862     /* Map "low" memory only */
0863     const unsigned long min_vaddr = PAGE_OFFSET;
0864     const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
0865 
0866     if (vstart < min_vaddr || vstart >= max_vaddr)
0867         return vstart;
0868 
0869     if (vend > max_vaddr || vend < min_vaddr)
0870         vend = max_vaddr;
0871 
0872     while (vstart < vend) {
0873         do_large_mapping(vstart, pstart);
0874         vstart += PGDIR_SIZE; pstart += PGDIR_SIZE;
0875     }
0876     return vstart;
0877 }
0878 
0879 static void __init map_kernel(void)
0880 {
0881     int i;
0882 
0883     if (phys_base > 0) {
0884         do_large_mapping(PAGE_OFFSET, phys_base);
0885     }
0886 
0887     for (i = 0; sp_banks[i].num_bytes != 0; i++) {
0888         map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
0889     }
0890 }
0891 
0892 void (*poke_srmmu)(void) = NULL;
0893 
0894 void __init srmmu_paging_init(void)
0895 {
0896     int i;
0897     phandle cpunode;
0898     char node_str[128];
0899     pgd_t *pgd;
0900     p4d_t *p4d;
0901     pud_t *pud;
0902     pmd_t *pmd;
0903     pte_t *pte;
0904     unsigned long pages_avail;
0905 
0906     init_mm.context = (unsigned long) NO_CONTEXT;
0907     sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
0908 
0909     if (sparc_cpu_model == sun4d)
0910         num_contexts = 65536; /* We know it is Viking */
0911     else {
0912         /* Find the number of contexts on the srmmu. */
0913         cpunode = prom_getchild(prom_root_node);
0914         num_contexts = 0;
0915         while (cpunode != 0) {
0916             prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
0917             if (!strcmp(node_str, "cpu")) {
0918                 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
0919                 break;
0920             }
0921             cpunode = prom_getsibling(cpunode);
0922         }
0923     }
0924 
0925     if (!num_contexts) {
0926         prom_printf("Something wrong, can't find cpu node in paging_init.\n");
0927         prom_halt();
0928     }
0929 
0930     pages_avail = 0;
0931     last_valid_pfn = bootmem_init(&pages_avail);
0932 
0933     srmmu_nocache_calcsize();
0934     srmmu_nocache_init();
0935     srmmu_inherit_prom_mappings(0xfe400000, (LINUX_OPPROM_ENDVM - PAGE_SIZE));
0936     map_kernel();
0937 
0938     /* ctx table has to be physically aligned to its size */
0939     srmmu_context_table = __srmmu_get_nocache(num_contexts * sizeof(ctxd_t), num_contexts * sizeof(ctxd_t));
0940     srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa(srmmu_context_table);
0941 
0942     for (i = 0; i < num_contexts; i++)
0943         srmmu_ctxd_set(__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
0944 
0945     flush_cache_all();
0946     srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
0947 #ifdef CONFIG_SMP
0948     /* Stop from hanging here... */
0949     local_ops->tlb_all();
0950 #else
0951     flush_tlb_all();
0952 #endif
0953     poke_srmmu();
0954 
0955     srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
0956     srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
0957 
0958     srmmu_allocate_ptable_skeleton(
0959         __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
0960     srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
0961 
0962     pgd = pgd_offset_k(PKMAP_BASE);
0963     p4d = p4d_offset(pgd, PKMAP_BASE);
0964     pud = pud_offset(p4d, PKMAP_BASE);
0965     pmd = pmd_offset(pud, PKMAP_BASE);
0966     pte = pte_offset_kernel(pmd, PKMAP_BASE);
0967     pkmap_page_table = pte;
0968 
0969     flush_cache_all();
0970     flush_tlb_all();
0971 
0972     sparc_context_init(num_contexts);
0973 
0974     {
0975         unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0 };
0976 
0977         max_zone_pfn[ZONE_DMA] = max_low_pfn;
0978         max_zone_pfn[ZONE_NORMAL] = max_low_pfn;
0979         max_zone_pfn[ZONE_HIGHMEM] = highend_pfn;
0980 
0981         free_area_init(max_zone_pfn);
0982     }
0983 }
0984 
0985 void mmu_info(struct seq_file *m)
0986 {
0987     seq_printf(m,
0988            "MMU type\t: %s\n"
0989            "contexts\t: %d\n"
0990            "nocache total\t: %ld\n"
0991            "nocache used\t: %d\n",
0992            srmmu_name,
0993            num_contexts,
0994            srmmu_nocache_size,
0995            srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
0996 }
0997 
0998 int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
0999 {
1000     mm->context = NO_CONTEXT;
1001     return 0;
1002 }
1003 
1004 void destroy_context(struct mm_struct *mm)
1005 {
1006     unsigned long flags;
1007 
1008     if (mm->context != NO_CONTEXT) {
1009         flush_cache_mm(mm);
1010         srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1011         flush_tlb_mm(mm);
1012         spin_lock_irqsave(&srmmu_context_spinlock, flags);
1013         free_context(mm->context);
1014         spin_unlock_irqrestore(&srmmu_context_spinlock, flags);
1015         mm->context = NO_CONTEXT;
1016     }
1017 }
1018 
1019 /* Init various srmmu chip types. */
1020 static void __init srmmu_is_bad(void)
1021 {
1022     prom_printf("Could not determine SRMMU chip type.\n");
1023     prom_halt();
1024 }
1025 
1026 static void __init init_vac_layout(void)
1027 {
1028     phandle nd;
1029     int cache_lines;
1030     char node_str[128];
1031 #ifdef CONFIG_SMP
1032     int cpu = 0;
1033     unsigned long max_size = 0;
1034     unsigned long min_line_size = 0x10000000;
1035 #endif
1036 
1037     nd = prom_getchild(prom_root_node);
1038     while ((nd = prom_getsibling(nd)) != 0) {
1039         prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1040         if (!strcmp(node_str, "cpu")) {
1041             vac_line_size = prom_getint(nd, "cache-line-size");
1042             if (vac_line_size == -1) {
1043                 prom_printf("can't determine cache-line-size, halting.\n");
1044                 prom_halt();
1045             }
1046             cache_lines = prom_getint(nd, "cache-nlines");
1047             if (cache_lines == -1) {
1048                 prom_printf("can't determine cache-nlines, halting.\n");
1049                 prom_halt();
1050             }
1051 
1052             vac_cache_size = cache_lines * vac_line_size;
1053 #ifdef CONFIG_SMP
1054             if (vac_cache_size > max_size)
1055                 max_size = vac_cache_size;
1056             if (vac_line_size < min_line_size)
1057                 min_line_size = vac_line_size;
1058             //FIXME: cpus not contiguous!!
1059             cpu++;
1060             if (cpu >= nr_cpu_ids || !cpu_online(cpu))
1061                 break;
1062 #else
1063             break;
1064 #endif
1065         }
1066     }
1067     if (nd == 0) {
1068         prom_printf("No CPU nodes found, halting.\n");
1069         prom_halt();
1070     }
1071 #ifdef CONFIG_SMP
1072     vac_cache_size = max_size;
1073     vac_line_size = min_line_size;
1074 #endif
1075     printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1076            (int)vac_cache_size, (int)vac_line_size);
1077 }
1078 
1079 static void poke_hypersparc(void)
1080 {
1081     volatile unsigned long clear;
1082     unsigned long mreg = srmmu_get_mmureg();
1083 
1084     hyper_flush_unconditional_combined();
1085 
1086     mreg &= ~(HYPERSPARC_CWENABLE);
1087     mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1088     mreg |= (HYPERSPARC_CMODE);
1089 
1090     srmmu_set_mmureg(mreg);
1091 
1092 #if 0 /* XXX I think this is bad news... -DaveM */
1093     hyper_clear_all_tags();
1094 #endif
1095 
1096     put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1097     hyper_flush_whole_icache();
1098     clear = srmmu_get_faddr();
1099     clear = srmmu_get_fstatus();
1100 }
1101 
1102 static const struct sparc32_cachetlb_ops hypersparc_ops = {
1103     .cache_all  = hypersparc_flush_cache_all,
1104     .cache_mm   = hypersparc_flush_cache_mm,
1105     .cache_page = hypersparc_flush_cache_page,
1106     .cache_range    = hypersparc_flush_cache_range,
1107     .tlb_all    = hypersparc_flush_tlb_all,
1108     .tlb_mm     = hypersparc_flush_tlb_mm,
1109     .tlb_page   = hypersparc_flush_tlb_page,
1110     .tlb_range  = hypersparc_flush_tlb_range,
1111     .page_to_ram    = hypersparc_flush_page_to_ram,
1112     .sig_insns  = hypersparc_flush_sig_insns,
1113     .page_for_dma   = hypersparc_flush_page_for_dma,
1114 };
1115 
1116 static void __init init_hypersparc(void)
1117 {
1118     srmmu_name = "ROSS HyperSparc";
1119     srmmu_modtype = HyperSparc;
1120 
1121     init_vac_layout();
1122 
1123     is_hypersparc = 1;
1124     sparc32_cachetlb_ops = &hypersparc_ops;
1125 
1126     poke_srmmu = poke_hypersparc;
1127 
1128     hypersparc_setup_blockops();
1129 }
1130 
1131 static void poke_swift(void)
1132 {
1133     unsigned long mreg;
1134 
1135     /* Clear any crap from the cache or else... */
1136     swift_flush_cache_all();
1137 
1138     /* Enable I & D caches */
1139     mreg = srmmu_get_mmureg();
1140     mreg |= (SWIFT_IE | SWIFT_DE);
1141     /*
1142      * The Swift branch folding logic is completely broken.  At
1143      * trap time, if things are just right, if can mistakenly
1144      * think that a trap is coming from kernel mode when in fact
1145      * it is coming from user mode (it mis-executes the branch in
1146      * the trap code).  So you see things like crashme completely
1147      * hosing your machine which is completely unacceptable.  Turn
1148      * this shit off... nice job Fujitsu.
1149      */
1150     mreg &= ~(SWIFT_BF);
1151     srmmu_set_mmureg(mreg);
1152 }
1153 
1154 static const struct sparc32_cachetlb_ops swift_ops = {
1155     .cache_all  = swift_flush_cache_all,
1156     .cache_mm   = swift_flush_cache_mm,
1157     .cache_page = swift_flush_cache_page,
1158     .cache_range    = swift_flush_cache_range,
1159     .tlb_all    = swift_flush_tlb_all,
1160     .tlb_mm     = swift_flush_tlb_mm,
1161     .tlb_page   = swift_flush_tlb_page,
1162     .tlb_range  = swift_flush_tlb_range,
1163     .page_to_ram    = swift_flush_page_to_ram,
1164     .sig_insns  = swift_flush_sig_insns,
1165     .page_for_dma   = swift_flush_page_for_dma,
1166 };
1167 
1168 #define SWIFT_MASKID_ADDR  0x10003018
1169 static void __init init_swift(void)
1170 {
1171     unsigned long swift_rev;
1172 
1173     __asm__ __volatile__("lda [%1] %2, %0\n\t"
1174                  "srl %0, 0x18, %0\n\t" :
1175                  "=r" (swift_rev) :
1176                  "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1177     srmmu_name = "Fujitsu Swift";
1178     switch (swift_rev) {
1179     case 0x11:
1180     case 0x20:
1181     case 0x23:
1182     case 0x30:
1183         srmmu_modtype = Swift_lots_o_bugs;
1184         hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1185         /*
1186          * Gee george, I wonder why Sun is so hush hush about
1187          * this hardware bug... really braindamage stuff going
1188          * on here.  However I think we can find a way to avoid
1189          * all of the workaround overhead under Linux.  Basically,
1190          * any page fault can cause kernel pages to become user
1191          * accessible (the mmu gets confused and clears some of
1192          * the ACC bits in kernel ptes).  Aha, sounds pretty
1193          * horrible eh?  But wait, after extensive testing it appears
1194          * that if you use pgd_t level large kernel pte's (like the
1195          * 4MB pages on the Pentium) the bug does not get tripped
1196          * at all.  This avoids almost all of the major overhead.
1197          * Welcome to a world where your vendor tells you to,
1198          * "apply this kernel patch" instead of "sorry for the
1199          * broken hardware, send it back and we'll give you
1200          * properly functioning parts"
1201          */
1202         break;
1203     case 0x25:
1204     case 0x31:
1205         srmmu_modtype = Swift_bad_c;
1206         hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1207         /*
1208          * You see Sun allude to this hardware bug but never
1209          * admit things directly, they'll say things like,
1210          * "the Swift chip cache problems" or similar.
1211          */
1212         break;
1213     default:
1214         srmmu_modtype = Swift_ok;
1215         break;
1216     }
1217 
1218     sparc32_cachetlb_ops = &swift_ops;
1219     flush_page_for_dma_global = 0;
1220 
1221     /*
1222      * Are you now convinced that the Swift is one of the
1223      * biggest VLSI abortions of all time?  Bravo Fujitsu!
1224      * Fujitsu, the !#?!%$'d up processor people.  I bet if
1225      * you examined the microcode of the Swift you'd find
1226      * XXX's all over the place.
1227      */
1228     poke_srmmu = poke_swift;
1229 }
1230 
1231 static void turbosparc_flush_cache_all(void)
1232 {
1233     flush_user_windows();
1234     turbosparc_idflash_clear();
1235 }
1236 
1237 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1238 {
1239     FLUSH_BEGIN(mm)
1240     flush_user_windows();
1241     turbosparc_idflash_clear();
1242     FLUSH_END
1243 }
1244 
1245 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1246 {
1247     FLUSH_BEGIN(vma->vm_mm)
1248     flush_user_windows();
1249     turbosparc_idflash_clear();
1250     FLUSH_END
1251 }
1252 
1253 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1254 {
1255     FLUSH_BEGIN(vma->vm_mm)
1256     flush_user_windows();
1257     if (vma->vm_flags & VM_EXEC)
1258         turbosparc_flush_icache();
1259     turbosparc_flush_dcache();
1260     FLUSH_END
1261 }
1262 
1263 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
1264 static void turbosparc_flush_page_to_ram(unsigned long page)
1265 {
1266 #ifdef TURBOSPARC_WRITEBACK
1267     volatile unsigned long clear;
1268 
1269     if (srmmu_probe(page))
1270         turbosparc_flush_page_cache(page);
1271     clear = srmmu_get_fstatus();
1272 #endif
1273 }
1274 
1275 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1276 {
1277 }
1278 
1279 static void turbosparc_flush_page_for_dma(unsigned long page)
1280 {
1281     turbosparc_flush_dcache();
1282 }
1283 
1284 static void turbosparc_flush_tlb_all(void)
1285 {
1286     srmmu_flush_whole_tlb();
1287 }
1288 
1289 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1290 {
1291     FLUSH_BEGIN(mm)
1292     srmmu_flush_whole_tlb();
1293     FLUSH_END
1294 }
1295 
1296 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1297 {
1298     FLUSH_BEGIN(vma->vm_mm)
1299     srmmu_flush_whole_tlb();
1300     FLUSH_END
1301 }
1302 
1303 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1304 {
1305     FLUSH_BEGIN(vma->vm_mm)
1306     srmmu_flush_whole_tlb();
1307     FLUSH_END
1308 }
1309 
1310 
1311 static void poke_turbosparc(void)
1312 {
1313     unsigned long mreg = srmmu_get_mmureg();
1314     unsigned long ccreg;
1315 
1316     /* Clear any crap from the cache or else... */
1317     turbosparc_flush_cache_all();
1318     /* Temporarily disable I & D caches */
1319     mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE);
1320     mreg &= ~(TURBOSPARC_PCENABLE);     /* Don't check parity */
1321     srmmu_set_mmureg(mreg);
1322 
1323     ccreg = turbosparc_get_ccreg();
1324 
1325 #ifdef TURBOSPARC_WRITEBACK
1326     ccreg |= (TURBOSPARC_SNENABLE);     /* Do DVMA snooping in Dcache */
1327     ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1328             /* Write-back D-cache, emulate VLSI
1329              * abortion number three, not number one */
1330 #else
1331     /* For now let's play safe, optimize later */
1332     ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1333             /* Do DVMA snooping in Dcache, Write-thru D-cache */
1334     ccreg &= ~(TURBOSPARC_uS2);
1335             /* Emulate VLSI abortion number three, not number one */
1336 #endif
1337 
1338     switch (ccreg & 7) {
1339     case 0: /* No SE cache */
1340     case 7: /* Test mode */
1341         break;
1342     default:
1343         ccreg |= (TURBOSPARC_SCENABLE);
1344     }
1345     turbosparc_set_ccreg(ccreg);
1346 
1347     mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1348     mreg |= (TURBOSPARC_ICSNOOP);       /* Icache snooping on */
1349     srmmu_set_mmureg(mreg);
1350 }
1351 
1352 static const struct sparc32_cachetlb_ops turbosparc_ops = {
1353     .cache_all  = turbosparc_flush_cache_all,
1354     .cache_mm   = turbosparc_flush_cache_mm,
1355     .cache_page = turbosparc_flush_cache_page,
1356     .cache_range    = turbosparc_flush_cache_range,
1357     .tlb_all    = turbosparc_flush_tlb_all,
1358     .tlb_mm     = turbosparc_flush_tlb_mm,
1359     .tlb_page   = turbosparc_flush_tlb_page,
1360     .tlb_range  = turbosparc_flush_tlb_range,
1361     .page_to_ram    = turbosparc_flush_page_to_ram,
1362     .sig_insns  = turbosparc_flush_sig_insns,
1363     .page_for_dma   = turbosparc_flush_page_for_dma,
1364 };
1365 
1366 static void __init init_turbosparc(void)
1367 {
1368     srmmu_name = "Fujitsu TurboSparc";
1369     srmmu_modtype = TurboSparc;
1370     sparc32_cachetlb_ops = &turbosparc_ops;
1371     poke_srmmu = poke_turbosparc;
1372 }
1373 
1374 static void poke_tsunami(void)
1375 {
1376     unsigned long mreg = srmmu_get_mmureg();
1377 
1378     tsunami_flush_icache();
1379     tsunami_flush_dcache();
1380     mreg &= ~TSUNAMI_ITD;
1381     mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1382     srmmu_set_mmureg(mreg);
1383 }
1384 
1385 static const struct sparc32_cachetlb_ops tsunami_ops = {
1386     .cache_all  = tsunami_flush_cache_all,
1387     .cache_mm   = tsunami_flush_cache_mm,
1388     .cache_page = tsunami_flush_cache_page,
1389     .cache_range    = tsunami_flush_cache_range,
1390     .tlb_all    = tsunami_flush_tlb_all,
1391     .tlb_mm     = tsunami_flush_tlb_mm,
1392     .tlb_page   = tsunami_flush_tlb_page,
1393     .tlb_range  = tsunami_flush_tlb_range,
1394     .page_to_ram    = tsunami_flush_page_to_ram,
1395     .sig_insns  = tsunami_flush_sig_insns,
1396     .page_for_dma   = tsunami_flush_page_for_dma,
1397 };
1398 
1399 static void __init init_tsunami(void)
1400 {
1401     /*
1402      * Tsunami's pretty sane, Sun and TI actually got it
1403      * somewhat right this time.  Fujitsu should have
1404      * taken some lessons from them.
1405      */
1406 
1407     srmmu_name = "TI Tsunami";
1408     srmmu_modtype = Tsunami;
1409     sparc32_cachetlb_ops = &tsunami_ops;
1410     poke_srmmu = poke_tsunami;
1411 
1412     tsunami_setup_blockops();
1413 }
1414 
1415 static void poke_viking(void)
1416 {
1417     unsigned long mreg = srmmu_get_mmureg();
1418     static int smp_catch;
1419 
1420     if (viking_mxcc_present) {
1421         unsigned long mxcc_control = mxcc_get_creg();
1422 
1423         mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1424         mxcc_control &= ~(MXCC_CTL_RRC);
1425         mxcc_set_creg(mxcc_control);
1426 
1427         /*
1428          * We don't need memory parity checks.
1429          * XXX This is a mess, have to dig out later. ecd.
1430         viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1431          */
1432 
1433         /* We do cache ptables on MXCC. */
1434         mreg |= VIKING_TCENABLE;
1435     } else {
1436         unsigned long bpreg;
1437 
1438         mreg &= ~(VIKING_TCENABLE);
1439         if (smp_catch++) {
1440             /* Must disable mixed-cmd mode here for other cpu's. */
1441             bpreg = viking_get_bpreg();
1442             bpreg &= ~(VIKING_ACTION_MIX);
1443             viking_set_bpreg(bpreg);
1444 
1445             /* Just in case PROM does something funny. */
1446             msi_set_sync();
1447         }
1448     }
1449 
1450     mreg |= VIKING_SPENABLE;
1451     mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1452     mreg |= VIKING_SBENABLE;
1453     mreg &= ~(VIKING_ACENABLE);
1454     srmmu_set_mmureg(mreg);
1455 }
1456 
1457 static struct sparc32_cachetlb_ops viking_ops __ro_after_init = {
1458     .cache_all  = viking_flush_cache_all,
1459     .cache_mm   = viking_flush_cache_mm,
1460     .cache_page = viking_flush_cache_page,
1461     .cache_range    = viking_flush_cache_range,
1462     .tlb_all    = viking_flush_tlb_all,
1463     .tlb_mm     = viking_flush_tlb_mm,
1464     .tlb_page   = viking_flush_tlb_page,
1465     .tlb_range  = viking_flush_tlb_range,
1466     .page_to_ram    = viking_flush_page_to_ram,
1467     .sig_insns  = viking_flush_sig_insns,
1468     .page_for_dma   = viking_flush_page_for_dma,
1469 };
1470 
1471 #ifdef CONFIG_SMP
1472 /* On sun4d the cpu broadcasts local TLB flushes, so we can just
1473  * perform the local TLB flush and all the other cpus will see it.
1474  * But, unfortunately, there is a bug in the sun4d XBUS backplane
1475  * that requires that we add some synchronization to these flushes.
1476  *
1477  * The bug is that the fifo which keeps track of all the pending TLB
1478  * broadcasts in the system is an entry or two too small, so if we
1479  * have too many going at once we'll overflow that fifo and lose a TLB
1480  * flush resulting in corruption.
1481  *
1482  * Our workaround is to take a global spinlock around the TLB flushes,
1483  * which guarentees we won't ever have too many pending.  It's a big
1484  * hammer, but a semaphore like system to make sure we only have N TLB
1485  * flushes going at once will require SMP locking anyways so there's
1486  * no real value in trying any harder than this.
1487  */
1488 static struct sparc32_cachetlb_ops viking_sun4d_smp_ops __ro_after_init = {
1489     .cache_all  = viking_flush_cache_all,
1490     .cache_mm   = viking_flush_cache_mm,
1491     .cache_page = viking_flush_cache_page,
1492     .cache_range    = viking_flush_cache_range,
1493     .tlb_all    = sun4dsmp_flush_tlb_all,
1494     .tlb_mm     = sun4dsmp_flush_tlb_mm,
1495     .tlb_page   = sun4dsmp_flush_tlb_page,
1496     .tlb_range  = sun4dsmp_flush_tlb_range,
1497     .page_to_ram    = viking_flush_page_to_ram,
1498     .sig_insns  = viking_flush_sig_insns,
1499     .page_for_dma   = viking_flush_page_for_dma,
1500 };
1501 #endif
1502 
1503 static void __init init_viking(void)
1504 {
1505     unsigned long mreg = srmmu_get_mmureg();
1506 
1507     /* Ahhh, the viking.  SRMMU VLSI abortion number two... */
1508     if (mreg & VIKING_MMODE) {
1509         srmmu_name = "TI Viking";
1510         viking_mxcc_present = 0;
1511         msi_set_sync();
1512 
1513         /*
1514          * We need this to make sure old viking takes no hits
1515          * on it's cache for dma snoops to workaround the
1516          * "load from non-cacheable memory" interrupt bug.
1517          * This is only necessary because of the new way in
1518          * which we use the IOMMU.
1519          */
1520         viking_ops.page_for_dma = viking_flush_page;
1521 #ifdef CONFIG_SMP
1522         viking_sun4d_smp_ops.page_for_dma = viking_flush_page;
1523 #endif
1524         flush_page_for_dma_global = 0;
1525     } else {
1526         srmmu_name = "TI Viking/MXCC";
1527         viking_mxcc_present = 1;
1528         srmmu_cache_pagetables = 1;
1529     }
1530 
1531     sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1532         &viking_ops;
1533 #ifdef CONFIG_SMP
1534     if (sparc_cpu_model == sun4d)
1535         sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1536             &viking_sun4d_smp_ops;
1537 #endif
1538 
1539     poke_srmmu = poke_viking;
1540 }
1541 
1542 /* Probe for the srmmu chip version. */
1543 static void __init get_srmmu_type(void)
1544 {
1545     unsigned long mreg, psr;
1546     unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1547 
1548     srmmu_modtype = SRMMU_INVAL_MOD;
1549     hwbug_bitmask = 0;
1550 
1551     mreg = srmmu_get_mmureg(); psr = get_psr();
1552     mod_typ = (mreg & 0xf0000000) >> 28;
1553     mod_rev = (mreg & 0x0f000000) >> 24;
1554     psr_typ = (psr >> 28) & 0xf;
1555     psr_vers = (psr >> 24) & 0xf;
1556 
1557     /* First, check for sparc-leon. */
1558     if (sparc_cpu_model == sparc_leon) {
1559         init_leon();
1560         return;
1561     }
1562 
1563     /* Second, check for HyperSparc or Cypress. */
1564     if (mod_typ == 1) {
1565         switch (mod_rev) {
1566         case 7:
1567             /* UP or MP Hypersparc */
1568             init_hypersparc();
1569             break;
1570         case 0:
1571         case 2:
1572         case 10:
1573         case 11:
1574         case 12:
1575         case 13:
1576         case 14:
1577         case 15:
1578         default:
1579             prom_printf("Sparc-Linux Cypress support does not longer exit.\n");
1580             prom_halt();
1581             break;
1582         }
1583         return;
1584     }
1585 
1586     /* Now Fujitsu TurboSparc. It might happen that it is
1587      * in Swift emulation mode, so we will check later...
1588      */
1589     if (psr_typ == 0 && psr_vers == 5) {
1590         init_turbosparc();
1591         return;
1592     }
1593 
1594     /* Next check for Fujitsu Swift. */
1595     if (psr_typ == 0 && psr_vers == 4) {
1596         phandle cpunode;
1597         char node_str[128];
1598 
1599         /* Look if it is not a TurboSparc emulating Swift... */
1600         cpunode = prom_getchild(prom_root_node);
1601         while ((cpunode = prom_getsibling(cpunode)) != 0) {
1602             prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1603             if (!strcmp(node_str, "cpu")) {
1604                 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
1605                     prom_getintdefault(cpunode, "psr-version", 1) == 5) {
1606                     init_turbosparc();
1607                     return;
1608                 }
1609                 break;
1610             }
1611         }
1612 
1613         init_swift();
1614         return;
1615     }
1616 
1617     /* Now the Viking family of srmmu. */
1618     if (psr_typ == 4 &&
1619        ((psr_vers == 0) ||
1620         ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
1621         init_viking();
1622         return;
1623     }
1624 
1625     /* Finally the Tsunami. */
1626     if (psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
1627         init_tsunami();
1628         return;
1629     }
1630 
1631     /* Oh well */
1632     srmmu_is_bad();
1633 }
1634 
1635 #ifdef CONFIG_SMP
1636 /* Local cross-calls. */
1637 static void smp_flush_page_for_dma(unsigned long page)
1638 {
1639     xc1(local_ops->page_for_dma, page);
1640     local_ops->page_for_dma(page);
1641 }
1642 
1643 static void smp_flush_cache_all(void)
1644 {
1645     xc0(local_ops->cache_all);
1646     local_ops->cache_all();
1647 }
1648 
1649 static void smp_flush_tlb_all(void)
1650 {
1651     xc0(local_ops->tlb_all);
1652     local_ops->tlb_all();
1653 }
1654 
1655 static void smp_flush_cache_mm(struct mm_struct *mm)
1656 {
1657     if (mm->context != NO_CONTEXT) {
1658         cpumask_t cpu_mask;
1659         cpumask_copy(&cpu_mask, mm_cpumask(mm));
1660         cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1661         if (!cpumask_empty(&cpu_mask))
1662             xc1(local_ops->cache_mm, (unsigned long)mm);
1663         local_ops->cache_mm(mm);
1664     }
1665 }
1666 
1667 static void smp_flush_tlb_mm(struct mm_struct *mm)
1668 {
1669     if (mm->context != NO_CONTEXT) {
1670         cpumask_t cpu_mask;
1671         cpumask_copy(&cpu_mask, mm_cpumask(mm));
1672         cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1673         if (!cpumask_empty(&cpu_mask)) {
1674             xc1(local_ops->tlb_mm, (unsigned long)mm);
1675             if (atomic_read(&mm->mm_users) == 1 && current->active_mm == mm)
1676                 cpumask_copy(mm_cpumask(mm),
1677                          cpumask_of(smp_processor_id()));
1678         }
1679         local_ops->tlb_mm(mm);
1680     }
1681 }
1682 
1683 static void smp_flush_cache_range(struct vm_area_struct *vma,
1684                   unsigned long start,
1685                   unsigned long end)
1686 {
1687     struct mm_struct *mm = vma->vm_mm;
1688 
1689     if (mm->context != NO_CONTEXT) {
1690         cpumask_t cpu_mask;
1691         cpumask_copy(&cpu_mask, mm_cpumask(mm));
1692         cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1693         if (!cpumask_empty(&cpu_mask))
1694             xc3(local_ops->cache_range, (unsigned long)vma, start,
1695                 end);
1696         local_ops->cache_range(vma, start, end);
1697     }
1698 }
1699 
1700 static void smp_flush_tlb_range(struct vm_area_struct *vma,
1701                 unsigned long start,
1702                 unsigned long end)
1703 {
1704     struct mm_struct *mm = vma->vm_mm;
1705 
1706     if (mm->context != NO_CONTEXT) {
1707         cpumask_t cpu_mask;
1708         cpumask_copy(&cpu_mask, mm_cpumask(mm));
1709         cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1710         if (!cpumask_empty(&cpu_mask))
1711             xc3(local_ops->tlb_range, (unsigned long)vma, start,
1712                 end);
1713         local_ops->tlb_range(vma, start, end);
1714     }
1715 }
1716 
1717 static void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1718 {
1719     struct mm_struct *mm = vma->vm_mm;
1720 
1721     if (mm->context != NO_CONTEXT) {
1722         cpumask_t cpu_mask;
1723         cpumask_copy(&cpu_mask, mm_cpumask(mm));
1724         cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1725         if (!cpumask_empty(&cpu_mask))
1726             xc2(local_ops->cache_page, (unsigned long)vma, page);
1727         local_ops->cache_page(vma, page);
1728     }
1729 }
1730 
1731 static void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1732 {
1733     struct mm_struct *mm = vma->vm_mm;
1734 
1735     if (mm->context != NO_CONTEXT) {
1736         cpumask_t cpu_mask;
1737         cpumask_copy(&cpu_mask, mm_cpumask(mm));
1738         cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1739         if (!cpumask_empty(&cpu_mask))
1740             xc2(local_ops->tlb_page, (unsigned long)vma, page);
1741         local_ops->tlb_page(vma, page);
1742     }
1743 }
1744 
1745 static void smp_flush_page_to_ram(unsigned long page)
1746 {
1747     /* Current theory is that those who call this are the one's
1748      * who have just dirtied their cache with the pages contents
1749      * in kernel space, therefore we only run this on local cpu.
1750      *
1751      * XXX This experiment failed, research further... -DaveM
1752      */
1753 #if 1
1754     xc1(local_ops->page_to_ram, page);
1755 #endif
1756     local_ops->page_to_ram(page);
1757 }
1758 
1759 static void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1760 {
1761     cpumask_t cpu_mask;
1762     cpumask_copy(&cpu_mask, mm_cpumask(mm));
1763     cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1764     if (!cpumask_empty(&cpu_mask))
1765         xc2(local_ops->sig_insns, (unsigned long)mm, insn_addr);
1766     local_ops->sig_insns(mm, insn_addr);
1767 }
1768 
1769 static struct sparc32_cachetlb_ops smp_cachetlb_ops __ro_after_init = {
1770     .cache_all  = smp_flush_cache_all,
1771     .cache_mm   = smp_flush_cache_mm,
1772     .cache_page = smp_flush_cache_page,
1773     .cache_range    = smp_flush_cache_range,
1774     .tlb_all    = smp_flush_tlb_all,
1775     .tlb_mm     = smp_flush_tlb_mm,
1776     .tlb_page   = smp_flush_tlb_page,
1777     .tlb_range  = smp_flush_tlb_range,
1778     .page_to_ram    = smp_flush_page_to_ram,
1779     .sig_insns  = smp_flush_sig_insns,
1780     .page_for_dma   = smp_flush_page_for_dma,
1781 };
1782 #endif
1783 
1784 /* Load up routines and constants for sun4m and sun4d mmu */
1785 void __init load_mmu(void)
1786 {
1787     /* Functions */
1788     get_srmmu_type();
1789 
1790 #ifdef CONFIG_SMP
1791     /* El switcheroo... */
1792     local_ops = sparc32_cachetlb_ops;
1793 
1794     if (sparc_cpu_model == sun4d || sparc_cpu_model == sparc_leon) {
1795         smp_cachetlb_ops.tlb_all = local_ops->tlb_all;
1796         smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm;
1797         smp_cachetlb_ops.tlb_range = local_ops->tlb_range;
1798         smp_cachetlb_ops.tlb_page = local_ops->tlb_page;
1799     }
1800 
1801     if (poke_srmmu == poke_viking) {
1802         /* Avoid unnecessary cross calls. */
1803         smp_cachetlb_ops.cache_all = local_ops->cache_all;
1804         smp_cachetlb_ops.cache_mm = local_ops->cache_mm;
1805         smp_cachetlb_ops.cache_range = local_ops->cache_range;
1806         smp_cachetlb_ops.cache_page = local_ops->cache_page;
1807 
1808         smp_cachetlb_ops.page_to_ram = local_ops->page_to_ram;
1809         smp_cachetlb_ops.sig_insns = local_ops->sig_insns;
1810         smp_cachetlb_ops.page_for_dma = local_ops->page_for_dma;
1811     }
1812 
1813     /* It really is const after this point. */
1814     sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1815         &smp_cachetlb_ops;
1816 #endif
1817 
1818     if (sparc_cpu_model != sun4d)
1819         ld_mmu_iommu();
1820 #ifdef CONFIG_SMP
1821     if (sparc_cpu_model == sun4d)
1822         sun4d_init_smp();
1823     else if (sparc_cpu_model == sparc_leon)
1824         leon_init_smp();
1825     else
1826         sun4m_init_smp();
1827 #endif
1828 }
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