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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * arch/sparc/math-emu/math.c
0004  *
0005  * Copyright (C) 1998 Peter Maydell (pmaydell@chiark.greenend.org.uk)
0006  * Copyright (C) 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz)
0007  * Copyright (C) 1999 David S. Miller (davem@redhat.com)
0008  *
0009  * This is a good place to start if you're trying to understand the
0010  * emulation code, because it's pretty simple. What we do is
0011  * essentially analyse the instruction to work out what the operation
0012  * is and which registers are involved. We then execute the appropriate
0013  * FXXXX function. [The floating point queue introduces a minor wrinkle;
0014  * see below...]
0015  * The fxxxxx.c files each emulate a single insn. They look relatively
0016  * simple because the complexity is hidden away in an unholy tangle
0017  * of preprocessor macros.
0018  *
0019  * The first layer of macros is single.h, double.h, quad.h. Generally
0020  * these files define macros for working with floating point numbers
0021  * of the three IEEE formats. FP_ADD_D(R,A,B) is for adding doubles,
0022  * for instance. These macros are usually defined as calls to more
0023  * generic macros (in this case _FP_ADD(D,2,R,X,Y) where the number
0024  * of machine words required to store the given IEEE format is passed
0025  * as a parameter. [double.h and co check the number of bits in a word
0026  * and define FP_ADD_D & co appropriately].
0027  * The generic macros are defined in op-common.h. This is where all
0028  * the grotty stuff like handling NaNs is coded. To handle the possible
0029  * word sizes macros in op-common.h use macros like _FP_FRAC_SLL_##wc()
0030  * where wc is the 'number of machine words' parameter (here 2).
0031  * These are defined in the third layer of macros: op-1.h, op-2.h
0032  * and op-4.h. These handle operations on floating point numbers composed
0033  * of 1,2 and 4 machine words respectively. [For example, on sparc64
0034  * doubles are one machine word so macros in double.h eventually use
0035  * constructs in op-1.h, but on sparc32 they use op-2.h definitions.]
0036  * soft-fp.h is on the same level as op-common.h, and defines some
0037  * macros which are independent of both word size and FP format.
0038  * Finally, sfp-machine.h is the machine dependent part of the
0039  * code: it defines the word size and what type a word is. It also
0040  * defines how _FP_MUL_MEAT_t() maps to _FP_MUL_MEAT_n_* : op-n.h
0041  * provide several possible flavours of multiply algorithm, most
0042  * of which require that you supply some form of asm or C primitive to
0043  * do the actual multiply. (such asm primitives should be defined
0044  * in sfp-machine.h too). udivmodti4.c is the same sort of thing.
0045  *
0046  * There may be some errors here because I'm working from a
0047  * SPARC architecture manual V9, and what I really want is V8...
0048  * Also, the insns which can generate exceptions seem to be a
0049  * greater subset of the FPops than for V9 (for example, FCMPED
0050  * has to be emulated on V8). So I think I'm going to have
0051  * to emulate them all just to be on the safe side...
0052  *
0053  * Emulation routines originate from soft-fp package, which is
0054  * part of glibc and has appropriate copyrights in it (allegedly).
0055  *
0056  * NB: on sparc int == long == 4 bytes, long long == 8 bytes.
0057  * Most bits of the kernel seem to go for long rather than int,
0058  * so we follow that practice...
0059  */
0060 
0061 /* TODO:
0062  * fpsave() saves the FP queue but fpload() doesn't reload it.
0063  * Therefore when we context switch or change FPU ownership
0064  * we have to check to see if the queue had anything in it and
0065  * emulate it if it did. This is going to be a pain.
0066  */
0067 
0068 #include <linux/types.h>
0069 #include <linux/sched.h>
0070 #include <linux/mm.h>
0071 #include <linux/perf_event.h>
0072 #include <linux/uaccess.h>
0073 
0074 #include "sfp-util_32.h"
0075 #include <math-emu/soft-fp.h>
0076 #include <math-emu/single.h>
0077 #include <math-emu/double.h>
0078 #include <math-emu/quad.h>
0079 
0080 #define FLOATFUNC(x) extern int x(void *,void *,void *)
0081 
0082 /* The Vn labels indicate what version of the SPARC architecture gas thinks
0083  * each insn is. This is from the binutils source :->
0084  */
0085 /* quadword instructions */
0086 #define FSQRTQ  0x02b       /* v8 */
0087 #define FADDQ   0x043       /* v8 */
0088 #define FSUBQ   0x047       /* v8 */
0089 #define FMULQ   0x04b       /* v8 */
0090 #define FDIVQ   0x04f       /* v8 */
0091 #define FDMULQ  0x06e       /* v8 */
0092 #define FQTOS   0x0c7       /* v8 */
0093 #define FQTOD   0x0cb       /* v8 */
0094 #define FITOQ   0x0cc       /* v8 */
0095 #define FSTOQ   0x0cd       /* v8 */
0096 #define FDTOQ   0x0ce       /* v8 */
0097 #define FQTOI   0x0d3       /* v8 */
0098 #define FCMPQ   0x053       /* v8 */
0099 #define FCMPEQ  0x057       /* v8 */
0100 /* single/double instructions (subnormal): should all work */
0101 #define FSQRTS  0x029       /* v7 */
0102 #define FSQRTD  0x02a       /* v7 */
0103 #define FADDS   0x041       /* v6 */
0104 #define FADDD   0x042       /* v6 */
0105 #define FSUBS   0x045       /* v6 */
0106 #define FSUBD   0x046       /* v6 */
0107 #define FMULS   0x049       /* v6 */
0108 #define FMULD   0x04a       /* v6 */
0109 #define FDIVS   0x04d       /* v6 */
0110 #define FDIVD   0x04e       /* v6 */
0111 #define FSMULD  0x069       /* v6 */
0112 #define FDTOS   0x0c6       /* v6 */
0113 #define FSTOD   0x0c9       /* v6 */
0114 #define FSTOI   0x0d1       /* v6 */
0115 #define FDTOI   0x0d2       /* v6 */
0116 #define FABSS   0x009       /* v6 */
0117 #define FCMPS   0x051       /* v6 */
0118 #define FCMPES  0x055       /* v6 */
0119 #define FCMPD   0x052       /* v6 */
0120 #define FCMPED  0x056       /* v6 */
0121 #define FMOVS   0x001       /* v6 */
0122 #define FNEGS   0x005       /* v6 */
0123 #define FITOS   0x0c4       /* v6 */
0124 #define FITOD   0x0c8       /* v6 */
0125 
0126 #define FSR_TEM_SHIFT   23UL
0127 #define FSR_TEM_MASK    (0x1fUL << FSR_TEM_SHIFT)
0128 #define FSR_AEXC_SHIFT  5UL
0129 #define FSR_AEXC_MASK   (0x1fUL << FSR_AEXC_SHIFT)
0130 #define FSR_CEXC_SHIFT  0UL
0131 #define FSR_CEXC_MASK   (0x1fUL << FSR_CEXC_SHIFT)
0132 
0133 static int do_one_mathemu(u32 insn, unsigned long *fsr, unsigned long *fregs);
0134 
0135 /* Unlike the Sparc64 version (which has a struct fpustate), we
0136  * pass the taskstruct corresponding to the task which currently owns the
0137  * FPU. This is partly because we don't have the fpustate struct and
0138  * partly because the task owning the FPU isn't always current (as is
0139  * the case for the Sparc64 port). This is probably SMP-related...
0140  * This function returns 1 if all queued insns were emulated successfully.
0141  * The test for unimplemented FPop in kernel mode has been moved into
0142  * kernel/traps.c for simplicity.
0143  */
0144 int do_mathemu(struct pt_regs *regs, struct task_struct *fpt)
0145 {
0146     /* regs->pc isn't necessarily the PC at which the offending insn is sitting.
0147      * The FPU maintains a queue of FPops which cause traps.
0148      * When it hits an instruction that requires that the trapped op succeeded
0149      * (usually because it reads a reg. that the trapped op wrote) then it
0150      * causes this exception. We need to emulate all the insns on the queue
0151      * and then allow the op to proceed.
0152      * This code should also handle the case where the trap was precise,
0153      * in which case the queue length is zero and regs->pc points at the
0154      * single FPop to be emulated. (this case is untested, though :->)
0155      * You'll need this case if you want to be able to emulate all FPops
0156      * because the FPU either doesn't exist or has been software-disabled.
0157      * [The UltraSPARC makes FP a precise trap; this isn't as stupid as it
0158      * might sound because the Ultra does funky things with a superscalar
0159      * architecture.]
0160      */
0161 
0162     /* You wouldn't believe how often I typed 'ftp' when I meant 'fpt' :-> */
0163 
0164     int i;
0165     int retcode = 0;                               /* assume all succeed */
0166     unsigned long insn;
0167 
0168     perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
0169 
0170 #ifdef DEBUG_MATHEMU
0171     printk("In do_mathemu()... pc is %08lx\n", regs->pc);
0172     printk("fpqdepth is %ld\n", fpt->thread.fpqdepth);
0173     for (i = 0; i < fpt->thread.fpqdepth; i++)
0174         printk("%d: %08lx at %08lx\n", i, fpt->thread.fpqueue[i].insn,
0175                (unsigned long)fpt->thread.fpqueue[i].insn_addr);
0176 #endif
0177 
0178     if (fpt->thread.fpqdepth == 0) {                   /* no queue, guilty insn is at regs->pc */
0179 #ifdef DEBUG_MATHEMU
0180         printk("precise trap at %08lx\n", regs->pc);
0181 #endif
0182         if (!get_user(insn, (u32 __user *) regs->pc)) {
0183             retcode = do_one_mathemu(insn, &fpt->thread.fsr, fpt->thread.float_regs);
0184             if (retcode) {
0185                 /* in this case we need to fix up PC & nPC */
0186                 regs->pc = regs->npc;
0187                 regs->npc += 4;
0188             }
0189         }
0190         return retcode;
0191     }
0192 
0193     /* Normal case: need to empty the queue... */
0194     for (i = 0; i < fpt->thread.fpqdepth; i++) {
0195         retcode = do_one_mathemu(fpt->thread.fpqueue[i].insn, &(fpt->thread.fsr), fpt->thread.float_regs);
0196         if (!retcode)                               /* insn failed, no point doing any more */
0197             break;
0198     }
0199     /* Now empty the queue and clear the queue_not_empty flag */
0200     if (retcode)
0201         fpt->thread.fsr &= ~(0x3000 | FSR_CEXC_MASK);
0202     else
0203         fpt->thread.fsr &= ~0x3000;
0204     fpt->thread.fpqdepth = 0;
0205 
0206     return retcode;
0207 }
0208 
0209 /* All routines returning an exception to raise should detect
0210  * such exceptions _before_ rounding to be consistent with
0211  * the behavior of the hardware in the implemented cases
0212  * (and thus with the recommendations in the V9 architecture
0213  * manual).
0214  *
0215  * We return 0 if a SIGFPE should be sent, 1 otherwise.
0216  */
0217 static inline int record_exception(unsigned long *pfsr, int eflag)
0218 {
0219     unsigned long fsr = *pfsr;
0220     int would_trap;
0221 
0222     /* Determine if this exception would have generated a trap. */
0223     would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL;
0224 
0225     /* If trapping, we only want to signal one bit. */
0226     if (would_trap != 0) {
0227         eflag &= ((fsr & FSR_TEM_MASK) >> FSR_TEM_SHIFT);
0228         if ((eflag & (eflag - 1)) != 0) {
0229             if (eflag & FP_EX_INVALID)
0230                 eflag = FP_EX_INVALID;
0231             else if (eflag & FP_EX_OVERFLOW)
0232                 eflag = FP_EX_OVERFLOW;
0233             else if (eflag & FP_EX_UNDERFLOW)
0234                 eflag = FP_EX_UNDERFLOW;
0235             else if (eflag & FP_EX_DIVZERO)
0236                 eflag = FP_EX_DIVZERO;
0237             else if (eflag & FP_EX_INEXACT)
0238                 eflag = FP_EX_INEXACT;
0239         }
0240     }
0241 
0242     /* Set CEXC, here is the rule:
0243      *
0244      *    In general all FPU ops will set one and only one
0245      *    bit in the CEXC field, this is always the case
0246      *    when the IEEE exception trap is enabled in TEM.
0247      */
0248     fsr &= ~(FSR_CEXC_MASK);
0249     fsr |= ((long)eflag << FSR_CEXC_SHIFT);
0250 
0251     /* Set the AEXC field, rule is:
0252      *
0253      *    If a trap would not be generated, the
0254      *    CEXC just generated is OR'd into the
0255      *    existing value of AEXC.
0256      */
0257     if (would_trap == 0)
0258         fsr |= ((long)eflag << FSR_AEXC_SHIFT);
0259 
0260     /* If trapping, indicate fault trap type IEEE. */
0261     if (would_trap != 0)
0262         fsr |= (1UL << 14);
0263 
0264     *pfsr = fsr;
0265 
0266     return (would_trap ? 0 : 1);
0267 }
0268 
0269 typedef union {
0270     u32 s;
0271     u64 d;
0272     u64 q[2];
0273 } *argp;
0274 
0275 static int do_one_mathemu(u32 insn, unsigned long *pfsr, unsigned long *fregs)
0276 {
0277     /* Emulate the given insn, updating fsr and fregs appropriately. */
0278     int type = 0;
0279     /* r is rd, b is rs2 and a is rs1. The *u arg tells
0280        whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack)
0281        non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */
0282 #define TYPE(dummy, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru << 8) | (r << 6)
0283     int freg;
0284     argp rs1 = NULL, rs2 = NULL, rd = NULL;
0285     FP_DECL_EX;
0286     FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
0287     FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
0288     FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
0289     int IR;
0290     long fsr;
0291 
0292 #ifdef DEBUG_MATHEMU
0293     printk("In do_mathemu(), emulating %08lx\n", insn);
0294 #endif
0295 
0296     if ((insn & 0xc1f80000) == 0x81a00000)  /* FPOP1 */ {
0297         switch ((insn >> 5) & 0x1ff) {
0298         case FSQRTQ: TYPE(3,3,1,3,1,0,0); break;
0299         case FADDQ:
0300         case FSUBQ:
0301         case FMULQ:
0302         case FDIVQ: TYPE(3,3,1,3,1,3,1); break;
0303         case FDMULQ: TYPE(3,3,1,2,1,2,1); break;
0304         case FQTOS: TYPE(3,1,1,3,1,0,0); break;
0305         case FQTOD: TYPE(3,2,1,3,1,0,0); break;
0306         case FITOQ: TYPE(3,3,1,1,0,0,0); break;
0307         case FSTOQ: TYPE(3,3,1,1,1,0,0); break;
0308         case FDTOQ: TYPE(3,3,1,2,1,0,0); break;
0309         case FQTOI: TYPE(3,1,0,3,1,0,0); break;
0310         case FSQRTS: TYPE(2,1,1,1,1,0,0); break;
0311         case FSQRTD: TYPE(2,2,1,2,1,0,0); break;
0312         case FADDD:
0313         case FSUBD:
0314         case FMULD:
0315         case FDIVD: TYPE(2,2,1,2,1,2,1); break;
0316         case FADDS:
0317         case FSUBS:
0318         case FMULS:
0319         case FDIVS: TYPE(2,1,1,1,1,1,1); break;
0320         case FSMULD: TYPE(2,2,1,1,1,1,1); break;
0321         case FDTOS: TYPE(2,1,1,2,1,0,0); break;
0322         case FSTOD: TYPE(2,2,1,1,1,0,0); break;
0323         case FSTOI: TYPE(2,1,0,1,1,0,0); break;
0324         case FDTOI: TYPE(2,1,0,2,1,0,0); break;
0325         case FITOS: TYPE(2,1,1,1,0,0,0); break;
0326         case FITOD: TYPE(2,2,1,1,0,0,0); break;
0327         case FMOVS:
0328         case FABSS:
0329         case FNEGS: TYPE(2,1,0,1,0,0,0); break;
0330         }
0331     } else if ((insn & 0xc1f80000) == 0x81a80000)   /* FPOP2 */ {
0332         switch ((insn >> 5) & 0x1ff) {
0333         case FCMPS: TYPE(3,0,0,1,1,1,1); break;
0334         case FCMPES: TYPE(3,0,0,1,1,1,1); break;
0335         case FCMPD: TYPE(3,0,0,2,1,2,1); break;
0336         case FCMPED: TYPE(3,0,0,2,1,2,1); break;
0337         case FCMPQ: TYPE(3,0,0,3,1,3,1); break;
0338         case FCMPEQ: TYPE(3,0,0,3,1,3,1); break;
0339         }
0340     }
0341 
0342     if (!type) {    /* oops, didn't recognise that FPop */
0343 #ifdef DEBUG_MATHEMU
0344         printk("attempt to emulate unrecognised FPop!\n");
0345 #endif
0346         return 0;
0347     }
0348 
0349     /* Decode the registers to be used */
0350     freg = (*pfsr >> 14) & 0xf;
0351 
0352     *pfsr &= ~0x1c000;              /* clear the traptype bits */
0353     
0354     freg = ((insn >> 14) & 0x1f);
0355     switch (type & 0x3) {               /* is rs1 single, double or quad? */
0356     case 3:
0357         if (freg & 3) {             /* quadwords must have bits 4&5 of the */
0358                             /* encoded reg. number set to zero. */
0359             *pfsr |= (6 << 14);
0360             return 0;           /* simulate invalid_fp_register exception */
0361         }
0362         fallthrough;
0363     case 2:
0364         if (freg & 1) {             /* doublewords must have bit 5 zeroed */
0365             *pfsr |= (6 << 14);
0366             return 0;
0367         }
0368     }
0369     rs1 = (argp)&fregs[freg];
0370     switch (type & 0x7) {
0371     case 7: FP_UNPACK_QP (QA, rs1); break;
0372     case 6: FP_UNPACK_DP (DA, rs1); break;
0373     case 5: FP_UNPACK_SP (SA, rs1); break;
0374     }
0375     freg = (insn & 0x1f);
0376     switch ((type >> 3) & 0x3) {            /* same again for rs2 */
0377     case 3:
0378         if (freg & 3) {             /* quadwords must have bits 4&5 of the */
0379                             /* encoded reg. number set to zero. */
0380             *pfsr |= (6 << 14);
0381             return 0;           /* simulate invalid_fp_register exception */
0382         }
0383         fallthrough;
0384     case 2:
0385         if (freg & 1) {             /* doublewords must have bit 5 zeroed */
0386             *pfsr |= (6 << 14);
0387             return 0;
0388         }
0389     }
0390     rs2 = (argp)&fregs[freg];
0391     switch ((type >> 3) & 0x7) {
0392     case 7: FP_UNPACK_QP (QB, rs2); break;
0393     case 6: FP_UNPACK_DP (DB, rs2); break;
0394     case 5: FP_UNPACK_SP (SB, rs2); break;
0395     }
0396     freg = ((insn >> 25) & 0x1f);
0397     switch ((type >> 6) & 0x3) {            /* and finally rd. This one's a bit different */
0398     case 0:                     /* dest is fcc. (this must be FCMPQ or FCMPEQ) */
0399         if (freg) {             /* V8 has only one set of condition codes, so */
0400                             /* anything but 0 in the rd field is an error */
0401             *pfsr |= (6 << 14);     /* (should probably flag as invalid opcode */
0402             return 0;           /* but SIGFPE will do :-> ) */
0403         }
0404         break;
0405     case 3:
0406         if (freg & 3) {             /* quadwords must have bits 4&5 of the */
0407                             /* encoded reg. number set to zero. */
0408             *pfsr |= (6 << 14);
0409             return 0;           /* simulate invalid_fp_register exception */
0410         }
0411         fallthrough;
0412     case 2:
0413         if (freg & 1) {             /* doublewords must have bit 5 zeroed */
0414             *pfsr |= (6 << 14);
0415             return 0;
0416         }
0417         fallthrough;
0418     case 1:
0419         rd = (void *)&fregs[freg];
0420         break;
0421     }
0422 #ifdef DEBUG_MATHEMU
0423     printk("executing insn...\n");
0424 #endif
0425     /* do the Right Thing */
0426     switch ((insn >> 5) & 0x1ff) {
0427     /* + */
0428     case FADDS: FP_ADD_S (SR, SA, SB); break;
0429     case FADDD: FP_ADD_D (DR, DA, DB); break;
0430     case FADDQ: FP_ADD_Q (QR, QA, QB); break;
0431     /* - */
0432     case FSUBS: FP_SUB_S (SR, SA, SB); break;
0433     case FSUBD: FP_SUB_D (DR, DA, DB); break;
0434     case FSUBQ: FP_SUB_Q (QR, QA, QB); break;
0435     /* * */
0436     case FMULS: FP_MUL_S (SR, SA, SB); break;
0437     case FSMULD: FP_CONV (D, S, 2, 1, DA, SA);
0438              FP_CONV (D, S, 2, 1, DB, SB);
0439     case FMULD: FP_MUL_D (DR, DA, DB); break;
0440     case FDMULQ: FP_CONV (Q, D, 4, 2, QA, DA);
0441              FP_CONV (Q, D, 4, 2, QB, DB);
0442     case FMULQ: FP_MUL_Q (QR, QA, QB); break;
0443     /* / */
0444     case FDIVS: FP_DIV_S (SR, SA, SB); break;
0445     case FDIVD: FP_DIV_D (DR, DA, DB); break;
0446     case FDIVQ: FP_DIV_Q (QR, QA, QB); break;
0447     /* sqrt */
0448     case FSQRTS: FP_SQRT_S (SR, SB); break;
0449     case FSQRTD: FP_SQRT_D (DR, DB); break;
0450     case FSQRTQ: FP_SQRT_Q (QR, QB); break;
0451     /* mov */
0452     case FMOVS: rd->s = rs2->s; break;
0453     case FABSS: rd->s = rs2->s & 0x7fffffff; break;
0454     case FNEGS: rd->s = rs2->s ^ 0x80000000; break;
0455     /* float to int */
0456     case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break;
0457     case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break;
0458     case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break;
0459     /* int to float */
0460     case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break;
0461     case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break;
0462     case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break;
0463     /* float to float */
0464     case FSTOD: FP_CONV (D, S, 2, 1, DR, SB); break;
0465     case FSTOQ: FP_CONV (Q, S, 4, 1, QR, SB); break;
0466     case FDTOQ: FP_CONV (Q, D, 4, 2, QR, DB); break;
0467     case FDTOS: FP_CONV (S, D, 1, 2, SR, DB); break;
0468     case FQTOS: FP_CONV (S, Q, 1, 4, SR, QB); break;
0469     case FQTOD: FP_CONV (D, Q, 2, 4, DR, QB); break;
0470     /* comparison */
0471     case FCMPS:
0472     case FCMPES:
0473         FP_CMP_S(IR, SB, SA, 3);
0474         if (IR == 3 &&
0475             (((insn >> 5) & 0x1ff) == FCMPES ||
0476              FP_ISSIGNAN_S(SA) ||
0477              FP_ISSIGNAN_S(SB)))
0478             FP_SET_EXCEPTION (FP_EX_INVALID);
0479         break;
0480     case FCMPD:
0481     case FCMPED:
0482         FP_CMP_D(IR, DB, DA, 3);
0483         if (IR == 3 &&
0484             (((insn >> 5) & 0x1ff) == FCMPED ||
0485              FP_ISSIGNAN_D(DA) ||
0486              FP_ISSIGNAN_D(DB)))
0487             FP_SET_EXCEPTION (FP_EX_INVALID);
0488         break;
0489     case FCMPQ:
0490     case FCMPEQ:
0491         FP_CMP_Q(IR, QB, QA, 3);
0492         if (IR == 3 &&
0493             (((insn >> 5) & 0x1ff) == FCMPEQ ||
0494              FP_ISSIGNAN_Q(QA) ||
0495              FP_ISSIGNAN_Q(QB)))
0496             FP_SET_EXCEPTION (FP_EX_INVALID);
0497     }
0498     if (!FP_INHIBIT_RESULTS) {
0499         switch ((type >> 6) & 0x7) {
0500         case 0: fsr = *pfsr;
0501             if (IR == -1) IR = 2;
0502             /* fcc is always fcc0 */
0503             fsr &= ~0xc00; fsr |= (IR << 10);
0504             *pfsr = fsr;
0505             break;
0506         case 1: rd->s = IR; break;
0507         case 5: FP_PACK_SP (rd, SR); break;
0508         case 6: FP_PACK_DP (rd, DR); break;
0509         case 7: FP_PACK_QP (rd, QR); break;
0510         }
0511     }
0512     if (_fex == 0)
0513         return 1;               /* success! */
0514     return record_exception(pfsr, _fex);
0515 }
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