sparc/lib/clear_page.S

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* clear_page.S: UltraSparc optimized clear page.
0003  *
0004  * Copyright (C) 1996, 1998, 1999, 2000, 2004 David S. Miller (davem@redhat.com)
0005  * Copyright (C) 1997 Jakub Jelinek (jakub@redhat.com)
0006  */
0007
0008 #include <linux/pgtable.h>
0009 #include <asm/visasm.h>
0010 #include <asm/thread_info.h>
0011 #include <asm/page.h>
0012 #include <asm/spitfire.h>
0013 #include <asm/head.h>
0014 #include <asm/export.h>
0015
0016     /* What we used to do was lock a TLB entry into a specific
0017      * TLB slot, clear the page with interrupts disabled, then
0018      * restore the original TLB entry.  This was great for
0019      * disturbing the TLB as little as possible, but it meant
0020      * we had to keep interrupts disabled for a long time.
0021      *
0022      * Now, we simply use the normal TLB loading mechanism,
0023      * and this makes the cpu choose a slot all by itself.
0024      * Then we do a normal TLB flush on exit.  We need only
0025      * disable preemption during the clear.
0026      */
0027
0028     .text
0029
0030     .globl      _clear_page
0031     EXPORT_SYMBOL(_clear_page)
0032 _clear_page:        /* %o0=dest */
0033     ba,pt       %xcc, clear_page_common
0034      clr        %o4
0035
0036     /* This thing is pretty important, it shows up
0037      * on the profiles via do_anonymous_page().
0038      */
0039     .align      32
0040     .globl      clear_user_page
0041     EXPORT_SYMBOL(clear_user_page)
0042 clear_user_page:    /* %o0=dest, %o1=vaddr */
0043     lduw        [%g6 + TI_PRE_COUNT], %o2
0044     sethi       %hi(PAGE_OFFSET), %g2
0045     sethi       %hi(PAGE_SIZE), %o4
0046
0047     ldx     [%g2 + %lo(PAGE_OFFSET)], %g2
0048     sethi       %hi(PAGE_KERNEL_LOCKED), %g3
0049
0050     ldx     [%g3 + %lo(PAGE_KERNEL_LOCKED)], %g3
0051     sub     %o0, %g2, %g1       ! paddr
0052
0053     and     %o1, %o4, %o0       ! vaddr D-cache alias bit
0054
0055     or      %g1, %g3, %g1       ! TTE data
0056     sethi       %hi(TLBTEMP_BASE), %o3
0057
0058     add     %o2, 1, %o4
0059     add     %o0, %o3, %o0       ! TTE vaddr
0060
0061     /* Disable preemption.  */
0062     mov     TLB_TAG_ACCESS, %g3
0063     stw     %o4, [%g6 + TI_PRE_COUNT]
0064
0065     /* Load TLB entry.  */
0066     rdpr        %pstate, %o4
0067     wrpr        %o4, PSTATE_IE, %pstate
0068     stxa        %o0, [%g3] ASI_DMMU
0069     stxa        %g1, [%g0] ASI_DTLB_DATA_IN
0070     sethi       %hi(KERNBASE), %g1
0071     flush       %g1
0072     wrpr        %o4, 0x0, %pstate
0073
0074     mov     1, %o4
0075
0076 clear_page_common:
0077     VISEntryHalf
0078     membar      #StoreLoad | #StoreStore | #LoadStore
0079     fzero       %f0
0080     sethi       %hi(PAGE_SIZE/64), %o1
0081     mov     %o0, %g1        ! remember vaddr for tlbflush
0082     fzero       %f2
0083     or      %o1, %lo(PAGE_SIZE/64), %o1
0084     faddd       %f0, %f2, %f4
0085     fmuld       %f0, %f2, %f6
0086     faddd       %f0, %f2, %f8
0087     fmuld       %f0, %f2, %f10
0088
0089     faddd       %f0, %f2, %f12
0090     fmuld       %f0, %f2, %f14
0091 1:  stda        %f0, [%o0 + %g0] ASI_BLK_P
0092     subcc       %o1, 1, %o1
0093     bne,pt      %icc, 1b
0094      add        %o0, 0x40, %o0
0095     membar      #Sync
0096     VISExitHalf
0097
0098     brz,pn      %o4, out
0099      nop
0100
0101     stxa        %g0, [%g1] ASI_DMMU_DEMAP
0102     membar      #Sync
0103     stw     %o2, [%g6 + TI_PRE_COUNT]
0104
0105 out:    retl
0106      nop
0107