sparc/lib/VISsave.S

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * VISsave.S: Code for saving FPU register state for
0004  *            VIS routines. One should not call this directly,
0005  *            but use macros provided in <asm/visasm.h>.
0006  *
0007  * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
0008  */
0009
0010 #include <linux/linkage.h>
0011
0012 #include <asm/asi.h>
0013 #include <asm/page.h>
0014 #include <asm/ptrace.h>
0015 #include <asm/visasm.h>
0016 #include <asm/thread_info.h>
0017 #include <asm/export.h>
0018
0019     /* On entry: %o5=current FPRS value, %g7 is callers address */
0020     /* May clobber %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
0021
0022     /* Nothing special need be done here to handle pre-emption, this
0023      * FPU save/restore mechanism is already preemption safe.
0024      */
0025     .text
0026     .align      32
0027 ENTRY(VISenter)
0028     ldub        [%g6 + TI_FPDEPTH], %g1
0029     brnz,a,pn   %g1, 1f
0030      cmp        %g1, 1
0031     stb     %g0, [%g6 + TI_FPSAVED]
0032     stx     %fsr, [%g6 + TI_XFSR]
0033 9:  jmpl        %g7 + %g0, %g0
0034      nop
0035 1:  bne,pn      %icc, 2f
0036
0037      srl        %g1, 1, %g1
0038 vis1:   ldub        [%g6 + TI_FPSAVED], %g3
0039     stx     %fsr, [%g6 + TI_XFSR]
0040     or      %g3, %o5, %g3
0041     stb     %g3, [%g6 + TI_FPSAVED]
0042     rd      %gsr, %g3
0043     clr     %g1
0044     ba,pt       %xcc, 3f
0045
0046      stx        %g3, [%g6 + TI_GSR]
0047 2:  add     %g6, %g1, %g3
0048     mov     FPRS_DU | FPRS_DL | FPRS_FEF, %o5
0049     sll     %g1, 3, %g1
0050     stb     %o5, [%g3 + TI_FPSAVED]
0051     rd      %gsr, %g2
0052     add     %g6, %g1, %g3
0053     stx     %g2, [%g3 + TI_GSR]
0054
0055     add     %g6, %g1, %g2
0056     stx     %fsr, [%g2 + TI_XFSR]
0057     sll     %g1, 5, %g1
0058 3:  andcc       %o5, FPRS_DL|FPRS_DU, %g0
0059     be,pn       %icc, 9b
0060      add        %g6, TI_FPREGS, %g2
0061     andcc       %o5, FPRS_DL, %g0
0062
0063     be,pn       %icc, 4f
0064      add        %g6, TI_FPREGS+0x40, %g3
0065     membar      #Sync
0066     stda        %f0, [%g2 + %g1] ASI_BLK_P
0067     stda        %f16, [%g3 + %g1] ASI_BLK_P
0068     membar      #Sync
0069     andcc       %o5, FPRS_DU, %g0
0070     be,pn       %icc, 5f
0071 4:   add        %g1, 128, %g1
0072     membar      #Sync
0073     stda        %f32, [%g2 + %g1] ASI_BLK_P
0074
0075     stda        %f48, [%g3 + %g1] ASI_BLK_P
0076 5:  membar      #Sync
0077     ba,pt       %xcc, 80f
0078      nop
0079
0080     .align      32
0081 80: jmpl        %g7 + %g0, %g0
0082      nop
0083 ENDPROC(VISenter)
0084 EXPORT_SYMBOL(VISenter)