sparc/kernel/winfixup.S

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* winfixup.S: Handle cases where user stack pointer is found to be bogus.
0003  *
0004  * Copyright (C) 1997, 2006 David S. Miller (davem@davemloft.net)
0005  */
0006
0007 #include <asm/asi.h>
0008 #include <asm/head.h>
0009 #include <asm/page.h>
0010 #include <asm/ptrace.h>
0011 #include <asm/processor.h>
0012 #include <asm/spitfire.h>
0013 #include <asm/thread_info.h>
0014
0015     .text
0016
0017     /* It used to be the case that these register window fault
0018      * handlers could run via the save and restore instructions
0019      * done by the trap entry and exit code.  They now do the
0020      * window spill/fill by hand, so that case no longer can occur.
0021      */
0022
0023     .align  32
0024 fill_fixup:
0025     TRAP_LOAD_THREAD_REG(%g6, %g1)
0026     rdpr    %tstate, %g1
0027     and %g1, TSTATE_CWP, %g1
0028     or  %g4, FAULT_CODE_WINFIXUP, %g4
0029     stb %g4, [%g6 + TI_FAULT_CODE]
0030     stx %g5, [%g6 + TI_FAULT_ADDR]
0031     wrpr    %g1, %cwp
0032     ba,pt   %xcc, etrap
0033      rd %pc, %g7
0034     call    do_sparc64_fault
0035      add    %sp, PTREGS_OFF, %o0
0036     ba,a,pt %xcc, rtrap
0037
0038     /* Be very careful about usage of the trap globals here.
0039      * You cannot touch %g5 as that has the fault information.
0040      */
0041 spill_fixup:
0042 spill_fixup_mna:
0043 spill_fixup_dax:
0044     TRAP_LOAD_THREAD_REG(%g6, %g1)
0045     ldx [%g6 + TI_FLAGS], %g1
0046     andcc   %sp, 0x1, %g0
0047     movne   %icc, 0, %g1
0048     andcc   %g1, _TIF_32BIT, %g0
0049     ldub    [%g6 + TI_WSAVED], %g1
0050     sll %g1, 3, %g3
0051     add %g6, %g3, %g3
0052     stx %sp, [%g3 + TI_RWIN_SPTRS]
0053     sll %g1, 7, %g3
0054     bne,pt  %xcc, 1f
0055      add    %g6, %g3, %g3
0056     stx %l0, [%g3 + TI_REG_WINDOW + 0x00]
0057     stx %l1, [%g3 + TI_REG_WINDOW + 0x08]
0058     stx %l2, [%g3 + TI_REG_WINDOW + 0x10]
0059     stx %l3, [%g3 + TI_REG_WINDOW + 0x18]
0060     stx %l4, [%g3 + TI_REG_WINDOW + 0x20]
0061     stx %l5, [%g3 + TI_REG_WINDOW + 0x28]
0062     stx %l6, [%g3 + TI_REG_WINDOW + 0x30]
0063     stx %l7, [%g3 + TI_REG_WINDOW + 0x38]
0064     stx %i0, [%g3 + TI_REG_WINDOW + 0x40]
0065     stx %i1, [%g3 + TI_REG_WINDOW + 0x48]
0066     stx %i2, [%g3 + TI_REG_WINDOW + 0x50]
0067     stx %i3, [%g3 + TI_REG_WINDOW + 0x58]
0068     stx %i4, [%g3 + TI_REG_WINDOW + 0x60]
0069     stx %i5, [%g3 + TI_REG_WINDOW + 0x68]
0070     stx %i6, [%g3 + TI_REG_WINDOW + 0x70]
0071     ba,pt   %xcc, 2f
0072      stx    %i7, [%g3 + TI_REG_WINDOW + 0x78]
0073 1:  stw %l0, [%g3 + TI_REG_WINDOW + 0x00]
0074     stw %l1, [%g3 + TI_REG_WINDOW + 0x04]
0075     stw %l2, [%g3 + TI_REG_WINDOW + 0x08]
0076     stw %l3, [%g3 + TI_REG_WINDOW + 0x0c]
0077     stw %l4, [%g3 + TI_REG_WINDOW + 0x10]
0078     stw %l5, [%g3 + TI_REG_WINDOW + 0x14]
0079     stw %l6, [%g3 + TI_REG_WINDOW + 0x18]
0080     stw %l7, [%g3 + TI_REG_WINDOW + 0x1c]
0081     stw %i0, [%g3 + TI_REG_WINDOW + 0x20]
0082     stw %i1, [%g3 + TI_REG_WINDOW + 0x24]
0083     stw %i2, [%g3 + TI_REG_WINDOW + 0x28]
0084     stw %i3, [%g3 + TI_REG_WINDOW + 0x2c]
0085     stw %i4, [%g3 + TI_REG_WINDOW + 0x30]
0086     stw %i5, [%g3 + TI_REG_WINDOW + 0x34]
0087     stw %i6, [%g3 + TI_REG_WINDOW + 0x38]
0088     stw %i7, [%g3 + TI_REG_WINDOW + 0x3c]
0089 2:  add %g1, 1, %g1
0090     stb %g1, [%g6 + TI_WSAVED]
0091     rdpr    %tstate, %g1
0092     andcc   %g1, TSTATE_PRIV, %g0
0093     saved
0094     be,pn   %xcc, 1f
0095      and    %g1, TSTATE_CWP, %g1
0096     retry
0097 1:  mov FAULT_CODE_WRITE | FAULT_CODE_DTLB | FAULT_CODE_WINFIXUP, %g4
0098     stb %g4, [%g6 + TI_FAULT_CODE]
0099     stx %g5, [%g6 + TI_FAULT_ADDR]
0100     wrpr    %g1, %cwp
0101     ba,pt   %xcc, etrap
0102      rd %pc, %g7
0103     call    do_sparc64_fault
0104      add    %sp, PTREGS_OFF, %o0
0105     ba,a,pt %xcc, rtrap
0106
0107 winfix_mna:
0108     andn    %g3, 0x7f, %g3
0109     add %g3, 0x78, %g3
0110     wrpr    %g3, %tnpc
0111     done
0112
0113 fill_fixup_mna:
0114     rdpr    %tstate, %g1
0115     and %g1, TSTATE_CWP, %g1
0116     wrpr    %g1, %cwp
0117     ba,pt   %xcc, etrap
0118      rd %pc, %g7
0119     sethi   %hi(tlb_type), %g1
0120     lduw    [%g1 + %lo(tlb_type)], %g1
0121     cmp %g1, 3
0122     bne,pt  %icc, 1f
0123      add    %sp, PTREGS_OFF, %o0
0124     mov %l4, %o2
0125     call    sun4v_do_mna
0126      mov    %l5, %o1
0127     ba,a,pt %xcc, rtrap
0128 1:  mov %l4, %o1
0129     mov %l5, %o2
0130     call    mem_address_unaligned
0131      nop
0132     ba,a,pt %xcc, rtrap
0133
0134 winfix_dax:
0135     andn    %g3, 0x7f, %g3
0136     add %g3, 0x74, %g3
0137     wrpr    %g3, %tnpc
0138     done
0139
0140 fill_fixup_dax:
0141     rdpr    %tstate, %g1
0142     and %g1, TSTATE_CWP, %g1
0143     wrpr    %g1, %cwp
0144     ba,pt   %xcc, etrap
0145      rd %pc, %g7
0146     sethi   %hi(tlb_type), %g1
0147     mov %l4, %o1
0148     lduw    [%g1 + %lo(tlb_type)], %g1
0149     mov %l5, %o2
0150     cmp %g1, 3
0151     bne,pt  %icc, 1f
0152      add    %sp, PTREGS_OFF, %o0
0153     call    sun4v_data_access_exception
0154      nop
0155     ba,a,pt %xcc, rtrap
0156      nop
0157 1:  call    spitfire_data_access_exception
0158      nop
0159     ba,a,pt %xcc, rtrap
0160      nop