sparc/kernel/trampoline_32.S

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * trampoline.S: SMP cpu boot-up trampoline code.
0004  *
0005  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
0006  * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
0007  */
0008
0009 #include <asm/head.h>
0010 #include <asm/psr.h>
0011 #include <asm/page.h>
0012 #include <asm/asi.h>
0013 #include <asm/ptrace.h>
0014 #include <asm/vaddrs.h>
0015 #include <asm/contregs.h>
0016 #include <asm/thread_info.h>
0017
0018     .globl sun4m_cpu_startup
0019     .globl sun4d_cpu_startup
0020
0021     .align 4
0022
0023 /* When we start up a cpu for the first time it enters this routine.
0024  * This initializes the chip from whatever state the prom left it
0025  * in and sets PIL in %psr to 15, no irqs.
0026  */
0027
0028 sun4m_cpu_startup:
0029 cpu1_startup:
0030     sethi   %hi(trapbase_cpu1), %g3
0031     b   1f
0032      or %g3, %lo(trapbase_cpu1), %g3
0033
0034 cpu2_startup:
0035     sethi   %hi(trapbase_cpu2), %g3
0036     b   1f
0037      or %g3, %lo(trapbase_cpu2), %g3
0038
0039 cpu3_startup:
0040     sethi   %hi(trapbase_cpu3), %g3
0041     b   1f
0042      or %g3, %lo(trapbase_cpu3), %g3
0043
0044 1:
0045     /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
0046     set (PSR_PIL | PSR_S | PSR_PS), %g1
0047     wr  %g1, 0x0, %psr      ! traps off though
0048     WRITE_PAUSE
0049
0050     /* Our %wim is one behind CWP */
0051     mov 2, %g1
0052     wr  %g1, 0x0, %wim
0053     WRITE_PAUSE
0054
0055     /* This identifies "this cpu". */
0056     wr  %g3, 0x0, %tbr
0057     WRITE_PAUSE
0058
0059     /* Give ourselves a stack and curptr. */
0060     set current_set, %g5
0061     srl %g3, 10, %g4
0062     and %g4, 0xc, %g4
0063     ld  [%g5 + %g4], %g6
0064
0065     sethi   %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
0066     or  %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
0067     add %g6, %sp, %sp
0068
0069     /* Turn on traps (PSR_ET). */
0070     rd  %psr, %g1
0071     wr  %g1, PSR_ET, %psr   ! traps on
0072     WRITE_PAUSE
0073
0074     /* Init our caches, etc. */
0075     set poke_srmmu, %g5
0076     ld  [%g5], %g5
0077     call    %g5
0078      nop
0079
0080     /* Start this processor. */
0081     call    smp_callin
0082      nop
0083
0084     b,a smp_panic
0085
0086     .text
0087     .align  4
0088
0089 smp_panic:
0090     call    cpu_panic
0091      nop
0092
0093 /* CPUID in bootbus can be found at PA 0xff0140000 */
0094 #define SUN4D_BOOTBUS_CPUID 0xf0140000
0095
0096     .align  4
0097
0098 sun4d_cpu_startup:
0099     /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
0100     set (PSR_PIL | PSR_S | PSR_PS), %g1
0101     wr  %g1, 0x0, %psr      ! traps off though
0102     WRITE_PAUSE
0103
0104     /* Our %wim is one behind CWP */
0105     mov 2, %g1
0106     wr  %g1, 0x0, %wim
0107     WRITE_PAUSE
0108
0109     /* Set tbr - we use just one trap table. */
0110     set trapbase, %g1
0111     wr  %g1, 0x0, %tbr
0112     WRITE_PAUSE
0113
0114     /* Get our CPU id out of bootbus */
0115     set SUN4D_BOOTBUS_CPUID, %g3
0116     lduba   [%g3] ASI_M_CTL, %g3
0117     and %g3, 0xf8, %g3
0118     srl %g3, 3, %g1
0119     sta %g1, [%g0] ASI_M_VIKING_TMP1
0120
0121     /* Give ourselves a stack and curptr. */
0122     set current_set, %g5
0123     srl %g3, 1, %g4
0124     ld  [%g5 + %g4], %g6
0125
0126     sethi   %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
0127     or  %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
0128     add %g6, %sp, %sp
0129
0130     /* Turn on traps (PSR_ET). */
0131     rd  %psr, %g1
0132     wr  %g1, PSR_ET, %psr   ! traps on
0133     WRITE_PAUSE
0134
0135     /* Init our caches, etc. */
0136     set poke_srmmu, %g5
0137     ld  [%g5], %g5
0138     call    %g5
0139      nop
0140
0141     /* Start this processor. */
0142     call    smp_callin
0143      nop
0144
0145     b,a smp_panic
0146
0147     .align  4
0148         .global leon_smp_cpu_startup, smp_penguin_ctable
0149
0150 leon_smp_cpu_startup:
0151
0152         set smp_penguin_ctable,%g1
0153         ld [%g1+4],%g1
0154         srl %g1,4,%g1
0155         set 0x00000100,%g5 /* SRMMU_CTXTBL_PTR */
0156     sta %g1, [%g5] ASI_LEON_MMUREGS
0157
0158     /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
0159     set (PSR_PIL | PSR_S | PSR_PS), %g1
0160     wr  %g1, 0x0, %psr      ! traps off though
0161     WRITE_PAUSE
0162
0163     /* Our %wim is one behind CWP */
0164     mov 2, %g1
0165     wr  %g1, 0x0, %wim
0166     WRITE_PAUSE
0167
0168     /* Set tbr - we use just one trap table. */
0169     set trapbase, %g1
0170     wr  %g1, 0x0, %tbr
0171     WRITE_PAUSE
0172
0173     /* Get our CPU id */
0174         rd     %asr17,%g3
0175
0176     /* Give ourselves a stack and curptr. */
0177     set current_set, %g5
0178     srl %g3, 28, %g4
0179     sll %g4, 2, %g4
0180     ld  [%g5 + %g4], %g6
0181
0182     sethi   %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
0183     or  %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
0184     add %g6, %sp, %sp
0185
0186     /* Turn on traps (PSR_ET). */
0187     rd  %psr, %g1
0188     wr  %g1, PSR_ET, %psr   ! traps on
0189     WRITE_PAUSE
0190
0191     /* Init our caches, etc. */
0192     set poke_srmmu, %g5
0193     ld  [%g5], %g5
0194     call    %g5
0195      nop
0196
0197     /* Start this processor. */
0198     call    smp_callin
0199      nop
0200
0201     b,a smp_panic