sparc/kernel/time_32.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* linux/arch/sparc/kernel/time.c
0003  *
0004  * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
0005  * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
0006  *
0007  * Chris Davis (cdavis@cois.on.ca) 03/27/1998
0008  * Added support for the intersil on the sun4/4200
0009  *
0010  * Gleb Raiko (rajko@mech.math.msu.su) 08/18/1998
0011  * Support for MicroSPARC-IIep, PCI CPU.
0012  *
0013  * This file handles the Sparc specific time handling details.
0014  *
0015  * 1997-09-10   Updated NTP code according to technical memorandum Jan '96
0016  *      "A Kernel Model for Precision Timekeeping" by Dave Mills
0017  */
0018 #include <linux/errno.h>
0019 #include <linux/module.h>
0020 #include <linux/sched.h>
0021 #include <linux/kernel.h>
0022 #include <linux/param.h>
0023 #include <linux/string.h>
0024 #include <linux/mm.h>
0025 #include <linux/interrupt.h>
0026 #include <linux/time.h>
0027 #include <linux/rtc/m48t59.h>
0028 #include <linux/timex.h>
0029 #include <linux/clocksource.h>
0030 #include <linux/clockchips.h>
0031 #include <linux/init.h>
0032 #include <linux/pci.h>
0033 #include <linux/ioport.h>
0034 #include <linux/profile.h>
0035 #include <linux/of.h>
0036 #include <linux/of_device.h>
0037 #include <linux/platform_device.h>
0038
0039 #include <asm/mc146818rtc.h>
0040 #include <asm/oplib.h>
0041 #include <asm/timex.h>
0042 #include <asm/timer.h>
0043 #include <asm/irq.h>
0044 #include <asm/io.h>
0045 #include <asm/idprom.h>
0046 #include <asm/page.h>
0047 #include <asm/pcic.h>
0048 #include <asm/irq_regs.h>
0049 #include <asm/setup.h>
0050
0051 #include "kernel.h"
0052 #include "irq.h"
0053
0054 static __cacheline_aligned_in_smp DEFINE_SEQLOCK(timer_cs_lock);
0055 static __volatile__ u64 timer_cs_internal_counter = 0;
0056 static char timer_cs_enabled = 0;
0057
0058 static struct clock_event_device timer_ce;
0059 static char timer_ce_enabled = 0;
0060
0061 #ifdef CONFIG_SMP
0062 DEFINE_PER_CPU(struct clock_event_device, sparc32_clockevent);
0063 #endif
0064
0065 DEFINE_SPINLOCK(rtc_lock);
0066 EXPORT_SYMBOL(rtc_lock);
0067
0068 unsigned long profile_pc(struct pt_regs *regs)
0069 {
0070     extern char __copy_user_begin[], __copy_user_end[];
0071     extern char __bzero_begin[], __bzero_end[];
0072
0073     unsigned long pc = regs->pc;
0074
0075     if (in_lock_functions(pc) ||
0076         (pc >= (unsigned long) __copy_user_begin &&
0077          pc < (unsigned long) __copy_user_end) ||
0078         (pc >= (unsigned long) __bzero_begin &&
0079          pc < (unsigned long) __bzero_end))
0080         pc = regs->u_regs[UREG_RETPC];
0081     return pc;
0082 }
0083
0084 EXPORT_SYMBOL(profile_pc);
0085
0086 volatile u32 __iomem *master_l10_counter;
0087
0088 irqreturn_t notrace timer_interrupt(int dummy, void *dev_id)
0089 {
0090     if (timer_cs_enabled) {
0091         write_seqlock(&timer_cs_lock);
0092         timer_cs_internal_counter++;
0093         sparc_config.clear_clock_irq();
0094         write_sequnlock(&timer_cs_lock);
0095     } else {
0096         sparc_config.clear_clock_irq();
0097     }
0098
0099     if (timer_ce_enabled)
0100         timer_ce.event_handler(&timer_ce);
0101
0102     return IRQ_HANDLED;
0103 }
0104
0105 static int timer_ce_shutdown(struct clock_event_device *evt)
0106 {
0107     timer_ce_enabled = 0;
0108     smp_mb();
0109     return 0;
0110 }
0111
0112 static int timer_ce_set_periodic(struct clock_event_device *evt)
0113 {
0114     timer_ce_enabled = 1;
0115     smp_mb();
0116     return 0;
0117 }
0118
0119 static __init void setup_timer_ce(void)
0120 {
0121     struct clock_event_device *ce = &timer_ce;
0122
0123     BUG_ON(smp_processor_id() != boot_cpu_id);
0124
0125     ce->name     = "timer_ce";
0126     ce->rating   = 100;
0127     ce->features = CLOCK_EVT_FEAT_PERIODIC;
0128     ce->set_state_shutdown = timer_ce_shutdown;
0129     ce->set_state_periodic = timer_ce_set_periodic;
0130     ce->tick_resume = timer_ce_set_periodic;
0131     ce->cpumask  = cpu_possible_mask;
0132     ce->shift    = 32;
0133     ce->mult     = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
0134                           ce->shift);
0135     clockevents_register_device(ce);
0136 }
0137
0138 static unsigned int sbus_cycles_offset(void)
0139 {
0140     u32 val, offset;
0141
0142     val = sbus_readl(master_l10_counter);
0143     offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK;
0144
0145     /* Limit hit? */
0146     if (val & TIMER_LIMIT_BIT)
0147         offset += sparc_config.cs_period;
0148
0149     return offset;
0150 }
0151
0152 static u64 timer_cs_read(struct clocksource *cs)
0153 {
0154     unsigned int seq, offset;
0155     u64 cycles;
0156
0157     do {
0158         seq = read_seqbegin(&timer_cs_lock);
0159
0160         cycles = timer_cs_internal_counter;
0161         offset = sparc_config.get_cycles_offset();
0162     } while (read_seqretry(&timer_cs_lock, seq));
0163
0164     /* Count absolute cycles */
0165     cycles *= sparc_config.cs_period;
0166     cycles += offset;
0167
0168     return cycles;
0169 }
0170
0171 static struct clocksource timer_cs = {
0172     .name   = "timer_cs",
0173     .rating = 100,
0174     .read   = timer_cs_read,
0175     .mask   = CLOCKSOURCE_MASK(64),
0176     .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
0177 };
0178
0179 static __init int setup_timer_cs(void)
0180 {
0181     timer_cs_enabled = 1;
0182     return clocksource_register_hz(&timer_cs, sparc_config.clock_rate);
0183 }
0184
0185 #ifdef CONFIG_SMP
0186 static int percpu_ce_shutdown(struct clock_event_device *evt)
0187 {
0188     int cpu = cpumask_first(evt->cpumask);
0189
0190     sparc_config.load_profile_irq(cpu, 0);
0191     return 0;
0192 }
0193
0194 static int percpu_ce_set_periodic(struct clock_event_device *evt)
0195 {
0196     int cpu = cpumask_first(evt->cpumask);
0197
0198     sparc_config.load_profile_irq(cpu, SBUS_CLOCK_RATE / HZ);
0199     return 0;
0200 }
0201
0202 static int percpu_ce_set_next_event(unsigned long delta,
0203                     struct clock_event_device *evt)
0204 {
0205     int cpu = cpumask_first(evt->cpumask);
0206     unsigned int next = (unsigned int)delta;
0207
0208     sparc_config.load_profile_irq(cpu, next);
0209     return 0;
0210 }
0211
0212 void register_percpu_ce(int cpu)
0213 {
0214     struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu);
0215     unsigned int features = CLOCK_EVT_FEAT_PERIODIC;
0216
0217     if (sparc_config.features & FEAT_L14_ONESHOT)
0218         features |= CLOCK_EVT_FEAT_ONESHOT;
0219
0220     ce->name           = "percpu_ce";
0221     ce->rating         = 200;
0222     ce->features       = features;
0223     ce->set_state_shutdown = percpu_ce_shutdown;
0224     ce->set_state_periodic = percpu_ce_set_periodic;
0225     ce->set_state_oneshot = percpu_ce_shutdown;
0226     ce->set_next_event = percpu_ce_set_next_event;
0227     ce->cpumask        = cpumask_of(cpu);
0228     ce->shift          = 32;
0229     ce->mult           = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
0230                                 ce->shift);
0231     ce->max_delta_ns   = clockevent_delta2ns(sparc_config.clock_rate, ce);
0232     ce->max_delta_ticks = (unsigned long)sparc_config.clock_rate;
0233     ce->min_delta_ns   = clockevent_delta2ns(100, ce);
0234     ce->min_delta_ticks = 100;
0235
0236     clockevents_register_device(ce);
0237 }
0238 #endif
0239
0240 static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
0241 {
0242     struct platform_device *pdev = to_platform_device(dev);
0243     struct m48t59_plat_data *pdata = pdev->dev.platform_data;
0244
0245     return readb(pdata->ioaddr + ofs);
0246 }
0247
0248 static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
0249 {
0250     struct platform_device *pdev = to_platform_device(dev);
0251     struct m48t59_plat_data *pdata = pdev->dev.platform_data;
0252
0253     writeb(val, pdata->ioaddr + ofs);
0254 }
0255
0256 static struct m48t59_plat_data m48t59_data = {
0257     .read_byte = mostek_read_byte,
0258     .write_byte = mostek_write_byte,
0259 };
0260
0261 /* resource is set at runtime */
0262 static struct platform_device m48t59_rtc = {
0263     .name       = "rtc-m48t59",
0264     .id     = 0,
0265     .num_resources  = 1,
0266     .dev    = {
0267         .platform_data = &m48t59_data,
0268     },
0269 };
0270
0271 static int clock_probe(struct platform_device *op)
0272 {
0273     struct device_node *dp = op->dev.of_node;
0274     const char *model = of_get_property(dp, "model", NULL);
0275
0276     if (!model)
0277         return -ENODEV;
0278
0279     /* Only the primary RTC has an address property */
0280     if (!of_find_property(dp, "address", NULL))
0281         return -ENODEV;
0282
0283     m48t59_rtc.resource = &op->resource[0];
0284     if (!strcmp(model, "mk48t02")) {
0285         /* Map the clock register io area read-only */
0286         m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
0287                         2048, "rtc-m48t59");
0288         m48t59_data.type = M48T59RTC_TYPE_M48T02;
0289     } else if (!strcmp(model, "mk48t08")) {
0290         m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
0291                         8192, "rtc-m48t59");
0292         m48t59_data.type = M48T59RTC_TYPE_M48T08;
0293     } else
0294         return -ENODEV;
0295
0296     if (platform_device_register(&m48t59_rtc) < 0)
0297         printk(KERN_ERR "Registering RTC device failed\n");
0298
0299     return 0;
0300 }
0301
0302 static const struct of_device_id clock_match[] = {
0303     {
0304         .name = "eeprom",
0305     },
0306     {},
0307 };
0308
0309 static struct platform_driver clock_driver = {
0310     .probe      = clock_probe,
0311     .driver = {
0312         .name = "rtc",
0313         .of_match_table = clock_match,
0314     },
0315 };
0316
0317
0318 /* Probe for the mostek real time clock chip. */
0319 static int __init clock_init(void)
0320 {
0321     return platform_driver_register(&clock_driver);
0322 }
0323 /* Must be after subsys_initcall() so that busses are probed.  Must
0324  * be before device_initcall() because things like the RTC driver
0325  * need to see the clock registers.
0326  */
0327 fs_initcall(clock_init);
0328
0329 static void __init sparc32_late_time_init(void)
0330 {
0331     if (sparc_config.features & FEAT_L10_CLOCKEVENT)
0332         setup_timer_ce();
0333     if (sparc_config.features & FEAT_L10_CLOCKSOURCE)
0334         setup_timer_cs();
0335 #ifdef CONFIG_SMP
0336     register_percpu_ce(smp_processor_id());
0337 #endif
0338 }
0339
0340 static void __init sbus_time_init(void)
0341 {
0342     sparc_config.get_cycles_offset = sbus_cycles_offset;
0343     sparc_config.init_timers();
0344 }
0345
0346 void __init time_init(void)
0347 {
0348     sparc_config.features = 0;
0349     late_time_init = sparc32_late_time_init;
0350
0351     if (pcic_present())
0352         pci_time_init();
0353     else
0354         sbus_time_init();
0355 }
0356