sparc/kernel/sysfs.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* sysfs.c: Topology sysfs support code for sparc64.
0003  *
0004  * Copyright (C) 2007 David S. Miller <davem@davemloft.net>
0005  */
0006 #include <linux/sched.h>
0007 #include <linux/device.h>
0008 #include <linux/cpu.h>
0009 #include <linux/smp.h>
0010 #include <linux/percpu.h>
0011 #include <linux/init.h>
0012
0013 #include <asm/cpudata.h>
0014 #include <asm/hypervisor.h>
0015 #include <asm/spitfire.h>
0016
0017 static DEFINE_PER_CPU(struct hv_mmu_statistics, mmu_stats) __attribute__((aligned(64)));
0018
0019 #define SHOW_MMUSTAT_ULONG(NAME) \
0020 static ssize_t show_##NAME(struct device *dev, \
0021             struct device_attribute *attr, char *buf) \
0022 { \
0023     struct hv_mmu_statistics *p = &per_cpu(mmu_stats, dev->id); \
0024     return sprintf(buf, "%lu\n", p->NAME); \
0025 } \
0026 static DEVICE_ATTR(NAME, 0444, show_##NAME, NULL)
0027
0028 SHOW_MMUSTAT_ULONG(immu_tsb_hits_ctx0_8k_tte);
0029 SHOW_MMUSTAT_ULONG(immu_tsb_ticks_ctx0_8k_tte);
0030 SHOW_MMUSTAT_ULONG(immu_tsb_hits_ctx0_64k_tte);
0031 SHOW_MMUSTAT_ULONG(immu_tsb_ticks_ctx0_64k_tte);
0032 SHOW_MMUSTAT_ULONG(immu_tsb_hits_ctx0_4mb_tte);
0033 SHOW_MMUSTAT_ULONG(immu_tsb_ticks_ctx0_4mb_tte);
0034 SHOW_MMUSTAT_ULONG(immu_tsb_hits_ctx0_256mb_tte);
0035 SHOW_MMUSTAT_ULONG(immu_tsb_ticks_ctx0_256mb_tte);
0036 SHOW_MMUSTAT_ULONG(immu_tsb_hits_ctxnon0_8k_tte);
0037 SHOW_MMUSTAT_ULONG(immu_tsb_ticks_ctxnon0_8k_tte);
0038 SHOW_MMUSTAT_ULONG(immu_tsb_hits_ctxnon0_64k_tte);
0039 SHOW_MMUSTAT_ULONG(immu_tsb_ticks_ctxnon0_64k_tte);
0040 SHOW_MMUSTAT_ULONG(immu_tsb_hits_ctxnon0_4mb_tte);
0041 SHOW_MMUSTAT_ULONG(immu_tsb_ticks_ctxnon0_4mb_tte);
0042 SHOW_MMUSTAT_ULONG(immu_tsb_hits_ctxnon0_256mb_tte);
0043 SHOW_MMUSTAT_ULONG(immu_tsb_ticks_ctxnon0_256mb_tte);
0044 SHOW_MMUSTAT_ULONG(dmmu_tsb_hits_ctx0_8k_tte);
0045 SHOW_MMUSTAT_ULONG(dmmu_tsb_ticks_ctx0_8k_tte);
0046 SHOW_MMUSTAT_ULONG(dmmu_tsb_hits_ctx0_64k_tte);
0047 SHOW_MMUSTAT_ULONG(dmmu_tsb_ticks_ctx0_64k_tte);
0048 SHOW_MMUSTAT_ULONG(dmmu_tsb_hits_ctx0_4mb_tte);
0049 SHOW_MMUSTAT_ULONG(dmmu_tsb_ticks_ctx0_4mb_tte);
0050 SHOW_MMUSTAT_ULONG(dmmu_tsb_hits_ctx0_256mb_tte);
0051 SHOW_MMUSTAT_ULONG(dmmu_tsb_ticks_ctx0_256mb_tte);
0052 SHOW_MMUSTAT_ULONG(dmmu_tsb_hits_ctxnon0_8k_tte);
0053 SHOW_MMUSTAT_ULONG(dmmu_tsb_ticks_ctxnon0_8k_tte);
0054 SHOW_MMUSTAT_ULONG(dmmu_tsb_hits_ctxnon0_64k_tte);
0055 SHOW_MMUSTAT_ULONG(dmmu_tsb_ticks_ctxnon0_64k_tte);
0056 SHOW_MMUSTAT_ULONG(dmmu_tsb_hits_ctxnon0_4mb_tte);
0057 SHOW_MMUSTAT_ULONG(dmmu_tsb_ticks_ctxnon0_4mb_tte);
0058 SHOW_MMUSTAT_ULONG(dmmu_tsb_hits_ctxnon0_256mb_tte);
0059 SHOW_MMUSTAT_ULONG(dmmu_tsb_ticks_ctxnon0_256mb_tte);
0060
0061 static struct attribute *mmu_stat_attrs[] = {
0062     &dev_attr_immu_tsb_hits_ctx0_8k_tte.attr,
0063     &dev_attr_immu_tsb_ticks_ctx0_8k_tte.attr,
0064     &dev_attr_immu_tsb_hits_ctx0_64k_tte.attr,
0065     &dev_attr_immu_tsb_ticks_ctx0_64k_tte.attr,
0066     &dev_attr_immu_tsb_hits_ctx0_4mb_tte.attr,
0067     &dev_attr_immu_tsb_ticks_ctx0_4mb_tte.attr,
0068     &dev_attr_immu_tsb_hits_ctx0_256mb_tte.attr,
0069     &dev_attr_immu_tsb_ticks_ctx0_256mb_tte.attr,
0070     &dev_attr_immu_tsb_hits_ctxnon0_8k_tte.attr,
0071     &dev_attr_immu_tsb_ticks_ctxnon0_8k_tte.attr,
0072     &dev_attr_immu_tsb_hits_ctxnon0_64k_tte.attr,
0073     &dev_attr_immu_tsb_ticks_ctxnon0_64k_tte.attr,
0074     &dev_attr_immu_tsb_hits_ctxnon0_4mb_tte.attr,
0075     &dev_attr_immu_tsb_ticks_ctxnon0_4mb_tte.attr,
0076     &dev_attr_immu_tsb_hits_ctxnon0_256mb_tte.attr,
0077     &dev_attr_immu_tsb_ticks_ctxnon0_256mb_tte.attr,
0078     &dev_attr_dmmu_tsb_hits_ctx0_8k_tte.attr,
0079     &dev_attr_dmmu_tsb_ticks_ctx0_8k_tte.attr,
0080     &dev_attr_dmmu_tsb_hits_ctx0_64k_tte.attr,
0081     &dev_attr_dmmu_tsb_ticks_ctx0_64k_tte.attr,
0082     &dev_attr_dmmu_tsb_hits_ctx0_4mb_tte.attr,
0083     &dev_attr_dmmu_tsb_ticks_ctx0_4mb_tte.attr,
0084     &dev_attr_dmmu_tsb_hits_ctx0_256mb_tte.attr,
0085     &dev_attr_dmmu_tsb_ticks_ctx0_256mb_tte.attr,
0086     &dev_attr_dmmu_tsb_hits_ctxnon0_8k_tte.attr,
0087     &dev_attr_dmmu_tsb_ticks_ctxnon0_8k_tte.attr,
0088     &dev_attr_dmmu_tsb_hits_ctxnon0_64k_tte.attr,
0089     &dev_attr_dmmu_tsb_ticks_ctxnon0_64k_tte.attr,
0090     &dev_attr_dmmu_tsb_hits_ctxnon0_4mb_tte.attr,
0091     &dev_attr_dmmu_tsb_ticks_ctxnon0_4mb_tte.attr,
0092     &dev_attr_dmmu_tsb_hits_ctxnon0_256mb_tte.attr,
0093     &dev_attr_dmmu_tsb_ticks_ctxnon0_256mb_tte.attr,
0094     NULL,
0095 };
0096
0097 static struct attribute_group mmu_stat_group = {
0098     .attrs = mmu_stat_attrs,
0099     .name = "mmu_stats",
0100 };
0101
0102 static long read_mmustat_enable(void *data __maybe_unused)
0103 {
0104     unsigned long ra = 0;
0105
0106     sun4v_mmustat_info(&ra);
0107
0108     return ra != 0;
0109 }
0110
0111 static long write_mmustat_enable(void *data)
0112 {
0113     unsigned long ra, orig_ra, *val = data;
0114
0115     if (*val)
0116         ra = __pa(&per_cpu(mmu_stats, smp_processor_id()));
0117     else
0118         ra = 0UL;
0119
0120     return sun4v_mmustat_conf(ra, &orig_ra);
0121 }
0122
0123 static ssize_t show_mmustat_enable(struct device *s,
0124                 struct device_attribute *attr, char *buf)
0125 {
0126     long val = work_on_cpu(s->id, read_mmustat_enable, NULL);
0127
0128     return sprintf(buf, "%lx\n", val);
0129 }
0130
0131 static ssize_t store_mmustat_enable(struct device *s,
0132             struct device_attribute *attr, const char *buf,
0133             size_t count)
0134 {
0135     unsigned long val;
0136     long err;
0137     int ret;
0138
0139     ret = sscanf(buf, "%lu", &val);
0140     if (ret != 1)
0141         return -EINVAL;
0142
0143     err = work_on_cpu(s->id, write_mmustat_enable, &val);
0144     if (err)
0145         return -EIO;
0146
0147     return count;
0148 }
0149
0150 static DEVICE_ATTR(mmustat_enable, 0644, show_mmustat_enable, store_mmustat_enable);
0151
0152 static int mmu_stats_supported;
0153
0154 static int register_mmu_stats(struct device *s)
0155 {
0156     if (!mmu_stats_supported)
0157         return 0;
0158     device_create_file(s, &dev_attr_mmustat_enable);
0159     return sysfs_create_group(&s->kobj, &mmu_stat_group);
0160 }
0161
0162 #ifdef CONFIG_HOTPLUG_CPU
0163 static void unregister_mmu_stats(struct device *s)
0164 {
0165     if (!mmu_stats_supported)
0166         return;
0167     sysfs_remove_group(&s->kobj, &mmu_stat_group);
0168     device_remove_file(s, &dev_attr_mmustat_enable);
0169 }
0170 #endif
0171
0172 #define SHOW_CPUDATA_ULONG_NAME(NAME, MEMBER) \
0173 static ssize_t show_##NAME(struct device *dev, \
0174         struct device_attribute *attr, char *buf) \
0175 { \
0176     cpuinfo_sparc *c = &cpu_data(dev->id); \
0177     return sprintf(buf, "%lu\n", c->MEMBER); \
0178 }
0179
0180 #define SHOW_CPUDATA_UINT_NAME(NAME, MEMBER) \
0181 static ssize_t show_##NAME(struct device *dev, \
0182         struct device_attribute *attr, char *buf) \
0183 { \
0184     cpuinfo_sparc *c = &cpu_data(dev->id); \
0185     return sprintf(buf, "%u\n", c->MEMBER); \
0186 }
0187
0188 SHOW_CPUDATA_ULONG_NAME(clock_tick, clock_tick);
0189 SHOW_CPUDATA_UINT_NAME(l1_dcache_size, dcache_size);
0190 SHOW_CPUDATA_UINT_NAME(l1_dcache_line_size, dcache_line_size);
0191 SHOW_CPUDATA_UINT_NAME(l1_icache_size, icache_size);
0192 SHOW_CPUDATA_UINT_NAME(l1_icache_line_size, icache_line_size);
0193 SHOW_CPUDATA_UINT_NAME(l2_cache_size, ecache_size);
0194 SHOW_CPUDATA_UINT_NAME(l2_cache_line_size, ecache_line_size);
0195
0196 static struct device_attribute cpu_core_attrs[] = {
0197     __ATTR(clock_tick,          0444, show_clock_tick, NULL),
0198     __ATTR(l1_dcache_size,      0444, show_l1_dcache_size, NULL),
0199     __ATTR(l1_dcache_line_size, 0444, show_l1_dcache_line_size, NULL),
0200     __ATTR(l1_icache_size,      0444, show_l1_icache_size, NULL),
0201     __ATTR(l1_icache_line_size, 0444, show_l1_icache_line_size, NULL),
0202     __ATTR(l2_cache_size,       0444, show_l2_cache_size, NULL),
0203     __ATTR(l2_cache_line_size,  0444, show_l2_cache_line_size, NULL),
0204 };
0205
0206 static DEFINE_PER_CPU(struct cpu, cpu_devices);
0207
0208 static int register_cpu_online(unsigned int cpu)
0209 {
0210     struct cpu *c = &per_cpu(cpu_devices, cpu);
0211     struct device *s = &c->dev;
0212     int i;
0213
0214     for (i = 0; i < ARRAY_SIZE(cpu_core_attrs); i++)
0215         device_create_file(s, &cpu_core_attrs[i]);
0216
0217     register_mmu_stats(s);
0218     return 0;
0219 }
0220
0221 static int unregister_cpu_online(unsigned int cpu)
0222 {
0223 #ifdef CONFIG_HOTPLUG_CPU
0224     struct cpu *c = &per_cpu(cpu_devices, cpu);
0225     struct device *s = &c->dev;
0226     int i;
0227
0228     unregister_mmu_stats(s);
0229     for (i = 0; i < ARRAY_SIZE(cpu_core_attrs); i++)
0230         device_remove_file(s, &cpu_core_attrs[i]);
0231 #endif
0232     return 0;
0233 }
0234
0235 static void __init check_mmu_stats(void)
0236 {
0237     unsigned long dummy1, err;
0238
0239     if (tlb_type != hypervisor)
0240         return;
0241
0242     err = sun4v_mmustat_info(&dummy1);
0243     if (!err)
0244         mmu_stats_supported = 1;
0245 }
0246
0247 static int __init topology_init(void)
0248 {
0249     int cpu, ret;
0250
0251     check_mmu_stats();
0252
0253     for_each_possible_cpu(cpu) {
0254         struct cpu *c = &per_cpu(cpu_devices, cpu);
0255
0256         register_cpu(c, cpu);
0257     }
0258
0259     ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "sparc/topology:online",
0260                 register_cpu_online, unregister_cpu_online);
0261     WARN_ON(ret < 0);
0262     return 0;
0263 }
0264
0265 subsys_initcall(topology_init);