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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  linux/arch/sparc64/kernel/setup.c
0004  *
0005  *  Copyright (C) 1995,1996  David S. Miller (davem@caip.rutgers.edu)
0006  *  Copyright (C) 1997       Jakub Jelinek (jj@sunsite.mff.cuni.cz)
0007  */
0008 
0009 #include <linux/errno.h>
0010 #include <linux/sched.h>
0011 #include <linux/kernel.h>
0012 #include <linux/mm.h>
0013 #include <linux/stddef.h>
0014 #include <linux/unistd.h>
0015 #include <linux/ptrace.h>
0016 #include <asm/smp.h>
0017 #include <linux/user.h>
0018 #include <linux/screen_info.h>
0019 #include <linux/delay.h>
0020 #include <linux/fs.h>
0021 #include <linux/seq_file.h>
0022 #include <linux/syscalls.h>
0023 #include <linux/kdev_t.h>
0024 #include <linux/major.h>
0025 #include <linux/string.h>
0026 #include <linux/init.h>
0027 #include <linux/inet.h>
0028 #include <linux/console.h>
0029 #include <linux/root_dev.h>
0030 #include <linux/interrupt.h>
0031 #include <linux/cpu.h>
0032 #include <linux/initrd.h>
0033 #include <linux/module.h>
0034 #include <linux/start_kernel.h>
0035 #include <linux/memblock.h>
0036 #include <uapi/linux/mount.h>
0037 
0038 #include <asm/io.h>
0039 #include <asm/processor.h>
0040 #include <asm/oplib.h>
0041 #include <asm/page.h>
0042 #include <asm/idprom.h>
0043 #include <asm/head.h>
0044 #include <asm/starfire.h>
0045 #include <asm/mmu_context.h>
0046 #include <asm/timer.h>
0047 #include <asm/sections.h>
0048 #include <asm/setup.h>
0049 #include <asm/mmu.h>
0050 #include <asm/ns87303.h>
0051 #include <asm/btext.h>
0052 #include <asm/elf.h>
0053 #include <asm/mdesc.h>
0054 #include <asm/cacheflush.h>
0055 #include <asm/dma.h>
0056 #include <asm/irq.h>
0057 
0058 #ifdef CONFIG_IP_PNP
0059 #include <net/ipconfig.h>
0060 #endif
0061 
0062 #include "entry.h"
0063 #include "kernel.h"
0064 
0065 /* Used to synchronize accesses to NatSemi SUPER I/O chip configure
0066  * operations in asm/ns87303.h
0067  */
0068 DEFINE_SPINLOCK(ns87303_lock);
0069 EXPORT_SYMBOL(ns87303_lock);
0070 
0071 struct screen_info screen_info = {
0072     0, 0,           /* orig-x, orig-y */
0073     0,          /* unused */
0074     0,          /* orig-video-page */
0075     0,          /* orig-video-mode */
0076     128,            /* orig-video-cols */
0077     0, 0, 0,        /* unused, ega_bx, unused */
0078     54,         /* orig-video-lines */
0079     0,                      /* orig-video-isVGA */
0080     16                      /* orig-video-points */
0081 };
0082 
0083 static void
0084 prom_console_write(struct console *con, const char *s, unsigned int n)
0085 {
0086     prom_write(s, n);
0087 }
0088 
0089 /* Exported for mm/init.c:paging_init. */
0090 unsigned long cmdline_memory_size = 0;
0091 
0092 static struct console prom_early_console = {
0093     .name =     "earlyprom",
0094     .write =    prom_console_write,
0095     .flags =    CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME,
0096     .index =    -1,
0097 };
0098 
0099 /*
0100  * Process kernel command line switches that are specific to the
0101  * SPARC or that require special low-level processing.
0102  */
0103 static void __init process_switch(char c)
0104 {
0105     switch (c) {
0106     case 'd':
0107     case 's':
0108         break;
0109     case 'h':
0110         prom_printf("boot_flags_init: Halt!\n");
0111         prom_halt();
0112         break;
0113     case 'p':
0114         prom_early_console.flags &= ~CON_BOOT;
0115         break;
0116     case 'P':
0117         /* Force UltraSPARC-III P-Cache on. */
0118         if (tlb_type != cheetah) {
0119             printk("BOOT: Ignoring P-Cache force option.\n");
0120             break;
0121         }
0122         cheetah_pcache_forced_on = 1;
0123         add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
0124         cheetah_enable_pcache();
0125         break;
0126 
0127     default:
0128         printk("Unknown boot switch (-%c)\n", c);
0129         break;
0130     }
0131 }
0132 
0133 static void __init boot_flags_init(char *commands)
0134 {
0135     while (*commands) {
0136         /* Move to the start of the next "argument". */
0137         while (*commands == ' ')
0138             commands++;
0139 
0140         /* Process any command switches, otherwise skip it. */
0141         if (*commands == '\0')
0142             break;
0143         if (*commands == '-') {
0144             commands++;
0145             while (*commands && *commands != ' ')
0146                 process_switch(*commands++);
0147             continue;
0148         }
0149         if (!strncmp(commands, "mem=", 4))
0150             cmdline_memory_size = memparse(commands + 4, &commands);
0151 
0152         while (*commands && *commands != ' ')
0153             commands++;
0154     }
0155 }
0156 
0157 extern unsigned short root_flags;
0158 extern unsigned short root_dev;
0159 extern unsigned short ram_flags;
0160 #define RAMDISK_IMAGE_START_MASK    0x07FF
0161 #define RAMDISK_PROMPT_FLAG     0x8000
0162 #define RAMDISK_LOAD_FLAG       0x4000
0163 
0164 extern int root_mountflags;
0165 
0166 char reboot_command[COMMAND_LINE_SIZE];
0167 
0168 static void __init per_cpu_patch(void)
0169 {
0170     struct cpuid_patch_entry *p;
0171     unsigned long ver;
0172     int is_jbus;
0173 
0174     if (tlb_type == spitfire && !this_is_starfire)
0175         return;
0176 
0177     is_jbus = 0;
0178     if (tlb_type != hypervisor) {
0179         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
0180         is_jbus = ((ver >> 32UL) == __JALAPENO_ID ||
0181                (ver >> 32UL) == __SERRANO_ID);
0182     }
0183 
0184     p = &__cpuid_patch;
0185     while (p < &__cpuid_patch_end) {
0186         unsigned long addr = p->addr;
0187         unsigned int *insns;
0188 
0189         switch (tlb_type) {
0190         case spitfire:
0191             insns = &p->starfire[0];
0192             break;
0193         case cheetah:
0194         case cheetah_plus:
0195             if (is_jbus)
0196                 insns = &p->cheetah_jbus[0];
0197             else
0198                 insns = &p->cheetah_safari[0];
0199             break;
0200         case hypervisor:
0201             insns = &p->sun4v[0];
0202             break;
0203         default:
0204             prom_printf("Unknown cpu type, halting.\n");
0205             prom_halt();
0206         }
0207 
0208         *(unsigned int *) (addr +  0) = insns[0];
0209         wmb();
0210         __asm__ __volatile__("flush %0" : : "r" (addr +  0));
0211 
0212         *(unsigned int *) (addr +  4) = insns[1];
0213         wmb();
0214         __asm__ __volatile__("flush %0" : : "r" (addr +  4));
0215 
0216         *(unsigned int *) (addr +  8) = insns[2];
0217         wmb();
0218         __asm__ __volatile__("flush %0" : : "r" (addr +  8));
0219 
0220         *(unsigned int *) (addr + 12) = insns[3];
0221         wmb();
0222         __asm__ __volatile__("flush %0" : : "r" (addr + 12));
0223 
0224         p++;
0225     }
0226 }
0227 
0228 void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
0229                  struct sun4v_1insn_patch_entry *end)
0230 {
0231     while (start < end) {
0232         unsigned long addr = start->addr;
0233 
0234         *(unsigned int *) (addr +  0) = start->insn;
0235         wmb();
0236         __asm__ __volatile__("flush %0" : : "r" (addr +  0));
0237 
0238         start++;
0239     }
0240 }
0241 
0242 void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
0243                  struct sun4v_2insn_patch_entry *end)
0244 {
0245     while (start < end) {
0246         unsigned long addr = start->addr;
0247 
0248         *(unsigned int *) (addr +  0) = start->insns[0];
0249         wmb();
0250         __asm__ __volatile__("flush %0" : : "r" (addr +  0));
0251 
0252         *(unsigned int *) (addr +  4) = start->insns[1];
0253         wmb();
0254         __asm__ __volatile__("flush %0" : : "r" (addr +  4));
0255 
0256         start++;
0257     }
0258 }
0259 
0260 void sun_m7_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
0261                  struct sun4v_2insn_patch_entry *end)
0262 {
0263     while (start < end) {
0264         unsigned long addr = start->addr;
0265 
0266         *(unsigned int *) (addr +  0) = start->insns[0];
0267         wmb();
0268         __asm__ __volatile__("flush %0" : : "r" (addr +  0));
0269 
0270         *(unsigned int *) (addr +  4) = start->insns[1];
0271         wmb();
0272         __asm__ __volatile__("flush %0" : : "r" (addr +  4));
0273 
0274         start++;
0275     }
0276 }
0277 
0278 static void __init sun4v_patch(void)
0279 {
0280     extern void sun4v_hvapi_init(void);
0281 
0282     if (tlb_type != hypervisor)
0283         return;
0284 
0285     sun4v_patch_1insn_range(&__sun4v_1insn_patch,
0286                 &__sun4v_1insn_patch_end);
0287 
0288     sun4v_patch_2insn_range(&__sun4v_2insn_patch,
0289                 &__sun4v_2insn_patch_end);
0290 
0291     switch (sun4v_chip_type) {
0292     case SUN4V_CHIP_SPARC_M7:
0293     case SUN4V_CHIP_SPARC_M8:
0294     case SUN4V_CHIP_SPARC_SN:
0295         sun4v_patch_1insn_range(&__sun_m7_1insn_patch,
0296                     &__sun_m7_1insn_patch_end);
0297         sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,
0298                      &__sun_m7_2insn_patch_end);
0299         break;
0300     default:
0301         break;
0302     }
0303 
0304     if (sun4v_chip_type != SUN4V_CHIP_NIAGARA1) {
0305         sun4v_patch_1insn_range(&__fast_win_ctrl_1insn_patch,
0306                     &__fast_win_ctrl_1insn_patch_end);
0307     }
0308 
0309     sun4v_hvapi_init();
0310 }
0311 
0312 static void __init popc_patch(void)
0313 {
0314     struct popc_3insn_patch_entry *p3;
0315     struct popc_6insn_patch_entry *p6;
0316 
0317     p3 = &__popc_3insn_patch;
0318     while (p3 < &__popc_3insn_patch_end) {
0319         unsigned long i, addr = p3->addr;
0320 
0321         for (i = 0; i < 3; i++) {
0322             *(unsigned int *) (addr +  (i * 4)) = p3->insns[i];
0323             wmb();
0324             __asm__ __volatile__("flush %0"
0325                          : : "r" (addr +  (i * 4)));
0326         }
0327 
0328         p3++;
0329     }
0330 
0331     p6 = &__popc_6insn_patch;
0332     while (p6 < &__popc_6insn_patch_end) {
0333         unsigned long i, addr = p6->addr;
0334 
0335         for (i = 0; i < 6; i++) {
0336             *(unsigned int *) (addr +  (i * 4)) = p6->insns[i];
0337             wmb();
0338             __asm__ __volatile__("flush %0"
0339                          : : "r" (addr +  (i * 4)));
0340         }
0341 
0342         p6++;
0343     }
0344 }
0345 
0346 static void __init pause_patch(void)
0347 {
0348     struct pause_patch_entry *p;
0349 
0350     p = &__pause_3insn_patch;
0351     while (p < &__pause_3insn_patch_end) {
0352         unsigned long i, addr = p->addr;
0353 
0354         for (i = 0; i < 3; i++) {
0355             *(unsigned int *) (addr +  (i * 4)) = p->insns[i];
0356             wmb();
0357             __asm__ __volatile__("flush %0"
0358                          : : "r" (addr +  (i * 4)));
0359         }
0360 
0361         p++;
0362     }
0363 }
0364 
0365 void __init start_early_boot(void)
0366 {
0367     int cpu;
0368 
0369     check_if_starfire();
0370     per_cpu_patch();
0371     sun4v_patch();
0372     smp_init_cpu_poke();
0373 
0374     cpu = hard_smp_processor_id();
0375     if (cpu >= NR_CPUS) {
0376         prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
0377                 cpu, NR_CPUS);
0378         prom_halt();
0379     }
0380     current_thread_info()->cpu = cpu;
0381 
0382     time_init_early();
0383     prom_init_report();
0384     start_kernel();
0385 }
0386 
0387 /* On Ultra, we support all of the v8 capabilities. */
0388 unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
0389                    HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
0390                    HWCAP_SPARC_V9);
0391 EXPORT_SYMBOL(sparc64_elf_hwcap);
0392 
0393 static const char *hwcaps[] = {
0394     "flush", "stbar", "swap", "muldiv", "v9",
0395     "ultra3", "blkinit", "n2",
0396 
0397     /* These strings are as they appear in the machine description
0398      * 'hwcap-list' property for cpu nodes.
0399      */
0400     "mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
0401     "ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
0402     "ima", "cspare", "pause", "cbcond", NULL /*reserved for crypto */,
0403     "adp",
0404 };
0405 
0406 static const char *crypto_hwcaps[] = {
0407     "aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
0408     "sha512", "mpmul", "montmul", "montsqr", "crc32c",
0409 };
0410 
0411 void cpucap_info(struct seq_file *m)
0412 {
0413     unsigned long caps = sparc64_elf_hwcap;
0414     int i, printed = 0;
0415 
0416     seq_puts(m, "cpucaps\t\t: ");
0417     for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
0418         unsigned long bit = 1UL << i;
0419         if (hwcaps[i] && (caps & bit)) {
0420             seq_printf(m, "%s%s",
0421                    printed ? "," : "", hwcaps[i]);
0422             printed++;
0423         }
0424     }
0425     if (caps & HWCAP_SPARC_CRYPTO) {
0426         unsigned long cfr;
0427 
0428         __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
0429         for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
0430             unsigned long bit = 1UL << i;
0431             if (cfr & bit) {
0432                 seq_printf(m, "%s%s",
0433                        printed ? "," : "", crypto_hwcaps[i]);
0434                 printed++;
0435             }
0436         }
0437     }
0438     seq_putc(m, '\n');
0439 }
0440 
0441 static void __init report_one_hwcap(int *printed, const char *name)
0442 {
0443     if ((*printed) == 0)
0444         printk(KERN_INFO "CPU CAPS: [");
0445     printk(KERN_CONT "%s%s",
0446            (*printed) ? "," : "", name);
0447     if (++(*printed) == 8) {
0448         printk(KERN_CONT "]\n");
0449         *printed = 0;
0450     }
0451 }
0452 
0453 static void __init report_crypto_hwcaps(int *printed)
0454 {
0455     unsigned long cfr;
0456     int i;
0457 
0458     __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
0459 
0460     for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
0461         unsigned long bit = 1UL << i;
0462         if (cfr & bit)
0463             report_one_hwcap(printed, crypto_hwcaps[i]);
0464     }
0465 }
0466 
0467 static void __init report_hwcaps(unsigned long caps)
0468 {
0469     int i, printed = 0;
0470 
0471     for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
0472         unsigned long bit = 1UL << i;
0473         if (hwcaps[i] && (caps & bit))
0474             report_one_hwcap(&printed, hwcaps[i]);
0475     }
0476     if (caps & HWCAP_SPARC_CRYPTO)
0477         report_crypto_hwcaps(&printed);
0478     if (printed != 0)
0479         printk(KERN_CONT "]\n");
0480 }
0481 
0482 static unsigned long __init mdesc_cpu_hwcap_list(void)
0483 {
0484     struct mdesc_handle *hp;
0485     unsigned long caps = 0;
0486     const char *prop;
0487     int len;
0488     u64 pn;
0489 
0490     hp = mdesc_grab();
0491     if (!hp)
0492         return 0;
0493 
0494     pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
0495     if (pn == MDESC_NODE_NULL)
0496         goto out;
0497 
0498     prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
0499     if (!prop)
0500         goto out;
0501 
0502     while (len) {
0503         int i, plen;
0504 
0505         for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
0506             unsigned long bit = 1UL << i;
0507 
0508             if (hwcaps[i] && !strcmp(prop, hwcaps[i])) {
0509                 caps |= bit;
0510                 break;
0511             }
0512         }
0513         for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
0514             if (!strcmp(prop, crypto_hwcaps[i]))
0515                 caps |= HWCAP_SPARC_CRYPTO;
0516         }
0517 
0518         plen = strlen(prop) + 1;
0519         prop += plen;
0520         len -= plen;
0521     }
0522 
0523 out:
0524     mdesc_release(hp);
0525     return caps;
0526 }
0527 
0528 /* This yields a mask that user programs can use to figure out what
0529  * instruction set this cpu supports.
0530  */
0531 static void __init init_sparc64_elf_hwcap(void)
0532 {
0533     unsigned long cap = sparc64_elf_hwcap;
0534     unsigned long mdesc_caps;
0535 
0536     if (tlb_type == cheetah || tlb_type == cheetah_plus)
0537         cap |= HWCAP_SPARC_ULTRA3;
0538     else if (tlb_type == hypervisor) {
0539         if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
0540             sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
0541             sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
0542             sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
0543             sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
0544             sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
0545             sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
0546             sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
0547             sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
0548             sun4v_chip_type == SUN4V_CHIP_SPARC64X)
0549             cap |= HWCAP_SPARC_BLKINIT;
0550         if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
0551             sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
0552             sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
0553             sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
0554             sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
0555             sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
0556             sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
0557             sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
0558             sun4v_chip_type == SUN4V_CHIP_SPARC64X)
0559             cap |= HWCAP_SPARC_N2;
0560     }
0561 
0562     cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS);
0563 
0564     mdesc_caps = mdesc_cpu_hwcap_list();
0565     if (!mdesc_caps) {
0566         if (tlb_type == spitfire)
0567             cap |= AV_SPARC_VIS;
0568         if (tlb_type == cheetah || tlb_type == cheetah_plus)
0569             cap |= AV_SPARC_VIS | AV_SPARC_VIS2;
0570         if (tlb_type == cheetah_plus) {
0571             unsigned long impl, ver;
0572 
0573             __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
0574             impl = ((ver >> 32) & 0xffff);
0575             if (impl == PANTHER_IMPL)
0576                 cap |= AV_SPARC_POPC;
0577         }
0578         if (tlb_type == hypervisor) {
0579             if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
0580                 cap |= AV_SPARC_ASI_BLK_INIT;
0581             if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
0582                 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
0583                 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
0584                 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
0585                 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
0586                 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
0587                 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
0588                 sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
0589                 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
0590                 cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
0591                     AV_SPARC_ASI_BLK_INIT |
0592                     AV_SPARC_POPC);
0593             if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
0594                 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
0595                 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
0596                 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
0597                 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
0598                 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
0599                 sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
0600                 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
0601                 cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
0602                     AV_SPARC_FMAF);
0603         }
0604     }
0605     sparc64_elf_hwcap = cap | mdesc_caps;
0606 
0607     report_hwcaps(sparc64_elf_hwcap);
0608 
0609     if (sparc64_elf_hwcap & AV_SPARC_POPC)
0610         popc_patch();
0611     if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
0612         pause_patch();
0613 }
0614 
0615 void __init alloc_irqstack_bootmem(void)
0616 {
0617     unsigned int i, node;
0618 
0619     for_each_possible_cpu(i) {
0620         node = cpu_to_node(i);
0621 
0622         softirq_stack[i] = memblock_alloc_node(THREAD_SIZE,
0623                                THREAD_SIZE, node);
0624         if (!softirq_stack[i])
0625             panic("%s: Failed to allocate %lu bytes align=%lx nid=%d\n",
0626                   __func__, THREAD_SIZE, THREAD_SIZE, node);
0627         hardirq_stack[i] = memblock_alloc_node(THREAD_SIZE,
0628                                THREAD_SIZE, node);
0629         if (!hardirq_stack[i])
0630             panic("%s: Failed to allocate %lu bytes align=%lx nid=%d\n",
0631                   __func__, THREAD_SIZE, THREAD_SIZE, node);
0632     }
0633 }
0634 
0635 void __init setup_arch(char **cmdline_p)
0636 {
0637     /* Initialize PROM console and command line. */
0638     *cmdline_p = prom_getbootargs();
0639     strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
0640     parse_early_param();
0641 
0642     boot_flags_init(*cmdline_p);
0643 #ifdef CONFIG_EARLYFB
0644     if (btext_find_display())
0645 #endif
0646         register_console(&prom_early_console);
0647 
0648     if (tlb_type == hypervisor)
0649         pr_info("ARCH: SUN4V\n");
0650     else
0651         pr_info("ARCH: SUN4U\n");
0652 
0653     idprom_init();
0654 
0655     if (!root_flags)
0656         root_mountflags &= ~MS_RDONLY;
0657     ROOT_DEV = old_decode_dev(root_dev);
0658 #ifdef CONFIG_BLK_DEV_RAM
0659     rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
0660 #endif
0661 
0662 #ifdef CONFIG_IP_PNP
0663     if (!ic_set_manually) {
0664         phandle chosen = prom_finddevice("/chosen");
0665         u32 cl, sv, gw;
0666 
0667         cl = prom_getintdefault (chosen, "client-ip", 0);
0668         sv = prom_getintdefault (chosen, "server-ip", 0);
0669         gw = prom_getintdefault (chosen, "gateway-ip", 0);
0670         if (cl && sv) {
0671             ic_myaddr = cl;
0672             ic_servaddr = sv;
0673             if (gw)
0674                 ic_gateway = gw;
0675 #if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP)
0676             ic_proto_enabled = 0;
0677 #endif
0678         }
0679     }
0680 #endif
0681 
0682     /* Get boot processor trap_block[] setup.  */
0683     init_cur_cpu_trap(current_thread_info());
0684 
0685     paging_init();
0686     init_sparc64_elf_hwcap();
0687     smp_fill_in_cpu_possible_map();
0688     /*
0689      * Once the OF device tree and MDESC have been setup and nr_cpus has
0690      * been parsed, we know the list of possible cpus.  Therefore we can
0691      * allocate the IRQ stacks.
0692      */
0693     alloc_irqstack_bootmem();
0694 }
0695 
0696 extern int stop_a_enabled;
0697 
0698 void sun_do_break(void)
0699 {
0700     if (!stop_a_enabled)
0701         return;
0702 
0703     prom_printf("\n");
0704     flush_user_windows();
0705 
0706     prom_cmdline();
0707 }
0708 EXPORT_SYMBOL(sun_do_break);
0709 
0710 int stop_a_enabled = 1;
0711 EXPORT_SYMBOL(stop_a_enabled);
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