Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * sbus.c: UltraSparc SBUS controller support.
0004  *
0005  * Copyright (C) 1999 David S. Miller (davem@redhat.com)
0006  */
0007 
0008 #include <linux/kernel.h>
0009 #include <linux/types.h>
0010 #include <linux/mm.h>
0011 #include <linux/spinlock.h>
0012 #include <linux/slab.h>
0013 #include <linux/export.h>
0014 #include <linux/init.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/of.h>
0017 #include <linux/of_device.h>
0018 #include <linux/numa.h>
0019 
0020 #include <asm/page.h>
0021 #include <asm/io.h>
0022 #include <asm/upa.h>
0023 #include <asm/cache.h>
0024 #include <asm/dma.h>
0025 #include <asm/irq.h>
0026 #include <asm/prom.h>
0027 #include <asm/oplib.h>
0028 #include <asm/starfire.h>
0029 
0030 #include "iommu_common.h"
0031 
0032 #define MAP_BASE    ((u32)0xc0000000)
0033 
0034 /* Offsets from iommu_regs */
0035 #define SYSIO_IOMMUREG_BASE 0x2400UL
0036 #define IOMMU_CONTROL   (0x2400UL - 0x2400UL)   /* IOMMU control register */
0037 #define IOMMU_TSBBASE   (0x2408UL - 0x2400UL)   /* TSB base address register */
0038 #define IOMMU_FLUSH (0x2410UL - 0x2400UL)   /* IOMMU flush register */
0039 #define IOMMU_VADIAG    (0x4400UL - 0x2400UL)   /* SBUS virtual address diagnostic */
0040 #define IOMMU_TAGCMP    (0x4408UL - 0x2400UL)   /* TLB tag compare diagnostics */
0041 #define IOMMU_LRUDIAG   (0x4500UL - 0x2400UL)   /* IOMMU LRU queue diagnostics */
0042 #define IOMMU_TAGDIAG   (0x4580UL - 0x2400UL)   /* TLB tag diagnostics */
0043 #define IOMMU_DRAMDIAG  (0x4600UL - 0x2400UL)   /* TLB data RAM diagnostics */
0044 
0045 #define IOMMU_DRAM_VALID    (1UL << 30UL)
0046 
0047 /* Offsets from strbuf_regs */
0048 #define SYSIO_STRBUFREG_BASE    0x2800UL
0049 #define STRBUF_CONTROL  (0x2800UL - 0x2800UL)   /* Control */
0050 #define STRBUF_PFLUSH   (0x2808UL - 0x2800UL)   /* Page flush/invalidate */
0051 #define STRBUF_FSYNC    (0x2810UL - 0x2800UL)   /* Flush synchronization */
0052 #define STRBUF_DRAMDIAG (0x5000UL - 0x2800UL)   /* data RAM diagnostic */
0053 #define STRBUF_ERRDIAG  (0x5400UL - 0x2800UL)   /* error status diagnostics */
0054 #define STRBUF_PTAGDIAG (0x5800UL - 0x2800UL)   /* Page tag diagnostics */
0055 #define STRBUF_LTAGDIAG (0x5900UL - 0x2800UL)   /* Line tag diagnostics */
0056 
0057 #define STRBUF_TAG_VALID    0x02UL
0058 
0059 /* Enable 64-bit DVMA mode for the given device. */
0060 void sbus_set_sbus64(struct device *dev, int bursts)
0061 {
0062     struct iommu *iommu = dev->archdata.iommu;
0063     struct platform_device *op = to_platform_device(dev);
0064     const struct linux_prom_registers *regs;
0065     unsigned long cfg_reg;
0066     int slot;
0067     u64 val;
0068 
0069     regs = of_get_property(op->dev.of_node, "reg", NULL);
0070     if (!regs) {
0071         printk(KERN_ERR "sbus_set_sbus64: Cannot find regs for %pOF\n",
0072                op->dev.of_node);
0073         return;
0074     }
0075     slot = regs->which_io;
0076 
0077     cfg_reg = iommu->write_complete_reg;
0078     switch (slot) {
0079     case 0:
0080         cfg_reg += 0x20UL;
0081         break;
0082     case 1:
0083         cfg_reg += 0x28UL;
0084         break;
0085     case 2:
0086         cfg_reg += 0x30UL;
0087         break;
0088     case 3:
0089         cfg_reg += 0x38UL;
0090         break;
0091     case 13:
0092         cfg_reg += 0x40UL;
0093         break;
0094     case 14:
0095         cfg_reg += 0x48UL;
0096         break;
0097     case 15:
0098         cfg_reg += 0x50UL;
0099         break;
0100 
0101     default:
0102         return;
0103     }
0104 
0105     val = upa_readq(cfg_reg);
0106     if (val & (1UL << 14UL)) {
0107         /* Extended transfer mode already enabled. */
0108         return;
0109     }
0110 
0111     val |= (1UL << 14UL);
0112 
0113     if (bursts & DMA_BURST8)
0114         val |= (1UL << 1UL);
0115     if (bursts & DMA_BURST16)
0116         val |= (1UL << 2UL);
0117     if (bursts & DMA_BURST32)
0118         val |= (1UL << 3UL);
0119     if (bursts & DMA_BURST64)
0120         val |= (1UL << 4UL);
0121     upa_writeq(val, cfg_reg);
0122 }
0123 EXPORT_SYMBOL(sbus_set_sbus64);
0124 
0125 /* INO number to IMAP register offset for SYSIO external IRQ's.
0126  * This should conform to both Sunfire/Wildfire server and Fusion
0127  * desktop designs.
0128  */
0129 #define SYSIO_IMAP_SLOT0    0x2c00UL
0130 #define SYSIO_IMAP_SLOT1    0x2c08UL
0131 #define SYSIO_IMAP_SLOT2    0x2c10UL
0132 #define SYSIO_IMAP_SLOT3    0x2c18UL
0133 #define SYSIO_IMAP_SCSI     0x3000UL
0134 #define SYSIO_IMAP_ETH      0x3008UL
0135 #define SYSIO_IMAP_BPP      0x3010UL
0136 #define SYSIO_IMAP_AUDIO    0x3018UL
0137 #define SYSIO_IMAP_PFAIL    0x3020UL
0138 #define SYSIO_IMAP_KMS      0x3028UL
0139 #define SYSIO_IMAP_FLPY     0x3030UL
0140 #define SYSIO_IMAP_SHW      0x3038UL
0141 #define SYSIO_IMAP_KBD      0x3040UL
0142 #define SYSIO_IMAP_MS       0x3048UL
0143 #define SYSIO_IMAP_SER      0x3050UL
0144 #define SYSIO_IMAP_TIM0     0x3060UL
0145 #define SYSIO_IMAP_TIM1     0x3068UL
0146 #define SYSIO_IMAP_UE       0x3070UL
0147 #define SYSIO_IMAP_CE       0x3078UL
0148 #define SYSIO_IMAP_SBERR    0x3080UL
0149 #define SYSIO_IMAP_PMGMT    0x3088UL
0150 #define SYSIO_IMAP_GFX      0x3090UL
0151 #define SYSIO_IMAP_EUPA     0x3098UL
0152 
0153 #define bogon     ((unsigned long) -1)
0154 static unsigned long sysio_irq_offsets[] = {
0155     /* SBUS Slot 0 --> 3, level 1 --> 7 */
0156     SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
0157     SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
0158     SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
0159     SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
0160     SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
0161     SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
0162     SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
0163     SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
0164 
0165     /* Onboard devices (not relevant/used on SunFire). */
0166     SYSIO_IMAP_SCSI,
0167     SYSIO_IMAP_ETH,
0168     SYSIO_IMAP_BPP,
0169     bogon,
0170     SYSIO_IMAP_AUDIO,
0171     SYSIO_IMAP_PFAIL,
0172     bogon,
0173     bogon,
0174     SYSIO_IMAP_KMS,
0175     SYSIO_IMAP_FLPY,
0176     SYSIO_IMAP_SHW,
0177     SYSIO_IMAP_KBD,
0178     SYSIO_IMAP_MS,
0179     SYSIO_IMAP_SER,
0180     bogon,
0181     bogon,
0182     SYSIO_IMAP_TIM0,
0183     SYSIO_IMAP_TIM1,
0184     bogon,
0185     bogon,
0186     SYSIO_IMAP_UE,
0187     SYSIO_IMAP_CE,
0188     SYSIO_IMAP_SBERR,
0189     SYSIO_IMAP_PMGMT,
0190 };
0191 
0192 #undef bogon
0193 
0194 #define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
0195 
0196 /* Convert Interrupt Mapping register pointer to associated
0197  * Interrupt Clear register pointer, SYSIO specific version.
0198  */
0199 #define SYSIO_ICLR_UNUSED0  0x3400UL
0200 #define SYSIO_ICLR_SLOT0    0x3408UL
0201 #define SYSIO_ICLR_SLOT1    0x3448UL
0202 #define SYSIO_ICLR_SLOT2    0x3488UL
0203 #define SYSIO_ICLR_SLOT3    0x34c8UL
0204 static unsigned long sysio_imap_to_iclr(unsigned long imap)
0205 {
0206     unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
0207     return imap + diff;
0208 }
0209 
0210 static unsigned int sbus_build_irq(struct platform_device *op, unsigned int ino)
0211 {
0212     struct iommu *iommu = op->dev.archdata.iommu;
0213     unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
0214     unsigned long imap, iclr;
0215     int sbus_level = 0;
0216 
0217     imap = sysio_irq_offsets[ino];
0218     if (imap == ((unsigned long)-1)) {
0219         prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
0220                 ino);
0221         prom_halt();
0222     }
0223     imap += reg_base;
0224 
0225     /* SYSIO inconsistency.  For external SLOTS, we have to select
0226      * the right ICLR register based upon the lower SBUS irq level
0227      * bits.
0228      */
0229     if (ino >= 0x20) {
0230         iclr = sysio_imap_to_iclr(imap);
0231     } else {
0232         int sbus_slot = (ino & 0x18)>>3;
0233         
0234         sbus_level = ino & 0x7;
0235 
0236         switch(sbus_slot) {
0237         case 0:
0238             iclr = reg_base + SYSIO_ICLR_SLOT0;
0239             break;
0240         case 1:
0241             iclr = reg_base + SYSIO_ICLR_SLOT1;
0242             break;
0243         case 2:
0244             iclr = reg_base + SYSIO_ICLR_SLOT2;
0245             break;
0246         default:
0247         case 3:
0248             iclr = reg_base + SYSIO_ICLR_SLOT3;
0249             break;
0250         }
0251 
0252         iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
0253     }
0254     return build_irq(sbus_level, iclr, imap);
0255 }
0256 
0257 /* Error interrupt handling. */
0258 #define SYSIO_UE_AFSR   0x0030UL
0259 #define SYSIO_UE_AFAR   0x0038UL
0260 #define  SYSIO_UEAFSR_PPIO  0x8000000000000000UL /* Primary PIO cause         */
0261 #define  SYSIO_UEAFSR_PDRD  0x4000000000000000UL /* Primary DVMA read cause   */
0262 #define  SYSIO_UEAFSR_PDWR  0x2000000000000000UL /* Primary DVMA write cause  */
0263 #define  SYSIO_UEAFSR_SPIO  0x1000000000000000UL /* Secondary PIO is cause    */
0264 #define  SYSIO_UEAFSR_SDRD  0x0800000000000000UL /* Secondary DVMA read cause */
0265 #define  SYSIO_UEAFSR_SDWR  0x0400000000000000UL /* Secondary DVMA write cause*/
0266 #define  SYSIO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved                  */
0267 #define  SYSIO_UEAFSR_DOFF  0x0000e00000000000UL /* Doubleword Offset         */
0268 #define  SYSIO_UEAFSR_SIZE  0x00001c0000000000UL /* Bad transfer size 2^SIZE  */
0269 #define  SYSIO_UEAFSR_MID   0x000003e000000000UL /* UPA MID causing the fault */
0270 #define  SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved                  */
0271 static irqreturn_t sysio_ue_handler(int irq, void *dev_id)
0272 {
0273     struct platform_device *op = dev_id;
0274     struct iommu *iommu = op->dev.archdata.iommu;
0275     unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
0276     unsigned long afsr_reg, afar_reg;
0277     unsigned long afsr, afar, error_bits;
0278     int reported, portid;
0279 
0280     afsr_reg = reg_base + SYSIO_UE_AFSR;
0281     afar_reg = reg_base + SYSIO_UE_AFAR;
0282 
0283     /* Latch error status. */
0284     afsr = upa_readq(afsr_reg);
0285     afar = upa_readq(afar_reg);
0286 
0287     /* Clear primary/secondary error status bits. */
0288     error_bits = afsr &
0289         (SYSIO_UEAFSR_PPIO | SYSIO_UEAFSR_PDRD | SYSIO_UEAFSR_PDWR |
0290          SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR);
0291     upa_writeq(error_bits, afsr_reg);
0292 
0293     portid = of_getintprop_default(op->dev.of_node, "portid", -1);
0294 
0295     /* Log the error. */
0296     printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n",
0297            portid,
0298            (((error_bits & SYSIO_UEAFSR_PPIO) ?
0299          "PIO" :
0300          ((error_bits & SYSIO_UEAFSR_PDRD) ?
0301           "DVMA Read" :
0302           ((error_bits & SYSIO_UEAFSR_PDWR) ?
0303            "DVMA Write" : "???")))));
0304     printk("SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n",
0305            portid,
0306            (afsr & SYSIO_UEAFSR_DOFF) >> 45UL,
0307            (afsr & SYSIO_UEAFSR_SIZE) >> 42UL,
0308            (afsr & SYSIO_UEAFSR_MID) >> 37UL);
0309     printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
0310     printk("SYSIO[%x]: Secondary UE errors [", portid);
0311     reported = 0;
0312     if (afsr & SYSIO_UEAFSR_SPIO) {
0313         reported++;
0314         printk("(PIO)");
0315     }
0316     if (afsr & SYSIO_UEAFSR_SDRD) {
0317         reported++;
0318         printk("(DVMA Read)");
0319     }
0320     if (afsr & SYSIO_UEAFSR_SDWR) {
0321         reported++;
0322         printk("(DVMA Write)");
0323     }
0324     if (!reported)
0325         printk("(none)");
0326     printk("]\n");
0327 
0328     return IRQ_HANDLED;
0329 }
0330 
0331 #define SYSIO_CE_AFSR   0x0040UL
0332 #define SYSIO_CE_AFAR   0x0048UL
0333 #define  SYSIO_CEAFSR_PPIO  0x8000000000000000UL /* Primary PIO cause         */
0334 #define  SYSIO_CEAFSR_PDRD  0x4000000000000000UL /* Primary DVMA read cause   */
0335 #define  SYSIO_CEAFSR_PDWR  0x2000000000000000UL /* Primary DVMA write cause  */
0336 #define  SYSIO_CEAFSR_SPIO  0x1000000000000000UL /* Secondary PIO cause       */
0337 #define  SYSIO_CEAFSR_SDRD  0x0800000000000000UL /* Secondary DVMA read cause */
0338 #define  SYSIO_CEAFSR_SDWR  0x0400000000000000UL /* Secondary DVMA write cause*/
0339 #define  SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved                  */
0340 #define  SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits             */
0341 #define  SYSIO_CEAFSR_DOFF  0x0000e00000000000UL /* Double Offset             */
0342 #define  SYSIO_CEAFSR_SIZE  0x00001c0000000000UL /* Bad transfer size 2^SIZE  */
0343 #define  SYSIO_CEAFSR_MID   0x000003e000000000UL /* UPA MID causing the fault */
0344 #define  SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved                  */
0345 static irqreturn_t sysio_ce_handler(int irq, void *dev_id)
0346 {
0347     struct platform_device *op = dev_id;
0348     struct iommu *iommu = op->dev.archdata.iommu;
0349     unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
0350     unsigned long afsr_reg, afar_reg;
0351     unsigned long afsr, afar, error_bits;
0352     int reported, portid;
0353 
0354     afsr_reg = reg_base + SYSIO_CE_AFSR;
0355     afar_reg = reg_base + SYSIO_CE_AFAR;
0356 
0357     /* Latch error status. */
0358     afsr = upa_readq(afsr_reg);
0359     afar = upa_readq(afar_reg);
0360 
0361     /* Clear primary/secondary error status bits. */
0362     error_bits = afsr &
0363         (SYSIO_CEAFSR_PPIO | SYSIO_CEAFSR_PDRD | SYSIO_CEAFSR_PDWR |
0364          SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR);
0365     upa_writeq(error_bits, afsr_reg);
0366 
0367     portid = of_getintprop_default(op->dev.of_node, "portid", -1);
0368 
0369     printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n",
0370            portid,
0371            (((error_bits & SYSIO_CEAFSR_PPIO) ?
0372          "PIO" :
0373          ((error_bits & SYSIO_CEAFSR_PDRD) ?
0374           "DVMA Read" :
0375           ((error_bits & SYSIO_CEAFSR_PDWR) ?
0376            "DVMA Write" : "???")))));
0377 
0378     /* XXX Use syndrome and afar to print out module string just like
0379      * XXX UDB CE trap handler does... -DaveM
0380      */
0381     printk("SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n",
0382            portid,
0383            (afsr & SYSIO_CEAFSR_DOFF) >> 45UL,
0384            (afsr & SYSIO_CEAFSR_ESYND) >> 48UL,
0385            (afsr & SYSIO_CEAFSR_SIZE) >> 42UL,
0386            (afsr & SYSIO_CEAFSR_MID) >> 37UL);
0387     printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
0388 
0389     printk("SYSIO[%x]: Secondary CE errors [", portid);
0390     reported = 0;
0391     if (afsr & SYSIO_CEAFSR_SPIO) {
0392         reported++;
0393         printk("(PIO)");
0394     }
0395     if (afsr & SYSIO_CEAFSR_SDRD) {
0396         reported++;
0397         printk("(DVMA Read)");
0398     }
0399     if (afsr & SYSIO_CEAFSR_SDWR) {
0400         reported++;
0401         printk("(DVMA Write)");
0402     }
0403     if (!reported)
0404         printk("(none)");
0405     printk("]\n");
0406 
0407     return IRQ_HANDLED;
0408 }
0409 
0410 #define SYSIO_SBUS_AFSR     0x2010UL
0411 #define SYSIO_SBUS_AFAR     0x2018UL
0412 #define  SYSIO_SBAFSR_PLE   0x8000000000000000UL /* Primary Late PIO Error    */
0413 #define  SYSIO_SBAFSR_PTO   0x4000000000000000UL /* Primary SBUS Timeout      */
0414 #define  SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK    */
0415 #define  SYSIO_SBAFSR_SLE   0x1000000000000000UL /* Secondary Late PIO Error  */
0416 #define  SYSIO_SBAFSR_STO   0x0800000000000000UL /* Secondary SBUS Timeout    */
0417 #define  SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK  */
0418 #define  SYSIO_SBAFSR_RESV1 0x03ff000000000000UL /* Reserved                  */
0419 #define  SYSIO_SBAFSR_RD    0x0000800000000000UL /* Primary was late PIO read */
0420 #define  SYSIO_SBAFSR_RESV2 0x0000600000000000UL /* Reserved                  */
0421 #define  SYSIO_SBAFSR_SIZE  0x00001c0000000000UL /* Size of transfer          */
0422 #define  SYSIO_SBAFSR_MID   0x000003e000000000UL /* MID causing the error     */
0423 #define  SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved                  */
0424 static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id)
0425 {
0426     struct platform_device *op = dev_id;
0427     struct iommu *iommu = op->dev.archdata.iommu;
0428     unsigned long afsr_reg, afar_reg, reg_base;
0429     unsigned long afsr, afar, error_bits;
0430     int reported, portid;
0431 
0432     reg_base = iommu->write_complete_reg - 0x2000UL;
0433     afsr_reg = reg_base + SYSIO_SBUS_AFSR;
0434     afar_reg = reg_base + SYSIO_SBUS_AFAR;
0435 
0436     afsr = upa_readq(afsr_reg);
0437     afar = upa_readq(afar_reg);
0438 
0439     /* Clear primary/secondary error status bits. */
0440     error_bits = afsr &
0441         (SYSIO_SBAFSR_PLE | SYSIO_SBAFSR_PTO | SYSIO_SBAFSR_PBERR |
0442          SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR);
0443     upa_writeq(error_bits, afsr_reg);
0444 
0445     portid = of_getintprop_default(op->dev.of_node, "portid", -1);
0446 
0447     /* Log the error. */
0448     printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n",
0449            portid,
0450            (((error_bits & SYSIO_SBAFSR_PLE) ?
0451          "Late PIO Error" :
0452          ((error_bits & SYSIO_SBAFSR_PTO) ?
0453           "Time Out" :
0454           ((error_bits & SYSIO_SBAFSR_PBERR) ?
0455            "Error Ack" : "???")))),
0456            (afsr & SYSIO_SBAFSR_RD) ? 1 : 0);
0457     printk("SYSIO[%x]: size[%lx] MID[%lx]\n",
0458            portid,
0459            (afsr & SYSIO_SBAFSR_SIZE) >> 42UL,
0460            (afsr & SYSIO_SBAFSR_MID) >> 37UL);
0461     printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
0462     printk("SYSIO[%x]: Secondary SBUS errors [", portid);
0463     reported = 0;
0464     if (afsr & SYSIO_SBAFSR_SLE) {
0465         reported++;
0466         printk("(Late PIO Error)");
0467     }
0468     if (afsr & SYSIO_SBAFSR_STO) {
0469         reported++;
0470         printk("(Time Out)");
0471     }
0472     if (afsr & SYSIO_SBAFSR_SBERR) {
0473         reported++;
0474         printk("(Error Ack)");
0475     }
0476     if (!reported)
0477         printk("(none)");
0478     printk("]\n");
0479 
0480     /* XXX check iommu/strbuf for further error status XXX */
0481 
0482     return IRQ_HANDLED;
0483 }
0484 
0485 #define ECC_CONTROL 0x0020UL
0486 #define  SYSIO_ECNTRL_ECCEN 0x8000000000000000UL /* Enable ECC Checking   */
0487 #define  SYSIO_ECNTRL_UEEN  0x4000000000000000UL /* Enable UE Interrupts  */
0488 #define  SYSIO_ECNTRL_CEEN  0x2000000000000000UL /* Enable CE Interrupts  */
0489 
0490 #define SYSIO_UE_INO        0x34
0491 #define SYSIO_CE_INO        0x35
0492 #define SYSIO_SBUSERR_INO   0x36
0493 
0494 static void __init sysio_register_error_handlers(struct platform_device *op)
0495 {
0496     struct iommu *iommu = op->dev.archdata.iommu;
0497     unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
0498     unsigned int irq;
0499     u64 control;
0500     int portid;
0501 
0502     portid = of_getintprop_default(op->dev.of_node, "portid", -1);
0503 
0504     irq = sbus_build_irq(op, SYSIO_UE_INO);
0505     if (request_irq(irq, sysio_ue_handler, 0,
0506             "SYSIO_UE", op) < 0) {
0507         prom_printf("SYSIO[%x]: Cannot register UE interrupt.\n",
0508                 portid);
0509         prom_halt();
0510     }
0511 
0512     irq = sbus_build_irq(op, SYSIO_CE_INO);
0513     if (request_irq(irq, sysio_ce_handler, 0,
0514             "SYSIO_CE", op) < 0) {
0515         prom_printf("SYSIO[%x]: Cannot register CE interrupt.\n",
0516                 portid);
0517         prom_halt();
0518     }
0519 
0520     irq = sbus_build_irq(op, SYSIO_SBUSERR_INO);
0521     if (request_irq(irq, sysio_sbus_error_handler, 0,
0522             "SYSIO_SBERR", op) < 0) {
0523         prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n",
0524                 portid);
0525         prom_halt();
0526     }
0527 
0528     /* Now turn the error interrupts on and also enable ECC checking. */
0529     upa_writeq((SYSIO_ECNTRL_ECCEN |
0530             SYSIO_ECNTRL_UEEN  |
0531             SYSIO_ECNTRL_CEEN),
0532            reg_base + ECC_CONTROL);
0533 
0534     control = upa_readq(iommu->write_complete_reg);
0535     control |= 0x100UL; /* SBUS Error Interrupt Enable */
0536     upa_writeq(control, iommu->write_complete_reg);
0537 }
0538 
0539 /* Boot time initialization. */
0540 static void __init sbus_iommu_init(struct platform_device *op)
0541 {
0542     const struct linux_prom64_registers *pr;
0543     struct device_node *dp = op->dev.of_node;
0544     struct iommu *iommu;
0545     struct strbuf *strbuf;
0546     unsigned long regs, reg_base;
0547     int i, portid;
0548     u64 control;
0549 
0550     pr = of_get_property(dp, "reg", NULL);
0551     if (!pr) {
0552         prom_printf("sbus_iommu_init: Cannot map SYSIO "
0553                 "control registers.\n");
0554         prom_halt();
0555     }
0556     regs = pr->phys_addr;
0557 
0558     iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC);
0559     strbuf = kzalloc(sizeof(*strbuf), GFP_ATOMIC);
0560     if (!iommu || !strbuf)
0561         goto fatal_memory_error;
0562 
0563     op->dev.archdata.iommu = iommu;
0564     op->dev.archdata.stc = strbuf;
0565     op->dev.archdata.numa_node = NUMA_NO_NODE;
0566 
0567     reg_base = regs + SYSIO_IOMMUREG_BASE;
0568     iommu->iommu_control = reg_base + IOMMU_CONTROL;
0569     iommu->iommu_tsbbase = reg_base + IOMMU_TSBBASE;
0570     iommu->iommu_flush = reg_base + IOMMU_FLUSH;
0571     iommu->iommu_tags = iommu->iommu_control +
0572         (IOMMU_TAGDIAG - IOMMU_CONTROL);
0573 
0574     reg_base = regs + SYSIO_STRBUFREG_BASE;
0575     strbuf->strbuf_control = reg_base + STRBUF_CONTROL;
0576     strbuf->strbuf_pflush = reg_base + STRBUF_PFLUSH;
0577     strbuf->strbuf_fsync = reg_base + STRBUF_FSYNC;
0578 
0579     strbuf->strbuf_enabled = 1;
0580 
0581     strbuf->strbuf_flushflag = (volatile unsigned long *)
0582         ((((unsigned long)&strbuf->__flushflag_buf[0])
0583           + 63UL)
0584          & ~63UL);
0585     strbuf->strbuf_flushflag_pa = (unsigned long)
0586         __pa(strbuf->strbuf_flushflag);
0587 
0588     /* The SYSIO SBUS control register is used for dummy reads
0589      * in order to ensure write completion.
0590      */
0591     iommu->write_complete_reg = regs + 0x2000UL;
0592 
0593     portid = of_getintprop_default(op->dev.of_node, "portid", -1);
0594     printk(KERN_INFO "SYSIO: UPA portID %x, at %016lx\n",
0595            portid, regs);
0596 
0597     /* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */
0598     if (iommu_table_init(iommu, IO_TSB_SIZE, MAP_BASE, 0xffffffff, -1))
0599         goto fatal_memory_error;
0600 
0601     control = upa_readq(iommu->iommu_control);
0602     control = ((7UL << 16UL)    |
0603            (0UL << 2UL)     |
0604            (1UL << 1UL)     |
0605            (1UL << 0UL));
0606     upa_writeq(control, iommu->iommu_control);
0607 
0608     /* Clean out any cruft in the IOMMU using
0609      * diagnostic accesses.
0610      */
0611     for (i = 0; i < 16; i++) {
0612         unsigned long dram, tag;
0613 
0614         dram = iommu->iommu_control + (IOMMU_DRAMDIAG - IOMMU_CONTROL);
0615         tag = iommu->iommu_control + (IOMMU_TAGDIAG - IOMMU_CONTROL);
0616 
0617         dram += (unsigned long)i * 8UL;
0618         tag += (unsigned long)i * 8UL;
0619         upa_writeq(0, dram);
0620         upa_writeq(0, tag);
0621     }
0622     upa_readq(iommu->write_complete_reg);
0623 
0624     /* Give the TSB to SYSIO. */
0625     upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
0626 
0627     /* Setup streaming buffer, DE=1 SB_EN=1 */
0628     control = (1UL << 1UL) | (1UL << 0UL);
0629     upa_writeq(control, strbuf->strbuf_control);
0630 
0631     /* Clear out the tags using diagnostics. */
0632     for (i = 0; i < 16; i++) {
0633         unsigned long ptag, ltag;
0634 
0635         ptag = strbuf->strbuf_control +
0636             (STRBUF_PTAGDIAG - STRBUF_CONTROL);
0637         ltag = strbuf->strbuf_control +
0638             (STRBUF_LTAGDIAG - STRBUF_CONTROL);
0639         ptag += (unsigned long)i * 8UL;
0640         ltag += (unsigned long)i * 8UL;
0641 
0642         upa_writeq(0UL, ptag);
0643         upa_writeq(0UL, ltag);
0644     }
0645 
0646     /* Enable DVMA arbitration for all devices/slots. */
0647     control = upa_readq(iommu->write_complete_reg);
0648     control |= 0x3fUL;
0649     upa_writeq(control, iommu->write_complete_reg);
0650 
0651     /* Now some Xfire specific grot... */
0652     if (this_is_starfire)
0653         starfire_hookup(portid);
0654 
0655     sysio_register_error_handlers(op);
0656     return;
0657 
0658 fatal_memory_error:
0659     kfree(iommu);
0660     kfree(strbuf);
0661     prom_printf("sbus_iommu_init: Fatal memory allocation error.\n");
0662 }
0663 
0664 static int __init sbus_init(void)
0665 {
0666     struct device_node *dp;
0667 
0668     for_each_node_by_name(dp, "sbus") {
0669         struct platform_device *op = of_find_device_by_node(dp);
0670 
0671         sbus_iommu_init(op);
0672         of_propagate_archdata(op);
0673     }
0674 
0675     return 0;
0676 }
0677 
0678 subsys_initcall(sbus_init);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!