sparc/kernel/psycho_common.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* psycho_common.c: Code common to PSYCHO and derivative PCI controllers.
0003  *
0004  * Copyright (C) 2008 David S. Miller <davem@davemloft.net>
0005  */
0006 #include <linux/kernel.h>
0007 #include <linux/interrupt.h>
0008 #include <linux/numa.h>
0009
0010 #include <asm/upa.h>
0011
0012 #include "pci_impl.h"
0013 #include "iommu_common.h"
0014 #include "psycho_common.h"
0015
0016 #define  PSYCHO_STRBUF_CTRL_DENAB   0x0000000000000002ULL
0017 #define  PSYCHO_STCERR_WRITE        0x0000000000000002ULL
0018 #define  PSYCHO_STCERR_READ     0x0000000000000001ULL
0019 #define  PSYCHO_STCTAG_PPN      0x0fffffff00000000ULL
0020 #define  PSYCHO_STCTAG_VPN      0x00000000ffffe000ULL
0021 #define  PSYCHO_STCTAG_VALID        0x0000000000000002ULL
0022 #define  PSYCHO_STCTAG_WRITE        0x0000000000000001ULL
0023 #define  PSYCHO_STCLINE_LINDX       0x0000000001e00000ULL
0024 #define  PSYCHO_STCLINE_SPTR        0x00000000001f8000ULL
0025 #define  PSYCHO_STCLINE_LADDR       0x0000000000007f00ULL
0026 #define  PSYCHO_STCLINE_EPTR        0x00000000000000fcULL
0027 #define  PSYCHO_STCLINE_VALID       0x0000000000000002ULL
0028 #define  PSYCHO_STCLINE_FOFN        0x0000000000000001ULL
0029
0030 static DEFINE_SPINLOCK(stc_buf_lock);
0031 static unsigned long stc_error_buf[128];
0032 static unsigned long stc_tag_buf[16];
0033 static unsigned long stc_line_buf[16];
0034
0035 static void psycho_check_stc_error(struct pci_pbm_info *pbm)
0036 {
0037     unsigned long err_base, tag_base, line_base;
0038     struct strbuf *strbuf = &pbm->stc;
0039     u64 control;
0040     int i;
0041
0042     if (!strbuf->strbuf_control)
0043         return;
0044
0045     err_base = strbuf->strbuf_err_stat;
0046     tag_base = strbuf->strbuf_tag_diag;
0047     line_base = strbuf->strbuf_line_diag;
0048
0049     spin_lock(&stc_buf_lock);
0050
0051     /* This is __REALLY__ dangerous.  When we put the streaming
0052      * buffer into diagnostic mode to probe it's tags and error
0053      * status, we _must_ clear all of the line tag valid bits
0054      * before re-enabling the streaming buffer.  If any dirty data
0055      * lives in the STC when we do this, we will end up
0056      * invalidating it before it has a chance to reach main
0057      * memory.
0058      */
0059     control = upa_readq(strbuf->strbuf_control);
0060     upa_writeq(control | PSYCHO_STRBUF_CTRL_DENAB, strbuf->strbuf_control);
0061     for (i = 0; i < 128; i++) {
0062         u64 val;
0063
0064         val = upa_readq(err_base + (i * 8UL));
0065         upa_writeq(0UL, err_base + (i * 8UL));
0066         stc_error_buf[i] = val;
0067     }
0068     for (i = 0; i < 16; i++) {
0069         stc_tag_buf[i] = upa_readq(tag_base + (i * 8UL));
0070         stc_line_buf[i] = upa_readq(line_base + (i * 8UL));
0071         upa_writeq(0UL, tag_base + (i * 8UL));
0072         upa_writeq(0UL, line_base + (i * 8UL));
0073     }
0074
0075     /* OK, state is logged, exit diagnostic mode. */
0076     upa_writeq(control, strbuf->strbuf_control);
0077
0078     for (i = 0; i < 16; i++) {
0079         int j, saw_error, first, last;
0080
0081         saw_error = 0;
0082         first = i * 8;
0083         last = first + 8;
0084         for (j = first; j < last; j++) {
0085             u64 errval = stc_error_buf[j];
0086             if (errval != 0) {
0087                 saw_error++;
0088                 printk(KERN_ERR "%s: STC_ERR(%d)[wr(%d)"
0089                        "rd(%d)]\n",
0090                        pbm->name,
0091                        j,
0092                        (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
0093                        (errval & PSYCHO_STCERR_READ) ? 1 : 0);
0094             }
0095         }
0096         if (saw_error != 0) {
0097             u64 tagval = stc_tag_buf[i];
0098             u64 lineval = stc_line_buf[i];
0099             printk(KERN_ERR "%s: STC_TAG(%d)[PA(%016llx)VA(%08llx)"
0100                    "V(%d)W(%d)]\n",
0101                    pbm->name,
0102                    i,
0103                    ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
0104                    (tagval & PSYCHO_STCTAG_VPN),
0105                    ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
0106                    ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
0107             printk(KERN_ERR "%s: STC_LINE(%d)[LIDX(%llx)SP(%llx)"
0108                    "LADDR(%llx)EP(%llx)V(%d)FOFN(%d)]\n",
0109                    pbm->name,
0110                    i,
0111                    ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
0112                    ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
0113                    ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
0114                    ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
0115                    ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
0116                    ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
0117         }
0118     }
0119
0120     spin_unlock(&stc_buf_lock);
0121 }
0122
0123 #define PSYCHO_IOMMU_TAG        0xa580UL
0124 #define PSYCHO_IOMMU_DATA       0xa600UL
0125
0126 static void psycho_record_iommu_tags_and_data(struct pci_pbm_info *pbm,
0127                           u64 *tag, u64 *data)
0128 {
0129     int i;
0130
0131     for (i = 0; i < 16; i++) {
0132         unsigned long base = pbm->controller_regs;
0133         unsigned long off = i * 8UL;
0134
0135         tag[i] = upa_readq(base + PSYCHO_IOMMU_TAG+off);
0136         data[i] = upa_readq(base + PSYCHO_IOMMU_DATA+off);
0137
0138         /* Now clear out the entry. */
0139         upa_writeq(0, base + PSYCHO_IOMMU_TAG + off);
0140         upa_writeq(0, base + PSYCHO_IOMMU_DATA + off);
0141     }
0142 }
0143
0144 #define  PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
0145 #define  PSYCHO_IOMMU_TAG_ERR    (0x1UL << 22UL)
0146 #define  PSYCHO_IOMMU_TAG_WRITE  (0x1UL << 21UL)
0147 #define  PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
0148 #define  PSYCHO_IOMMU_TAG_SIZE   (0x1UL << 19UL)
0149 #define  PSYCHO_IOMMU_TAG_VPAGE  0x7ffffULL
0150 #define  PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
0151 #define  PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
0152 #define  PSYCHO_IOMMU_DATA_PPAGE 0xfffffffULL
0153
0154 static void psycho_dump_iommu_tags_and_data(struct pci_pbm_info *pbm,
0155                         u64 *tag, u64 *data)
0156 {
0157     int i;
0158
0159     for (i = 0; i < 16; i++) {
0160         u64 tag_val, data_val;
0161         const char *type_str;
0162         tag_val = tag[i];
0163         if (!(tag_val & PSYCHO_IOMMU_TAG_ERR))
0164             continue;
0165
0166         data_val = data[i];
0167         switch((tag_val & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
0168         case 0:
0169             type_str = "Protection Error";
0170             break;
0171         case 1:
0172             type_str = "Invalid Error";
0173             break;
0174         case 2:
0175             type_str = "TimeOut Error";
0176             break;
0177         case 3:
0178         default:
0179             type_str = "ECC Error";
0180             break;
0181         }
0182
0183         printk(KERN_ERR "%s: IOMMU TAG(%d)[error(%s) wr(%d) "
0184                "str(%d) sz(%dK) vpg(%08llx)]\n",
0185                pbm->name, i, type_str,
0186                ((tag_val & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
0187                ((tag_val & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
0188                ((tag_val & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
0189                (tag_val & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
0190         printk(KERN_ERR "%s: IOMMU DATA(%d)[valid(%d) cache(%d) "
0191                "ppg(%016llx)]\n",
0192                pbm->name, i,
0193                ((data_val & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
0194                ((data_val & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
0195                (data_val & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
0196     }
0197 }
0198
0199 #define  PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL
0200 #define  PSYCHO_IOMMU_CTRL_XLTEERR  0x0000000001000000UL
0201
0202 void psycho_check_iommu_error(struct pci_pbm_info *pbm,
0203                   unsigned long afsr,
0204                   unsigned long afar,
0205                   enum psycho_error_type type)
0206 {
0207     u64 control, iommu_tag[16], iommu_data[16];
0208     struct iommu *iommu = pbm->iommu;
0209     unsigned long flags;
0210
0211     spin_lock_irqsave(&iommu->lock, flags);
0212     control = upa_readq(iommu->iommu_control);
0213     if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
0214         const char *type_str;
0215
0216         control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
0217         upa_writeq(control, iommu->iommu_control);
0218
0219         switch ((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
0220         case 0:
0221             type_str = "Protection Error";
0222             break;
0223         case 1:
0224             type_str = "Invalid Error";
0225             break;
0226         case 2:
0227             type_str = "TimeOut Error";
0228             break;
0229         case 3:
0230         default:
0231             type_str = "ECC Error";
0232             break;
0233         }
0234         printk(KERN_ERR "%s: IOMMU Error, type[%s]\n",
0235                pbm->name, type_str);
0236
0237         /* It is very possible for another DVMA to occur while
0238          * we do this probe, and corrupt the system further.
0239          * But we are so screwed at this point that we are
0240          * likely to crash hard anyways, so get as much
0241          * diagnostic information to the console as we can.
0242          */
0243         psycho_record_iommu_tags_and_data(pbm, iommu_tag, iommu_data);
0244         psycho_dump_iommu_tags_and_data(pbm, iommu_tag, iommu_data);
0245     }
0246     psycho_check_stc_error(pbm);
0247     spin_unlock_irqrestore(&iommu->lock, flags);
0248 }
0249
0250 #define  PSYCHO_PCICTRL_SBH_ERR  0x0000000800000000UL
0251 #define  PSYCHO_PCICTRL_SERR     0x0000000400000000UL
0252
0253 static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm)
0254 {
0255     irqreturn_t ret = IRQ_NONE;
0256     u64 csr, csr_error_bits;
0257     u16 stat, *addr;
0258
0259     csr = upa_readq(pbm->pci_csr);
0260     csr_error_bits = csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
0261     if (csr_error_bits) {
0262         /* Clear the errors.  */
0263         upa_writeq(csr, pbm->pci_csr);
0264
0265         /* Log 'em.  */
0266         if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
0267             printk(KERN_ERR "%s: PCI streaming byte hole "
0268                    "error asserted.\n", pbm->name);
0269         if (csr_error_bits & PSYCHO_PCICTRL_SERR)
0270             printk(KERN_ERR "%s: PCI SERR signal asserted.\n",
0271                    pbm->name);
0272         ret = IRQ_HANDLED;
0273     }
0274     addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
0275                     0, PCI_STATUS);
0276     pci_config_read16(addr, &stat);
0277     if (stat & (PCI_STATUS_PARITY |
0278             PCI_STATUS_SIG_TARGET_ABORT |
0279             PCI_STATUS_REC_TARGET_ABORT |
0280             PCI_STATUS_REC_MASTER_ABORT |
0281             PCI_STATUS_SIG_SYSTEM_ERROR)) {
0282         printk(KERN_ERR "%s: PCI bus error, PCI_STATUS[%04x]\n",
0283                pbm->name, stat);
0284         pci_config_write16(addr, 0xffff);
0285         ret = IRQ_HANDLED;
0286     }
0287     return ret;
0288 }
0289
0290 #define  PSYCHO_PCIAFSR_PMA 0x8000000000000000ULL
0291 #define  PSYCHO_PCIAFSR_PTA 0x4000000000000000ULL
0292 #define  PSYCHO_PCIAFSR_PRTRY   0x2000000000000000ULL
0293 #define  PSYCHO_PCIAFSR_PPERR   0x1000000000000000ULL
0294 #define  PSYCHO_PCIAFSR_SMA 0x0800000000000000ULL
0295 #define  PSYCHO_PCIAFSR_STA 0x0400000000000000ULL
0296 #define  PSYCHO_PCIAFSR_SRTRY   0x0200000000000000ULL
0297 #define  PSYCHO_PCIAFSR_SPERR   0x0100000000000000ULL
0298 #define  PSYCHO_PCIAFSR_RESV1   0x00ff000000000000ULL
0299 #define  PSYCHO_PCIAFSR_BMSK    0x0000ffff00000000ULL
0300 #define  PSYCHO_PCIAFSR_BLK 0x0000000080000000ULL
0301 #define  PSYCHO_PCIAFSR_RESV2   0x0000000040000000ULL
0302 #define  PSYCHO_PCIAFSR_MID 0x000000003e000000ULL
0303 #define  PSYCHO_PCIAFSR_RESV3   0x0000000001ffffffULL
0304
0305 irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
0306 {
0307     struct pci_pbm_info *pbm = dev_id;
0308     u64 afsr, afar, error_bits;
0309     int reported;
0310
0311     afsr = upa_readq(pbm->pci_afsr);
0312     afar = upa_readq(pbm->pci_afar);
0313     error_bits = afsr &
0314         (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
0315          PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
0316          PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
0317          PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
0318     if (!error_bits)
0319         return psycho_pcierr_intr_other(pbm);
0320     upa_writeq(error_bits, pbm->pci_afsr);
0321     printk(KERN_ERR "%s: PCI Error, primary error type[%s]\n",
0322            pbm->name,
0323            (((error_bits & PSYCHO_PCIAFSR_PMA) ?
0324          "Master Abort" :
0325          ((error_bits & PSYCHO_PCIAFSR_PTA) ?
0326           "Target Abort" :
0327           ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
0328            "Excessive Retries" :
0329            ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
0330             "Parity Error" : "???"))))));
0331     printk(KERN_ERR "%s: bytemask[%04llx] UPA_MID[%02llx] was_block(%d)\n",
0332            pbm->name,
0333            (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
0334            (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
0335            (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
0336     printk(KERN_ERR "%s: PCI AFAR [%016llx]\n", pbm->name, afar);
0337     printk(KERN_ERR "%s: PCI Secondary errors [", pbm->name);
0338     reported = 0;
0339     if (afsr & PSYCHO_PCIAFSR_SMA) {
0340         reported++;
0341         printk("(Master Abort)");
0342     }
0343     if (afsr & PSYCHO_PCIAFSR_STA) {
0344         reported++;
0345         printk("(Target Abort)");
0346     }
0347     if (afsr & PSYCHO_PCIAFSR_SRTRY) {
0348         reported++;
0349         printk("(Excessive Retries)");
0350     }
0351     if (afsr & PSYCHO_PCIAFSR_SPERR) {
0352         reported++;
0353         printk("(Parity Error)");
0354     }
0355     if (!reported)
0356         printk("(none)");
0357     printk("]\n");
0358
0359     if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
0360         psycho_check_iommu_error(pbm, afsr, afar, PCI_ERR);
0361         pci_scan_for_target_abort(pbm, pbm->pci_bus);
0362     }
0363     if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
0364         pci_scan_for_master_abort(pbm, pbm->pci_bus);
0365
0366     if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
0367         pci_scan_for_parity_error(pbm, pbm->pci_bus);
0368
0369     return IRQ_HANDLED;
0370 }
0371
0372 static void psycho_iommu_flush(struct pci_pbm_info *pbm)
0373 {
0374     int i;
0375
0376     for (i = 0; i < 16; i++) {
0377         unsigned long off = i * 8;
0378
0379         upa_writeq(0, pbm->controller_regs + PSYCHO_IOMMU_TAG + off);
0380         upa_writeq(0, pbm->controller_regs + PSYCHO_IOMMU_DATA + off);
0381     }
0382 }
0383
0384 #define PSYCHO_IOMMU_CONTROL        0x0200UL
0385 #define  PSYCHO_IOMMU_CTRL_TSBSZ    0x0000000000070000UL
0386 #define  PSYCHO_IOMMU_TSBSZ_1K          0x0000000000000000UL
0387 #define  PSYCHO_IOMMU_TSBSZ_2K          0x0000000000010000UL
0388 #define  PSYCHO_IOMMU_TSBSZ_4K          0x0000000000020000UL
0389 #define  PSYCHO_IOMMU_TSBSZ_8K          0x0000000000030000UL
0390 #define  PSYCHO_IOMMU_TSBSZ_16K         0x0000000000040000UL
0391 #define  PSYCHO_IOMMU_TSBSZ_32K         0x0000000000050000UL
0392 #define  PSYCHO_IOMMU_TSBSZ_64K         0x0000000000060000UL
0393 #define  PSYCHO_IOMMU_TSBSZ_128K        0x0000000000070000UL
0394 #define  PSYCHO_IOMMU_CTRL_TBWSZ        0x0000000000000004UL
0395 #define  PSYCHO_IOMMU_CTRL_DENAB        0x0000000000000002UL
0396 #define  PSYCHO_IOMMU_CTRL_ENAB         0x0000000000000001UL
0397 #define PSYCHO_IOMMU_FLUSH      0x0210UL
0398 #define PSYCHO_IOMMU_TSBBASE        0x0208UL
0399
0400 int psycho_iommu_init(struct pci_pbm_info *pbm, int tsbsize,
0401               u32 dvma_offset, u32 dma_mask,
0402               unsigned long write_complete_offset)
0403 {
0404     struct iommu *iommu = pbm->iommu;
0405     u64 control;
0406     int err;
0407
0408     iommu->iommu_control  = pbm->controller_regs + PSYCHO_IOMMU_CONTROL;
0409     iommu->iommu_tsbbase  = pbm->controller_regs + PSYCHO_IOMMU_TSBBASE;
0410     iommu->iommu_flush    = pbm->controller_regs + PSYCHO_IOMMU_FLUSH;
0411     iommu->iommu_tags     = pbm->controller_regs + PSYCHO_IOMMU_TAG;
0412     iommu->write_complete_reg = (pbm->controller_regs +
0413                      write_complete_offset);
0414
0415     iommu->iommu_ctxflush = 0;
0416
0417     control = upa_readq(iommu->iommu_control);
0418     control |= PSYCHO_IOMMU_CTRL_DENAB;
0419     upa_writeq(control, iommu->iommu_control);
0420
0421     psycho_iommu_flush(pbm);
0422
0423     /* Leave diag mode enabled for full-flushing done in pci_iommu.c */
0424     err = iommu_table_init(iommu, tsbsize * 1024 * 8,
0425                    dvma_offset, dma_mask, pbm->numa_node);
0426     if (err)
0427         return err;
0428
0429     upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
0430
0431     control = upa_readq(iommu->iommu_control);
0432     control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
0433     control |= PSYCHO_IOMMU_CTRL_ENAB;
0434
0435     switch (tsbsize) {
0436     case 64:
0437         control |= PSYCHO_IOMMU_TSBSZ_64K;
0438         break;
0439     case 128:
0440         control |= PSYCHO_IOMMU_TSBSZ_128K;
0441         break;
0442     default:
0443         return -EINVAL;
0444     }
0445
0446     upa_writeq(control, iommu->iommu_control);
0447
0448     return 0;
0449
0450 }
0451
0452 void psycho_pbm_init_common(struct pci_pbm_info *pbm, struct platform_device *op,
0453                 const char *chip_name, int chip_type)
0454 {
0455     struct device_node *dp = op->dev.of_node;
0456
0457     pbm->name = dp->full_name;
0458     pbm->numa_node = NUMA_NO_NODE;
0459     pbm->chip_type = chip_type;
0460     pbm->chip_version = of_getintprop_default(dp, "version#", 0);
0461     pbm->chip_revision = of_getintprop_default(dp, "module-revision#", 0);
0462     pbm->op = op;
0463     pbm->pci_ops = &sun4u_pci_ops;
0464     pbm->config_space_reg_bits = 8;
0465     pbm->index = pci_num_pbms++;
0466     pci_get_pbm_props(pbm);
0467     pci_determine_mem_io_space(pbm);
0468
0469     printk(KERN_INFO "%s: %s PCI Bus Module ver[%x:%x]\n",
0470            pbm->name, chip_name,
0471            pbm->chip_version, pbm->chip_revision);
0472 }