sparc/kernel/pcic.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * pcic.c: MicroSPARC-IIep PCI controller support
0004  *
0005  * Copyright (C) 1998 V. Roganov and G. Raiko
0006  *
0007  * Code is derived from Ultra/PCI PSYCHO controller support, see that
0008  * for author info.
0009  *
0010  * Support for diverse IIep based platforms by Pete Zaitcev.
0011  * CP-1200 by Eric Brower.
0012  */
0013
0014 #include <linux/kernel.h>
0015 #include <linux/types.h>
0016 #include <linux/init.h>
0017 #include <linux/mm.h>
0018 #include <linux/slab.h>
0019 #include <linux/jiffies.h>
0020
0021 #include <asm/swift.h> /* for cache flushing. */
0022 #include <asm/io.h>
0023
0024 #include <linux/ctype.h>
0025 #include <linux/pci.h>
0026 #include <linux/time.h>
0027 #include <linux/timex.h>
0028 #include <linux/interrupt.h>
0029 #include <linux/export.h>
0030
0031 #include <asm/irq.h>
0032 #include <asm/oplib.h>
0033 #include <asm/prom.h>
0034 #include <asm/pcic.h>
0035 #include <asm/timex.h>
0036 #include <asm/timer.h>
0037 #include <linux/uaccess.h>
0038 #include <asm/irq_regs.h>
0039
0040 #include "kernel.h"
0041 #include "irq.h"
0042
0043 /*
0044  * I studied different documents and many live PROMs both from 2.30
0045  * family and 3.xx versions. I came to the amazing conclusion: there is
0046  * absolutely no way to route interrupts in IIep systems relying on
0047  * information which PROM presents. We must hardcode interrupt routing
0048  * schematics. And this actually sucks.   -- zaitcev 1999/05/12
0049  *
0050  * To find irq for a device we determine which routing map
0051  * is in effect or, in other words, on which machine we are running.
0052  * We use PROM name for this although other techniques may be used
0053  * in special cases (Gleb reports a PROMless IIep based system).
0054  * Once we know the map we take device configuration address and
0055  * find PCIC pin number where INT line goes. Then we may either program
0056  * preferred irq into the PCIC or supply the preexisting irq to the device.
0057  */
0058 struct pcic_ca2irq {
0059     unsigned char busno;        /* PCI bus number */
0060     unsigned char devfn;        /* Configuration address */
0061     unsigned char pin;      /* PCIC external interrupt pin */
0062     unsigned char irq;      /* Preferred IRQ (mappable in PCIC) */
0063     unsigned int force;     /* Enforce preferred IRQ */
0064 };
0065
0066 struct pcic_sn2list {
0067     char *sysname;
0068     struct pcic_ca2irq *intmap;
0069     int mapdim;
0070 };
0071
0072 /*
0073  * JavaEngine-1 apparently has different versions.
0074  *
0075  * According to communications with Sun folks, for P2 build 501-4628-03:
0076  * pin 0 - parallel, audio;
0077  * pin 1 - Ethernet;
0078  * pin 2 - su;
0079  * pin 3 - PS/2 kbd and mouse.
0080  *
0081  * OEM manual (805-1486):
0082  * pin 0: Ethernet
0083  * pin 1: All EBus
0084  * pin 2: IGA (unused)
0085  * pin 3: Not connected
0086  * OEM manual says that 501-4628 & 501-4811 are the same thing,
0087  * only the latter has NAND flash in place.
0088  *
0089  * So far unofficial Sun wins over the OEM manual. Poor OEMs...
0090  */
0091 static struct pcic_ca2irq pcic_i_je1a[] = { /* 501-4811-03 */
0092     { 0, 0x00, 2, 12, 0 },      /* EBus: hogs all */
0093     { 0, 0x01, 1,  6, 1 },      /* Happy Meal */
0094     { 0, 0x80, 0,  7, 0 },      /* IGA (unused) */
0095 };
0096
0097 /* XXX JS-E entry is incomplete - PCI Slot 2 address (pin 7)? */
0098 static struct pcic_ca2irq pcic_i_jse[] = {
0099     { 0, 0x00, 0, 13, 0 },      /* Ebus - serial and keyboard */
0100     { 0, 0x01, 1,  6, 0 },      /* hme */
0101     { 0, 0x08, 2,  9, 0 },      /* VGA - we hope not used :) */
0102     { 0, 0x10, 6,  8, 0 },      /* PCI INTA# in Slot 1 */
0103     { 0, 0x18, 7, 12, 0 },      /* PCI INTA# in Slot 2, shared w. RTC */
0104     { 0, 0x38, 4,  9, 0 },      /* All ISA devices. Read 8259. */
0105     { 0, 0x80, 5, 11, 0 },      /* EIDE */
0106     /* {0,0x88, 0,0,0} - unknown device... PMU? Probably no interrupt. */
0107     { 0, 0xA0, 4,  9, 0 },      /* USB */
0108     /*
0109      * Some pins belong to non-PCI devices, we hardcode them in drivers.
0110      * sun4m timers - irq 10, 14
0111      * PC style RTC - pin 7, irq 4 ?
0112      * Smart card, Parallel - pin 4 shared with USB, ISA
0113      * audio - pin 3, irq 5 ?
0114      */
0115 };
0116
0117 /* SPARCengine-6 was the original release name of CP1200.
0118  * The documentation differs between the two versions
0119  */
0120 static struct pcic_ca2irq pcic_i_se6[] = {
0121     { 0, 0x08, 0,  2, 0 },      /* SCSI */
0122     { 0, 0x01, 1,  6, 0 },      /* HME  */
0123     { 0, 0x00, 3, 13, 0 },      /* EBus */
0124 };
0125
0126 /*
0127  * Krups (courtesy of Varol Kaptan)
0128  * No documentation available, but it was easy to guess
0129  * because it was very similar to Espresso.
0130  *
0131  * pin 0 - kbd, mouse, serial;
0132  * pin 1 - Ethernet;
0133  * pin 2 - igs (we do not use it);
0134  * pin 3 - audio;
0135  * pin 4,5,6 - unused;
0136  * pin 7 - RTC (from P2 onwards as David B. says).
0137  */
0138 static struct pcic_ca2irq pcic_i_jk[] = {
0139     { 0, 0x00, 0, 13, 0 },      /* Ebus - serial and keyboard */
0140     { 0, 0x01, 1,  6, 0 },      /* hme */
0141 };
0142
0143 /*
0144  * Several entries in this list may point to the same routing map
0145  * as several PROMs may be installed on the same physical board.
0146  */
0147 #define SN2L_INIT(name, map)    \
0148   { name, map, ARRAY_SIZE(map) }
0149
0150 static struct pcic_sn2list pcic_known_sysnames[] = {
0151     SN2L_INIT("SUNW,JavaEngine1", pcic_i_je1a), /* JE1, PROM 2.32 */
0152     SN2L_INIT("SUNW,JS-E", pcic_i_jse), /* PROLL JavaStation-E */
0153     SN2L_INIT("SUNW,SPARCengine-6", pcic_i_se6), /* SPARCengine-6/CP-1200 */
0154     SN2L_INIT("SUNW,JS-NC", pcic_i_jk), /* PROLL JavaStation-NC */
0155     SN2L_INIT("SUNW,JSIIep", pcic_i_jk),    /* OBP JavaStation-NC */
0156     { NULL, NULL, 0 }
0157 };
0158
0159 /*
0160  * Only one PCIC per IIep,
0161  * and since we have no SMP IIep, only one per system.
0162  */
0163 static int pcic0_up;
0164 static struct linux_pcic pcic0;
0165
0166 void __iomem *pcic_regs;
0167 static volatile int pcic_speculative;
0168 static volatile int pcic_trapped;
0169
0170 /* forward */
0171 unsigned int pcic_build_device_irq(struct platform_device *op,
0172                                    unsigned int real_irq);
0173
0174 #define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3))
0175
0176 static int pcic_read_config_dword(unsigned int busno, unsigned int devfn,
0177     int where, u32 *value)
0178 {
0179     struct linux_pcic *pcic;
0180     unsigned long flags;
0181
0182     pcic = &pcic0;
0183
0184     local_irq_save(flags);
0185 #if 0 /* does not fail here */
0186     pcic_speculative = 1;
0187     pcic_trapped = 0;
0188 #endif
0189     writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
0190 #if 0 /* does not fail here */
0191     nop();
0192     if (pcic_trapped) {
0193         local_irq_restore(flags);
0194         *value = ~0;
0195         return 0;
0196     }
0197 #endif
0198     pcic_speculative = 2;
0199     pcic_trapped = 0;
0200     *value = readl(pcic->pcic_config_space_data + (where&4));
0201     nop();
0202     if (pcic_trapped) {
0203         pcic_speculative = 0;
0204         local_irq_restore(flags);
0205         *value = ~0;
0206         return 0;
0207     }
0208     pcic_speculative = 0;
0209     local_irq_restore(flags);
0210     return 0;
0211 }
0212
0213 static int pcic_read_config(struct pci_bus *bus, unsigned int devfn,
0214    int where, int size, u32 *val)
0215 {
0216     unsigned int v;
0217
0218     if (bus->number != 0) return -EINVAL;
0219     switch (size) {
0220     case 1:
0221         pcic_read_config_dword(bus->number, devfn, where&~3, &v);
0222         *val = 0xff & (v >> (8*(where & 3)));
0223         return 0;
0224     case 2:
0225         if (where&1) return -EINVAL;
0226         pcic_read_config_dword(bus->number, devfn, where&~3, &v);
0227         *val = 0xffff & (v >> (8*(where & 3)));
0228         return 0;
0229     case 4:
0230         if (where&3) return -EINVAL;
0231         pcic_read_config_dword(bus->number, devfn, where&~3, val);
0232         return 0;
0233     }
0234     return -EINVAL;
0235 }
0236
0237 static int pcic_write_config_dword(unsigned int busno, unsigned int devfn,
0238     int where, u32 value)
0239 {
0240     struct linux_pcic *pcic;
0241     unsigned long flags;
0242
0243     pcic = &pcic0;
0244
0245     local_irq_save(flags);
0246     writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
0247     writel(value, pcic->pcic_config_space_data + (where&4));
0248     local_irq_restore(flags);
0249     return 0;
0250 }
0251
0252 static int pcic_write_config(struct pci_bus *bus, unsigned int devfn,
0253    int where, int size, u32 val)
0254 {
0255     unsigned int v;
0256
0257     if (bus->number != 0) return -EINVAL;
0258     switch (size) {
0259     case 1:
0260         pcic_read_config_dword(bus->number, devfn, where&~3, &v);
0261         v = (v & ~(0xff << (8*(where&3)))) |
0262             ((0xff&val) << (8*(where&3)));
0263         return pcic_write_config_dword(bus->number, devfn, where&~3, v);
0264     case 2:
0265         if (where&1) return -EINVAL;
0266         pcic_read_config_dword(bus->number, devfn, where&~3, &v);
0267         v = (v & ~(0xffff << (8*(where&3)))) |
0268             ((0xffff&val) << (8*(where&3)));
0269         return pcic_write_config_dword(bus->number, devfn, where&~3, v);
0270     case 4:
0271         if (where&3) return -EINVAL;
0272         return pcic_write_config_dword(bus->number, devfn, where, val);
0273     }
0274     return -EINVAL;
0275 }
0276
0277 static struct pci_ops pcic_ops = {
0278     .read =     pcic_read_config,
0279     .write =    pcic_write_config,
0280 };
0281
0282 /*
0283  * On sparc64 pcibios_init() calls pci_controller_probe().
0284  * We want PCIC probed little ahead so that interrupt controller
0285  * would be operational.
0286  */
0287 int __init pcic_probe(void)
0288 {
0289     struct linux_pcic *pcic;
0290     struct linux_prom_registers regs[PROMREG_MAX];
0291     struct linux_pbm_info* pbm;
0292     char namebuf[64];
0293     phandle node;
0294     int err;
0295
0296     if (pcic0_up) {
0297         prom_printf("PCIC: called twice!\n");
0298         prom_halt();
0299     }
0300     pcic = &pcic0;
0301
0302     node = prom_getchild (prom_root_node);
0303     node = prom_searchsiblings (node, "pci");
0304     if (node == 0)
0305         return -ENODEV;
0306     /*
0307      * Map in PCIC register set, config space, and IO base
0308      */
0309     err = prom_getproperty(node, "reg", (char*)regs, sizeof(regs));
0310     if (err == 0 || err == -1) {
0311         prom_printf("PCIC: Error, cannot get PCIC registers "
0312                 "from PROM.\n");
0313         prom_halt();
0314     }
0315
0316     pcic0_up = 1;
0317
0318     pcic->pcic_res_regs.name = "pcic_registers";
0319     pcic->pcic_regs = ioremap(regs[0].phys_addr, regs[0].reg_size);
0320     if (!pcic->pcic_regs) {
0321         prom_printf("PCIC: Error, cannot map PCIC registers.\n");
0322         prom_halt();
0323     }
0324
0325     pcic->pcic_res_io.name = "pcic_io";
0326     if ((pcic->pcic_io = (unsigned long)
0327         ioremap(regs[1].phys_addr, 0x10000)) == 0) {
0328         prom_printf("PCIC: Error, cannot map PCIC IO Base.\n");
0329         prom_halt();
0330     }
0331
0332     pcic->pcic_res_cfg_addr.name = "pcic_cfg_addr";
0333     if ((pcic->pcic_config_space_addr =
0334         ioremap(regs[2].phys_addr, regs[2].reg_size * 2)) == NULL) {
0335         prom_printf("PCIC: Error, cannot map "
0336                 "PCI Configuration Space Address.\n");
0337         prom_halt();
0338     }
0339
0340     /*
0341      * Docs say three least significant bits in address and data
0342      * must be the same. Thus, we need adjust size of data.
0343      */
0344     pcic->pcic_res_cfg_data.name = "pcic_cfg_data";
0345     if ((pcic->pcic_config_space_data =
0346         ioremap(regs[3].phys_addr, regs[3].reg_size * 2)) == NULL) {
0347         prom_printf("PCIC: Error, cannot map "
0348                 "PCI Configuration Space Data.\n");
0349         prom_halt();
0350     }
0351
0352     pbm = &pcic->pbm;
0353     pbm->prom_node = node;
0354     prom_getstring(node, "name", namebuf, 63);  namebuf[63] = 0;
0355     strcpy(pbm->prom_name, namebuf);
0356
0357     {
0358         extern int pcic_nmi_trap_patch[4];
0359
0360         t_nmi[0] = pcic_nmi_trap_patch[0];
0361         t_nmi[1] = pcic_nmi_trap_patch[1];
0362         t_nmi[2] = pcic_nmi_trap_patch[2];
0363         t_nmi[3] = pcic_nmi_trap_patch[3];
0364         swift_flush_dcache();
0365         pcic_regs = pcic->pcic_regs;
0366     }
0367
0368     prom_getstring(prom_root_node, "name", namebuf, 63);  namebuf[63] = 0;
0369     {
0370         struct pcic_sn2list *p;
0371
0372         for (p = pcic_known_sysnames; p->sysname != NULL; p++) {
0373             if (strcmp(namebuf, p->sysname) == 0)
0374                 break;
0375         }
0376         pcic->pcic_imap = p->intmap;
0377         pcic->pcic_imdim = p->mapdim;
0378     }
0379     if (pcic->pcic_imap == NULL) {
0380         /*
0381          * We do not panic here for the sake of embedded systems.
0382          */
0383         printk("PCIC: System %s is unknown, cannot route interrupts\n",
0384             namebuf);
0385     }
0386
0387     return 0;
0388 }
0389
0390 static void __init pcic_pbm_scan_bus(struct linux_pcic *pcic)
0391 {
0392     struct linux_pbm_info *pbm = &pcic->pbm;
0393
0394     pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, &pcic_ops, pbm);
0395     if (!pbm->pci_bus)
0396         return;
0397
0398 #if 0 /* deadwood transplanted from sparc64 */
0399     pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
0400     pci_record_assignments(pbm, pbm->pci_bus);
0401     pci_assign_unassigned(pbm, pbm->pci_bus);
0402     pci_fixup_irq(pbm, pbm->pci_bus);
0403 #endif
0404     pci_bus_add_devices(pbm->pci_bus);
0405 }
0406
0407 /*
0408  * Main entry point from the PCI subsystem.
0409  */
0410 static int __init pcic_init(void)
0411 {
0412     struct linux_pcic *pcic;
0413
0414     /*
0415      * PCIC should be initialized at start of the timer.
0416      * So, here we report the presence of PCIC and do some magic passes.
0417      */
0418     if(!pcic0_up)
0419         return 0;
0420     pcic = &pcic0;
0421
0422     /*
0423      *      Switch off IOTLB translation.
0424      */
0425     writeb(PCI_DVMA_CONTROL_IOTLB_DISABLE,
0426            pcic->pcic_regs+PCI_DVMA_CONTROL);
0427
0428     /*
0429      *      Increase mapped size for PCI memory space (DMA access).
0430      *      Should be done in that order (size first, address second).
0431      *      Why we couldn't set up 4GB and forget about it? XXX
0432      */
0433     writel(0xF0000000UL, pcic->pcic_regs+PCI_SIZE_0);
0434     writel(0+PCI_BASE_ADDRESS_SPACE_MEMORY,
0435            pcic->pcic_regs+PCI_BASE_ADDRESS_0);
0436
0437     pcic_pbm_scan_bus(pcic);
0438
0439     return 0;
0440 }
0441
0442 int pcic_present(void)
0443 {
0444     return pcic0_up;
0445 }
0446
0447 static int pdev_to_pnode(struct linux_pbm_info *pbm, struct pci_dev *pdev)
0448 {
0449     struct linux_prom_pci_registers regs[PROMREG_MAX];
0450     int err;
0451     phandle node = prom_getchild(pbm->prom_node);
0452
0453     while(node) {
0454         err = prom_getproperty(node, "reg",
0455                        (char *)&regs[0], sizeof(regs));
0456         if(err != 0 && err != -1) {
0457             unsigned long devfn = (regs[0].which_io >> 8) & 0xff;
0458             if(devfn == pdev->devfn)
0459                 return node;
0460         }
0461         node = prom_getsibling(node);
0462     }
0463     return 0;
0464 }
0465
0466 static inline struct pcidev_cookie *pci_devcookie_alloc(void)
0467 {
0468     return kmalloc(sizeof(struct pcidev_cookie), GFP_ATOMIC);
0469 }
0470
0471 static void pcic_map_pci_device(struct linux_pcic *pcic,
0472     struct pci_dev *dev, int node)
0473 {
0474     char namebuf[64];
0475     unsigned long address;
0476     unsigned long flags;
0477     int j;
0478
0479     if (node == 0 || node == -1) {
0480         strcpy(namebuf, "???");
0481     } else {
0482         prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
0483     }
0484
0485     for (j = 0; j < 6; j++) {
0486         address = dev->resource[j].start;
0487         if (address == 0) break;    /* are sequential */
0488         flags = dev->resource[j].flags;
0489         if ((flags & IORESOURCE_IO) != 0) {
0490             if (address < 0x10000) {
0491                 /*
0492                  * A device responds to I/O cycles on PCI.
0493                  * We generate these cycles with memory
0494                  * access into the fixed map (phys 0x30000000).
0495                  *
0496                  * Since a device driver does not want to
0497                  * do ioremap() before accessing PC-style I/O,
0498                  * we supply virtual, ready to access address.
0499                  *
0500                  * Note that request_region()
0501                  * works for these devices.
0502                  *
0503                  * XXX Neat trick, but it's a *bad* idea
0504                  * to shit into regions like that.
0505                  * What if we want to allocate one more
0506                  * PCI base address...
0507                  */
0508                 dev->resource[j].start =
0509                     pcic->pcic_io + address;
0510                 dev->resource[j].end = 1;  /* XXX */
0511                 dev->resource[j].flags =
0512                     (flags & ~IORESOURCE_IO) | IORESOURCE_MEM;
0513             } else {
0514                 /*
0515                  * OOPS... PCI Spec allows this. Sun does
0516                  * not have any devices getting above 64K
0517                  * so it must be user with a weird I/O
0518                  * board in a PCI slot. We must remap it
0519                  * under 64K but it is not done yet. XXX
0520                  */
0521                 pci_info(dev, "PCIC: Skipping I/O space at "
0522                      "0x%lx, this will Oops if a driver "
0523                      "attaches device '%s'\n", address,
0524                      namebuf);
0525             }
0526         }
0527     }
0528 }
0529
0530 static void
0531 pcic_fill_irq(struct linux_pcic *pcic, struct pci_dev *dev, int node)
0532 {
0533     struct pcic_ca2irq *p;
0534     unsigned int real_irq;
0535     int i, ivec;
0536     char namebuf[64];
0537
0538     if (node == 0 || node == -1) {
0539         strcpy(namebuf, "???");
0540     } else {
0541         prom_getstring(node, "name", namebuf, sizeof(namebuf));
0542     }
0543
0544     if ((p = pcic->pcic_imap) == NULL) {
0545         dev->irq = 0;
0546         return;
0547     }
0548     for (i = 0; i < pcic->pcic_imdim; i++) {
0549         if (p->busno == dev->bus->number && p->devfn == dev->devfn)
0550             break;
0551         p++;
0552     }
0553     if (i >= pcic->pcic_imdim) {
0554         pci_info(dev, "PCIC: device %s not found in %d\n", namebuf,
0555              pcic->pcic_imdim);
0556         dev->irq = 0;
0557         return;
0558     }
0559
0560     i = p->pin;
0561     if (i >= 0 && i < 4) {
0562         ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
0563         real_irq = ivec >> (i << 2) & 0xF;
0564     } else if (i >= 4 && i < 8) {
0565         ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
0566         real_irq = ivec >> ((i-4) << 2) & 0xF;
0567     } else {                    /* Corrupted map */
0568         pci_info(dev, "PCIC: BAD PIN %d\n", i); for (;;) {}
0569     }
0570 /* P3 */ /* printk("PCIC: device %s pin %d ivec 0x%x irq %x\n", namebuf, i, ivec, dev->irq); */
0571
0572     /* real_irq means PROM did not bother to program the upper
0573      * half of PCIC. This happens on JS-E with PROM 3.11, for instance.
0574      */
0575     if (real_irq == 0 || p->force) {
0576         if (p->irq == 0 || p->irq >= 15) {  /* Corrupted map */
0577             pci_info(dev, "PCIC: BAD IRQ %d\n", p->irq); for (;;) {}
0578         }
0579         pci_info(dev, "PCIC: setting irq %d at pin %d\n", p->irq,
0580              p->pin);
0581         real_irq = p->irq;
0582
0583         i = p->pin;
0584         if (i >= 4) {
0585             ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
0586             ivec &= ~(0xF << ((i - 4) << 2));
0587             ivec |= p->irq << ((i - 4) << 2);
0588             writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_HI);
0589         } else {
0590             ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
0591             ivec &= ~(0xF << (i << 2));
0592             ivec |= p->irq << (i << 2);
0593             writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_LO);
0594         }
0595     }
0596     dev->irq = pcic_build_device_irq(NULL, real_irq);
0597 }
0598
0599 /*
0600  * Normally called from {do_}pci_scan_bus...
0601  */
0602 void pcibios_fixup_bus(struct pci_bus *bus)
0603 {
0604     struct pci_dev *dev;
0605     struct linux_pcic *pcic;
0606     /* struct linux_pbm_info* pbm = &pcic->pbm; */
0607     int node;
0608     struct pcidev_cookie *pcp;
0609
0610     if (!pcic0_up) {
0611         pci_info(bus, "pcibios_fixup_bus: no PCIC\n");
0612         return;
0613     }
0614     pcic = &pcic0;
0615
0616     /*
0617      * Next crud is an equivalent of pbm = pcic_bus_to_pbm(bus);
0618      */
0619     if (bus->number != 0) {
0620         pci_info(bus, "pcibios_fixup_bus: nonzero bus 0x%x\n",
0621              bus->number);
0622         return;
0623     }
0624
0625     list_for_each_entry(dev, &bus->devices, bus_list) {
0626         node = pdev_to_pnode(&pcic->pbm, dev);
0627         if(node == 0)
0628             node = -1;
0629
0630         /* cookies */
0631         pcp = pci_devcookie_alloc();
0632         pcp->pbm = &pcic->pbm;
0633         pcp->prom_node = of_find_node_by_phandle(node);
0634         dev->sysdata = pcp;
0635
0636         /* fixing I/O to look like memory */
0637         if ((dev->class>>16) != PCI_BASE_CLASS_BRIDGE)
0638             pcic_map_pci_device(pcic, dev, node);
0639
0640         pcic_fill_irq(pcic, dev, node);
0641     }
0642 }
0643
0644 int pcibios_enable_device(struct pci_dev *dev, int mask)
0645 {
0646     u16 cmd, oldcmd;
0647     int i;
0648
0649     pci_read_config_word(dev, PCI_COMMAND, &cmd);
0650     oldcmd = cmd;
0651
0652     for (i = 0; i < PCI_NUM_RESOURCES; i++) {
0653         struct resource *res = &dev->resource[i];
0654
0655         /* Only set up the requested stuff */
0656         if (!(mask & (1<<i)))
0657             continue;
0658
0659         if (res->flags & IORESOURCE_IO)
0660             cmd |= PCI_COMMAND_IO;
0661         if (res->flags & IORESOURCE_MEM)
0662             cmd |= PCI_COMMAND_MEMORY;
0663     }
0664
0665     if (cmd != oldcmd) {
0666         pci_info(dev, "enabling device (%04x -> %04x)\n", oldcmd, cmd);
0667         pci_write_config_word(dev, PCI_COMMAND, cmd);
0668     }
0669     return 0;
0670 }
0671
0672 /* Makes compiler happy */
0673 static volatile int pcic_timer_dummy;
0674
0675 static void pcic_clear_clock_irq(void)
0676 {
0677     pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT);
0678 }
0679
0680 /* CPU frequency is 100 MHz, timer increments every 4 CPU clocks */
0681 #define USECS_PER_JIFFY  (1000000 / HZ)
0682 #define TICK_TIMER_LIMIT ((100 * 1000000 / 4) / HZ)
0683
0684 static unsigned int pcic_cycles_offset(void)
0685 {
0686     u32 value, count;
0687
0688     value = readl(pcic0.pcic_regs + PCI_SYS_COUNTER);
0689     count = value & ~PCI_SYS_COUNTER_OVERFLOW;
0690
0691     if (value & PCI_SYS_COUNTER_OVERFLOW)
0692         count += TICK_TIMER_LIMIT;
0693     /*
0694      * We divide all by HZ
0695      * to have microsecond resolution and to avoid overflow
0696      */
0697     count = ((count / HZ) * USECS_PER_JIFFY) / (TICK_TIMER_LIMIT / HZ);
0698
0699     /* Coordinate with the sparc_config.clock_rate setting */
0700     return count * 2;
0701 }
0702
0703 void __init pci_time_init(void)
0704 {
0705     struct linux_pcic *pcic = &pcic0;
0706     unsigned long v;
0707     int timer_irq, irq;
0708     int err;
0709
0710 #ifndef CONFIG_SMP
0711     /*
0712      * The clock_rate is in SBUS dimension.
0713      * We take into account this in pcic_cycles_offset()
0714      */
0715     sparc_config.clock_rate = SBUS_CLOCK_RATE / HZ;
0716     sparc_config.features |= FEAT_L10_CLOCKEVENT;
0717 #endif
0718     sparc_config.features |= FEAT_L10_CLOCKSOURCE;
0719     sparc_config.get_cycles_offset = pcic_cycles_offset;
0720
0721     writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT);
0722     /* PROM should set appropriate irq */
0723     v = readb(pcic->pcic_regs+PCI_COUNTER_IRQ);
0724     timer_irq = PCI_COUNTER_IRQ_SYS(v);
0725     writel (PCI_COUNTER_IRQ_SET(timer_irq, 0),
0726         pcic->pcic_regs+PCI_COUNTER_IRQ);
0727     irq = pcic_build_device_irq(NULL, timer_irq);
0728     err = request_irq(irq, timer_interrupt,
0729               IRQF_TIMER, "timer", NULL);
0730     if (err) {
0731         prom_printf("time_init: unable to attach IRQ%d\n", timer_irq);
0732         prom_halt();
0733     }
0734     local_irq_enable();
0735 }
0736
0737
0738 #if 0
0739 static void watchdog_reset() {
0740     writeb(0, pcic->pcic_regs+PCI_SYS_STATUS);
0741 }
0742 #endif
0743
0744 /*
0745  * NMI
0746  */
0747 void pcic_nmi(unsigned int pend, struct pt_regs *regs)
0748 {
0749     pend = swab32(pend);
0750
0751     if (!pcic_speculative || (pend & PCI_SYS_INT_PENDING_PIO) == 0) {
0752         /*
0753          * XXX On CP-1200 PCI #SERR may happen, we do not know
0754          * what to do about it yet.
0755          */
0756         printk("Aiee, NMI pend 0x%x pc 0x%x spec %d, hanging\n",
0757             pend, (int)regs->pc, pcic_speculative);
0758         for (;;) { }
0759     }
0760     pcic_speculative = 0;
0761     pcic_trapped = 1;
0762     regs->pc = regs->npc;
0763     regs->npc += 4;
0764 }
0765
0766 static inline unsigned long get_irqmask(int irq_nr)
0767 {
0768     return 1 << irq_nr;
0769 }
0770
0771 static void pcic_mask_irq(struct irq_data *data)
0772 {
0773     unsigned long mask, flags;
0774
0775     mask = (unsigned long)data->chip_data;
0776     local_irq_save(flags);
0777     writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET);
0778     local_irq_restore(flags);
0779 }
0780
0781 static void pcic_unmask_irq(struct irq_data *data)
0782 {
0783     unsigned long mask, flags;
0784
0785     mask = (unsigned long)data->chip_data;
0786     local_irq_save(flags);
0787     writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR);
0788     local_irq_restore(flags);
0789 }
0790
0791 static unsigned int pcic_startup_irq(struct irq_data *data)
0792 {
0793     irq_link(data->irq);
0794     pcic_unmask_irq(data);
0795     return 0;
0796 }
0797
0798 static struct irq_chip pcic_irq = {
0799     .name       = "pcic",
0800     .irq_startup    = pcic_startup_irq,
0801     .irq_mask   = pcic_mask_irq,
0802     .irq_unmask = pcic_unmask_irq,
0803 };
0804
0805 unsigned int pcic_build_device_irq(struct platform_device *op,
0806                                    unsigned int real_irq)
0807 {
0808     unsigned int irq;
0809     unsigned long mask;
0810
0811     irq = 0;
0812     mask = get_irqmask(real_irq);
0813     if (mask == 0)
0814         goto out;
0815
0816     irq = irq_alloc(real_irq, real_irq);
0817     if (irq == 0)
0818         goto out;
0819
0820     irq_set_chip_and_handler_name(irq, &pcic_irq,
0821                                   handle_level_irq, "PCIC");
0822     irq_set_chip_data(irq, (void *)mask);
0823
0824 out:
0825     return irq;
0826 }
0827
0828
0829 static void pcic_load_profile_irq(int cpu, unsigned int limit)
0830 {
0831     printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__);
0832 }
0833
0834 void __init sun4m_pci_init_IRQ(void)
0835 {
0836     sparc_config.build_device_irq = pcic_build_device_irq;
0837     sparc_config.clear_clock_irq  = pcic_clear_clock_irq;
0838     sparc_config.load_profile_irq = pcic_load_profile_irq;
0839 }
0840
0841 subsys_initcall(pcic_init);