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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support.
0003  *
0004  * Copyright (C) 2001, 2002, 2003, 2007, 2008 David S. Miller (davem@davemloft.net)
0005  */
0006 
0007 #include <linux/kernel.h>
0008 #include <linux/types.h>
0009 #include <linux/pci.h>
0010 #include <linux/init.h>
0011 #include <linux/slab.h>
0012 #include <linux/export.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/of_device.h>
0015 #include <linux/numa.h>
0016 
0017 #include <asm/iommu.h>
0018 #include <asm/irq.h>
0019 #include <asm/pstate.h>
0020 #include <asm/prom.h>
0021 #include <asm/upa.h>
0022 
0023 #include "pci_impl.h"
0024 #include "iommu_common.h"
0025 
0026 #define DRIVER_NAME "schizo"
0027 #define PFX     DRIVER_NAME ": "
0028 
0029 /* This is a convention that at least Excalibur and Merlin
0030  * follow.  I suppose the SCHIZO used in Starcat and friends
0031  * will do similar.
0032  *
0033  * The only way I could see this changing is if the newlink
0034  * block requires more space in Schizo's address space than
0035  * they predicted, thus requiring an address space reorg when
0036  * the newer Schizo is taped out.
0037  */
0038 
0039 /* Streaming buffer control register. */
0040 #define SCHIZO_STRBUF_CTRL_LPTR    0x00000000000000f0UL /* LRU Lock Pointer */
0041 #define SCHIZO_STRBUF_CTRL_LENAB   0x0000000000000008UL /* LRU Lock Enable */
0042 #define SCHIZO_STRBUF_CTRL_RRDIS   0x0000000000000004UL /* Rerun Disable */
0043 #define SCHIZO_STRBUF_CTRL_DENAB   0x0000000000000002UL /* Diagnostic Mode Enable */
0044 #define SCHIZO_STRBUF_CTRL_ENAB    0x0000000000000001UL /* Streaming Buffer Enable */
0045 
0046 /* IOMMU control register. */
0047 #define SCHIZO_IOMMU_CTRL_RESV     0xfffffffff9000000UL /* Reserved                      */
0048 #define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status      */
0049 #define SCHIZO_IOMMU_CTRL_XLTEERR  0x0000000001000000UL /* Translation Error encountered */
0050 #define SCHIZO_IOMMU_CTRL_LCKEN    0x0000000000800000UL /* Enable translation locking    */
0051 #define SCHIZO_IOMMU_CTRL_LCKPTR   0x0000000000780000UL /* Translation lock pointer      */
0052 #define SCHIZO_IOMMU_CTRL_TSBSZ    0x0000000000070000UL /* TSB Size                      */
0053 #define SCHIZO_IOMMU_TSBSZ_1K      0x0000000000000000UL /* TSB Table 1024 8-byte entries */
0054 #define SCHIZO_IOMMU_TSBSZ_2K      0x0000000000010000UL /* TSB Table 2048 8-byte entries */
0055 #define SCHIZO_IOMMU_TSBSZ_4K      0x0000000000020000UL /* TSB Table 4096 8-byte entries */
0056 #define SCHIZO_IOMMU_TSBSZ_8K      0x0000000000030000UL /* TSB Table 8192 8-byte entries */
0057 #define SCHIZO_IOMMU_TSBSZ_16K     0x0000000000040000UL /* TSB Table 16k 8-byte entries  */
0058 #define SCHIZO_IOMMU_TSBSZ_32K     0x0000000000050000UL /* TSB Table 32k 8-byte entries  */
0059 #define SCHIZO_IOMMU_TSBSZ_64K     0x0000000000060000UL /* TSB Table 64k 8-byte entries  */
0060 #define SCHIZO_IOMMU_TSBSZ_128K    0x0000000000070000UL /* TSB Table 128k 8-byte entries */
0061 #define SCHIZO_IOMMU_CTRL_RESV2    0x000000000000fff8UL /* Reserved                      */
0062 #define SCHIZO_IOMMU_CTRL_TBWSZ    0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
0063 #define SCHIZO_IOMMU_CTRL_DENAB    0x0000000000000002UL /* Diagnostic mode enable        */
0064 #define SCHIZO_IOMMU_CTRL_ENAB     0x0000000000000001UL /* IOMMU Enable                  */
0065 
0066 /* Schizo config space address format is nearly identical to
0067  * that of PSYCHO:
0068  *
0069  *  32             24 23 16 15    11 10       8 7   2  1 0
0070  * ---------------------------------------------------------
0071  * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 |
0072  * ---------------------------------------------------------
0073  */
0074 #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space)
0075 #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG)   \
0076     (((unsigned long)(BUS)   << 16) |   \
0077      ((unsigned long)(DEVFN) << 8)  |   \
0078      ((unsigned long)(REG)))
0079 
0080 static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm,
0081                       unsigned char bus,
0082                       unsigned int devfn,
0083                       int where)
0084 {
0085     if (!pbm)
0086         return NULL;
0087     bus -= pbm->pci_first_busno;
0088     return (void *)
0089         (SCHIZO_CONFIG_BASE(pbm) |
0090          SCHIZO_CONFIG_ENCODE(bus, devfn, where));
0091 }
0092 
0093 /* SCHIZO error handling support. */
0094 enum schizo_error_type {
0095     UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
0096 };
0097 
0098 static DEFINE_SPINLOCK(stc_buf_lock);
0099 static unsigned long stc_error_buf[128];
0100 static unsigned long stc_tag_buf[16];
0101 static unsigned long stc_line_buf[16];
0102 
0103 #define SCHIZO_UE_INO       0x30 /* Uncorrectable ECC error */
0104 #define SCHIZO_CE_INO       0x31 /* Correctable ECC error */
0105 #define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */
0106 #define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */
0107 #define SCHIZO_SERR_INO     0x34 /* Safari interface error */
0108 
0109 #define SCHIZO_STC_ERR  0xb800UL /* --> 0xba00 */
0110 #define SCHIZO_STC_TAG  0xba00UL /* --> 0xba80 */
0111 #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */
0112 
0113 #define SCHIZO_STCERR_WRITE 0x2UL
0114 #define SCHIZO_STCERR_READ  0x1UL
0115 
0116 #define SCHIZO_STCTAG_PPN   0x3fffffff00000000UL
0117 #define SCHIZO_STCTAG_VPN   0x00000000ffffe000UL
0118 #define SCHIZO_STCTAG_VALID 0x8000000000000000UL
0119 #define SCHIZO_STCTAG_READ  0x4000000000000000UL
0120 
0121 #define SCHIZO_STCLINE_LINDX    0x0000000007800000UL
0122 #define SCHIZO_STCLINE_SPTR 0x000000000007e000UL
0123 #define SCHIZO_STCLINE_LADDR    0x0000000000001fc0UL
0124 #define SCHIZO_STCLINE_EPTR 0x000000000000003fUL
0125 #define SCHIZO_STCLINE_VALID    0x0000000000600000UL
0126 #define SCHIZO_STCLINE_FOFN 0x0000000000180000UL
0127 
0128 static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
0129                      enum schizo_error_type type)
0130 {
0131     struct strbuf *strbuf = &pbm->stc;
0132     unsigned long regbase = pbm->pbm_regs;
0133     unsigned long err_base, tag_base, line_base;
0134     u64 control;
0135     int i;
0136 
0137     err_base = regbase + SCHIZO_STC_ERR;
0138     tag_base = regbase + SCHIZO_STC_TAG;
0139     line_base = regbase + SCHIZO_STC_LINE;
0140 
0141     spin_lock(&stc_buf_lock);
0142 
0143     /* This is __REALLY__ dangerous.  When we put the
0144      * streaming buffer into diagnostic mode to probe
0145      * it's tags and error status, we _must_ clear all
0146      * of the line tag valid bits before re-enabling
0147      * the streaming buffer.  If any dirty data lives
0148      * in the STC when we do this, we will end up
0149      * invalidating it before it has a chance to reach
0150      * main memory.
0151      */
0152     control = upa_readq(strbuf->strbuf_control);
0153     upa_writeq((control | SCHIZO_STRBUF_CTRL_DENAB),
0154            strbuf->strbuf_control);
0155     for (i = 0; i < 128; i++) {
0156         unsigned long val;
0157 
0158         val = upa_readq(err_base + (i * 8UL));
0159         upa_writeq(0UL, err_base + (i * 8UL));
0160         stc_error_buf[i] = val;
0161     }
0162     for (i = 0; i < 16; i++) {
0163         stc_tag_buf[i] = upa_readq(tag_base + (i * 8UL));
0164         stc_line_buf[i] = upa_readq(line_base + (i * 8UL));
0165         upa_writeq(0UL, tag_base + (i * 8UL));
0166         upa_writeq(0UL, line_base + (i * 8UL));
0167     }
0168 
0169     /* OK, state is logged, exit diagnostic mode. */
0170     upa_writeq(control, strbuf->strbuf_control);
0171 
0172     for (i = 0; i < 16; i++) {
0173         int j, saw_error, first, last;
0174 
0175         saw_error = 0;
0176         first = i * 8;
0177         last = first + 8;
0178         for (j = first; j < last; j++) {
0179             unsigned long errval = stc_error_buf[j];
0180             if (errval != 0) {
0181                 saw_error++;
0182                 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
0183                        pbm->name,
0184                        j,
0185                        (errval & SCHIZO_STCERR_WRITE) ? 1 : 0,
0186                        (errval & SCHIZO_STCERR_READ) ? 1 : 0);
0187             }
0188         }
0189         if (saw_error != 0) {
0190             unsigned long tagval = stc_tag_buf[i];
0191             unsigned long lineval = stc_line_buf[i];
0192             printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n",
0193                    pbm->name,
0194                    i,
0195                    ((tagval & SCHIZO_STCTAG_PPN) >> 19UL),
0196                    (tagval & SCHIZO_STCTAG_VPN),
0197                    ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0),
0198                    ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0));
0199 
0200             /* XXX Should spit out per-bank error information... -DaveM */
0201             printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
0202                    "V(%d)FOFN(%d)]\n",
0203                    pbm->name,
0204                    i,
0205                    ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL),
0206                    ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL),
0207                    ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL),
0208                    ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL),
0209                    ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0),
0210                    ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0));
0211         }
0212     }
0213 
0214     spin_unlock(&stc_buf_lock);
0215 }
0216 
0217 /* IOMMU is per-PBM in Schizo, so interrogate both for anonymous
0218  * controller level errors.
0219  */
0220 
0221 #define SCHIZO_IOMMU_TAG    0xa580UL
0222 #define SCHIZO_IOMMU_DATA   0xa600UL
0223 
0224 #define SCHIZO_IOMMU_TAG_CTXT   0x0000001ffe000000UL
0225 #define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL
0226 #define SCHIZO_IOMMU_TAG_ERR    0x0000000000400000UL
0227 #define SCHIZO_IOMMU_TAG_WRITE  0x0000000000200000UL
0228 #define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL
0229 #define SCHIZO_IOMMU_TAG_SIZE   0x0000000000080000UL
0230 #define SCHIZO_IOMMU_TAG_VPAGE  0x000000000007ffffUL
0231 
0232 #define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL
0233 #define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL
0234 #define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL
0235 
0236 static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
0237                      enum schizo_error_type type)
0238 {
0239     struct iommu *iommu = pbm->iommu;
0240     unsigned long iommu_tag[16];
0241     unsigned long iommu_data[16];
0242     unsigned long flags;
0243     u64 control;
0244     int i;
0245 
0246     spin_lock_irqsave(&iommu->lock, flags);
0247     control = upa_readq(iommu->iommu_control);
0248     if (control & SCHIZO_IOMMU_CTRL_XLTEERR) {
0249         unsigned long base;
0250         char *type_string;
0251 
0252         /* Clear the error encountered bit. */
0253         control &= ~SCHIZO_IOMMU_CTRL_XLTEERR;
0254         upa_writeq(control, iommu->iommu_control);
0255 
0256         switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
0257         case 0:
0258             type_string = "Protection Error";
0259             break;
0260         case 1:
0261             type_string = "Invalid Error";
0262             break;
0263         case 2:
0264             type_string = "TimeOut Error";
0265             break;
0266         case 3:
0267         default:
0268             type_string = "ECC Error";
0269             break;
0270         }
0271         printk("%s: IOMMU Error, type[%s]\n",
0272                pbm->name, type_string);
0273 
0274         /* Put the IOMMU into diagnostic mode and probe
0275          * it's TLB for entries with error status.
0276          *
0277          * It is very possible for another DVMA to occur
0278          * while we do this probe, and corrupt the system
0279          * further.  But we are so screwed at this point
0280          * that we are likely to crash hard anyways, so
0281          * get as much diagnostic information to the
0282          * console as we can.
0283          */
0284         upa_writeq(control | SCHIZO_IOMMU_CTRL_DENAB,
0285                iommu->iommu_control);
0286 
0287         base = pbm->pbm_regs;
0288 
0289         for (i = 0; i < 16; i++) {
0290             iommu_tag[i] =
0291                 upa_readq(base + SCHIZO_IOMMU_TAG + (i * 8UL));
0292             iommu_data[i] =
0293                 upa_readq(base + SCHIZO_IOMMU_DATA + (i * 8UL));
0294 
0295             /* Now clear out the entry. */
0296             upa_writeq(0, base + SCHIZO_IOMMU_TAG + (i * 8UL));
0297             upa_writeq(0, base + SCHIZO_IOMMU_DATA + (i * 8UL));
0298         }
0299 
0300         /* Leave diagnostic mode. */
0301         upa_writeq(control, iommu->iommu_control);
0302 
0303         for (i = 0; i < 16; i++) {
0304             unsigned long tag, data;
0305 
0306             tag = iommu_tag[i];
0307             if (!(tag & SCHIZO_IOMMU_TAG_ERR))
0308                 continue;
0309 
0310             data = iommu_data[i];
0311             switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) {
0312             case 0:
0313                 type_string = "Protection Error";
0314                 break;
0315             case 1:
0316                 type_string = "Invalid Error";
0317                 break;
0318             case 2:
0319                 type_string = "TimeOut Error";
0320                 break;
0321             case 3:
0322             default:
0323                 type_string = "ECC Error";
0324                 break;
0325             }
0326             printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) "
0327                    "sz(%dK) vpg(%08lx)]\n",
0328                    pbm->name, i, type_string,
0329                    (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL),
0330                    ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0),
0331                    ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0),
0332                    ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8),
0333                    (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
0334             printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
0335                    pbm->name, i,
0336                    ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0),
0337                    ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0),
0338                    (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
0339         }
0340     }
0341     if (pbm->stc.strbuf_enabled)
0342         __schizo_check_stc_error_pbm(pbm, type);
0343     spin_unlock_irqrestore(&iommu->lock, flags);
0344 }
0345 
0346 static void schizo_check_iommu_error(struct pci_pbm_info *pbm,
0347                      enum schizo_error_type type)
0348 {
0349     schizo_check_iommu_error_pbm(pbm, type);
0350     if (pbm->sibling)
0351         schizo_check_iommu_error_pbm(pbm->sibling, type);
0352 }
0353 
0354 /* Uncorrectable ECC error status gathering. */
0355 #define SCHIZO_UE_AFSR  0x10030UL
0356 #define SCHIZO_UE_AFAR  0x10038UL
0357 
0358 #define SCHIZO_UEAFSR_PPIO  0x8000000000000000UL /* Safari */
0359 #define SCHIZO_UEAFSR_PDRD  0x4000000000000000UL /* Safari/Tomatillo */
0360 #define SCHIZO_UEAFSR_PDWR  0x2000000000000000UL /* Safari */
0361 #define SCHIZO_UEAFSR_SPIO  0x1000000000000000UL /* Safari */
0362 #define SCHIZO_UEAFSR_SDMA  0x0800000000000000UL /* Safari/Tomatillo */
0363 #define SCHIZO_UEAFSR_ERRPNDG   0x0300000000000000UL /* Safari */
0364 #define SCHIZO_UEAFSR_BMSK  0x000003ff00000000UL /* Safari */
0365 #define SCHIZO_UEAFSR_QOFF  0x00000000c0000000UL /* Safari/Tomatillo */
0366 #define SCHIZO_UEAFSR_AID   0x000000001f000000UL /* Safari/Tomatillo */
0367 #define SCHIZO_UEAFSR_PARTIAL   0x0000000000800000UL /* Safari */
0368 #define SCHIZO_UEAFSR_OWNEDIN   0x0000000000400000UL /* Safari */
0369 #define SCHIZO_UEAFSR_MTAGSYND  0x00000000000f0000UL /* Safari */
0370 #define SCHIZO_UEAFSR_MTAG  0x000000000000e000UL /* Safari */
0371 #define SCHIZO_UEAFSR_ECCSYND   0x00000000000001ffUL /* Safari */
0372 
0373 static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
0374 {
0375     struct pci_pbm_info *pbm = dev_id;
0376     unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR;
0377     unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR;
0378     unsigned long afsr, afar, error_bits;
0379     int reported, limit;
0380 
0381     /* Latch uncorrectable error status. */
0382     afar = upa_readq(afar_reg);
0383 
0384     /* If either of the error pending bits are set in the
0385      * AFSR, the error status is being actively updated by
0386      * the hardware and we must re-read to get a clean value.
0387      */
0388     limit = 1000;
0389     do {
0390         afsr = upa_readq(afsr_reg);
0391     } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
0392 
0393     /* Clear the primary/secondary error status bits. */
0394     error_bits = afsr &
0395         (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR |
0396          SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA);
0397     if (!error_bits)
0398         return IRQ_NONE;
0399     upa_writeq(error_bits, afsr_reg);
0400 
0401     /* Log the error. */
0402     printk("%s: Uncorrectable Error, primary error type[%s]\n",
0403            pbm->name,
0404            (((error_bits & SCHIZO_UEAFSR_PPIO) ?
0405          "PIO" :
0406          ((error_bits & SCHIZO_UEAFSR_PDRD) ?
0407           "DMA Read" :
0408           ((error_bits & SCHIZO_UEAFSR_PDWR) ?
0409            "DMA Write" : "???")))));
0410     printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
0411            pbm->name,
0412            (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
0413            (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
0414            (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
0415     printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
0416            pbm->name,
0417            (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
0418            (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
0419            (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
0420            (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
0421            (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
0422     printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
0423     printk("%s: UE Secondary errors [", pbm->name);
0424     reported = 0;
0425     if (afsr & SCHIZO_UEAFSR_SPIO) {
0426         reported++;
0427         printk("(PIO)");
0428     }
0429     if (afsr & SCHIZO_UEAFSR_SDMA) {
0430         reported++;
0431         printk("(DMA)");
0432     }
0433     if (!reported)
0434         printk("(none)");
0435     printk("]\n");
0436 
0437     /* Interrogate IOMMU for error status. */
0438     schizo_check_iommu_error(pbm, UE_ERR);
0439 
0440     return IRQ_HANDLED;
0441 }
0442 
0443 #define SCHIZO_CE_AFSR  0x10040UL
0444 #define SCHIZO_CE_AFAR  0x10048UL
0445 
0446 #define SCHIZO_CEAFSR_PPIO  0x8000000000000000UL
0447 #define SCHIZO_CEAFSR_PDRD  0x4000000000000000UL
0448 #define SCHIZO_CEAFSR_PDWR  0x2000000000000000UL
0449 #define SCHIZO_CEAFSR_SPIO  0x1000000000000000UL
0450 #define SCHIZO_CEAFSR_SDMA  0x0800000000000000UL
0451 #define SCHIZO_CEAFSR_ERRPNDG   0x0300000000000000UL
0452 #define SCHIZO_CEAFSR_BMSK  0x000003ff00000000UL
0453 #define SCHIZO_CEAFSR_QOFF  0x00000000c0000000UL
0454 #define SCHIZO_CEAFSR_AID   0x000000001f000000UL
0455 #define SCHIZO_CEAFSR_PARTIAL   0x0000000000800000UL
0456 #define SCHIZO_CEAFSR_OWNEDIN   0x0000000000400000UL
0457 #define SCHIZO_CEAFSR_MTAGSYND  0x00000000000f0000UL
0458 #define SCHIZO_CEAFSR_MTAG  0x000000000000e000UL
0459 #define SCHIZO_CEAFSR_ECCSYND   0x00000000000001ffUL
0460 
0461 static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
0462 {
0463     struct pci_pbm_info *pbm = dev_id;
0464     unsigned long afsr_reg = pbm->controller_regs + SCHIZO_CE_AFSR;
0465     unsigned long afar_reg = pbm->controller_regs + SCHIZO_CE_AFAR;
0466     unsigned long afsr, afar, error_bits;
0467     int reported, limit;
0468 
0469     /* Latch error status. */
0470     afar = upa_readq(afar_reg);
0471 
0472     /* If either of the error pending bits are set in the
0473      * AFSR, the error status is being actively updated by
0474      * the hardware and we must re-read to get a clean value.
0475      */
0476     limit = 1000;
0477     do {
0478         afsr = upa_readq(afsr_reg);
0479     } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
0480 
0481     /* Clear primary/secondary error status bits. */
0482     error_bits = afsr &
0483         (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR |
0484          SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA);
0485     if (!error_bits)
0486         return IRQ_NONE;
0487     upa_writeq(error_bits, afsr_reg);
0488 
0489     /* Log the error. */
0490     printk("%s: Correctable Error, primary error type[%s]\n",
0491            pbm->name,
0492            (((error_bits & SCHIZO_CEAFSR_PPIO) ?
0493          "PIO" :
0494          ((error_bits & SCHIZO_CEAFSR_PDRD) ?
0495           "DMA Read" :
0496           ((error_bits & SCHIZO_CEAFSR_PDWR) ?
0497            "DMA Write" : "???")))));
0498 
0499     /* XXX Use syndrome and afar to print out module string just like
0500      * XXX UDB CE trap handler does... -DaveM
0501      */
0502     printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
0503            pbm->name,
0504            (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
0505            (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
0506            (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
0507     printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
0508            pbm->name,
0509            (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
0510            (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
0511            (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
0512            (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
0513            (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
0514     printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
0515     printk("%s: CE Secondary errors [", pbm->name);
0516     reported = 0;
0517     if (afsr & SCHIZO_CEAFSR_SPIO) {
0518         reported++;
0519         printk("(PIO)");
0520     }
0521     if (afsr & SCHIZO_CEAFSR_SDMA) {
0522         reported++;
0523         printk("(DMA)");
0524     }
0525     if (!reported)
0526         printk("(none)");
0527     printk("]\n");
0528 
0529     return IRQ_HANDLED;
0530 }
0531 
0532 #define SCHIZO_PCI_AFSR 0x2010UL
0533 #define SCHIZO_PCI_AFAR 0x2018UL
0534 
0535 #define SCHIZO_PCIAFSR_PMA  0x8000000000000000UL /* Schizo/Tomatillo */
0536 #define SCHIZO_PCIAFSR_PTA  0x4000000000000000UL /* Schizo/Tomatillo */
0537 #define SCHIZO_PCIAFSR_PRTRY    0x2000000000000000UL /* Schizo/Tomatillo */
0538 #define SCHIZO_PCIAFSR_PPERR    0x1000000000000000UL /* Schizo/Tomatillo */
0539 #define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */
0540 #define SCHIZO_PCIAFSR_PUNUS    0x0400000000000000UL /* Schizo */
0541 #define SCHIZO_PCIAFSR_SMA  0x0200000000000000UL /* Schizo/Tomatillo */
0542 #define SCHIZO_PCIAFSR_STA  0x0100000000000000UL /* Schizo/Tomatillo */
0543 #define SCHIZO_PCIAFSR_SRTRY    0x0080000000000000UL /* Schizo/Tomatillo */
0544 #define SCHIZO_PCIAFSR_SPERR    0x0040000000000000UL /* Schizo/Tomatillo */
0545 #define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */
0546 #define SCHIZO_PCIAFSR_SUNUS    0x0010000000000000UL /* Schizo */
0547 #define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */
0548 #define SCHIZO_PCIAFSR_BLK  0x0000000080000000UL /* Schizo/Tomatillo */
0549 #define SCHIZO_PCIAFSR_CFG  0x0000000040000000UL /* Schizo/Tomatillo */
0550 #define SCHIZO_PCIAFSR_MEM  0x0000000020000000UL /* Schizo/Tomatillo */
0551 #define SCHIZO_PCIAFSR_IO   0x0000000010000000UL /* Schizo/Tomatillo */
0552 
0553 #define SCHIZO_PCI_CTRL     (0x2000UL)
0554 #define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */
0555 #define SCHIZO_PCICTRL_DTO_INT  (1UL << 61UL) /* Tomatillo */
0556 #define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */
0557 #define SCHIZO_PCICTRL_ESLCK    (1UL << 51UL) /* Safari */
0558 #define SCHIZO_PCICTRL_ERRSLOT  (7UL << 48UL) /* Safari */
0559 #define SCHIZO_PCICTRL_TTO_ERR  (1UL << 38UL) /* Safari/Tomatillo */
0560 #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */
0561 #define SCHIZO_PCICTRL_DTO_ERR  (1UL << 36UL) /* Safari/Tomatillo */
0562 #define SCHIZO_PCICTRL_SBH_ERR  (1UL << 35UL) /* Safari */
0563 #define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */
0564 #define SCHIZO_PCICTRL_PCISPD   (1UL << 33UL) /* Safari */
0565 #define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */
0566 #define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */
0567 #define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */
0568 #define SCHIZO_PCICTRL_PTO  (3UL << 24UL) /* Safari/Tomatillo */
0569 #define SCHIZO_PCICTRL_PTO_SHIFT 24UL
0570 #define SCHIZO_PCICTRL_TRWSW    (7UL << 21UL) /* Tomatillo */
0571 #define SCHIZO_PCICTRL_F_TGT_A  (1UL << 20UL) /* Tomatillo */
0572 #define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */
0573 #define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */
0574 #define SCHIZO_PCICTRL_SBH_INT  (1UL << 18UL) /* Safari */
0575 #define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */
0576 #define SCHIZO_PCICTRL_EEN  (1UL << 17UL) /* Safari/Tomatillo */
0577 #define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */
0578 #define SCHIZO_PCICTRL_PCIRST   (1UL <<  8UL) /* Safari */
0579 #define SCHIZO_PCICTRL_ARB_S    (0x3fUL << 0UL) /* Safari */
0580 #define SCHIZO_PCICTRL_ARB_T    (0xffUL << 0UL) /* Tomatillo */
0581 
0582 static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
0583 {
0584     unsigned long csr_reg, csr, csr_error_bits;
0585     irqreturn_t ret = IRQ_NONE;
0586     u32 stat;
0587 
0588     csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL;
0589     csr = upa_readq(csr_reg);
0590     csr_error_bits =
0591         csr & (SCHIZO_PCICTRL_BUS_UNUS |
0592                SCHIZO_PCICTRL_TTO_ERR |
0593                SCHIZO_PCICTRL_RTRY_ERR |
0594                SCHIZO_PCICTRL_DTO_ERR |
0595                SCHIZO_PCICTRL_SBH_ERR |
0596                SCHIZO_PCICTRL_SERR);
0597     if (csr_error_bits) {
0598         /* Clear the errors.  */
0599         upa_writeq(csr, csr_reg);
0600 
0601         /* Log 'em.  */
0602         if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS)
0603             printk("%s: Bus unusable error asserted.\n",
0604                    pbm->name);
0605         if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR)
0606             printk("%s: PCI TRDY# timeout error asserted.\n",
0607                    pbm->name);
0608         if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR)
0609             printk("%s: PCI excessive retry error asserted.\n",
0610                    pbm->name);
0611         if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR)
0612             printk("%s: PCI discard timeout error asserted.\n",
0613                    pbm->name);
0614         if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR)
0615             printk("%s: PCI streaming byte hole error asserted.\n",
0616                    pbm->name);
0617         if (csr_error_bits & SCHIZO_PCICTRL_SERR)
0618             printk("%s: PCI SERR signal asserted.\n",
0619                    pbm->name);
0620         ret = IRQ_HANDLED;
0621     }
0622     pbm->pci_ops->read(pbm->pci_bus, 0, PCI_STATUS, 2, &stat);
0623     if (stat & (PCI_STATUS_PARITY |
0624             PCI_STATUS_SIG_TARGET_ABORT |
0625             PCI_STATUS_REC_TARGET_ABORT |
0626             PCI_STATUS_REC_MASTER_ABORT |
0627             PCI_STATUS_SIG_SYSTEM_ERROR)) {
0628         printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
0629                pbm->name, stat);
0630         pbm->pci_ops->write(pbm->pci_bus, 0, PCI_STATUS, 2, 0xffff);
0631         ret = IRQ_HANDLED;
0632     }
0633     return ret;
0634 }
0635 
0636 static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
0637 {
0638     struct pci_pbm_info *pbm = dev_id;
0639     unsigned long afsr_reg, afar_reg, base;
0640     unsigned long afsr, afar, error_bits;
0641     int reported;
0642 
0643     base = pbm->pbm_regs;
0644 
0645     afsr_reg = base + SCHIZO_PCI_AFSR;
0646     afar_reg = base + SCHIZO_PCI_AFAR;
0647 
0648     /* Latch error status. */
0649     afar = upa_readq(afar_reg);
0650     afsr = upa_readq(afsr_reg);
0651 
0652     /* Clear primary/secondary error status bits. */
0653     error_bits = afsr &
0654         (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
0655          SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
0656          SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
0657          SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
0658          SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
0659          SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS);
0660     if (!error_bits)
0661         return schizo_pcierr_intr_other(pbm);
0662     upa_writeq(error_bits, afsr_reg);
0663 
0664     /* Log the error. */
0665     printk("%s: PCI Error, primary error type[%s]\n",
0666            pbm->name,
0667            (((error_bits & SCHIZO_PCIAFSR_PMA) ?
0668          "Master Abort" :
0669          ((error_bits & SCHIZO_PCIAFSR_PTA) ?
0670           "Target Abort" :
0671           ((error_bits & SCHIZO_PCIAFSR_PRTRY) ?
0672            "Excessive Retries" :
0673            ((error_bits & SCHIZO_PCIAFSR_PPERR) ?
0674             "Parity Error" :
0675             ((error_bits & SCHIZO_PCIAFSR_PTTO) ?
0676              "Timeout" :
0677              ((error_bits & SCHIZO_PCIAFSR_PUNUS) ?
0678               "Bus Unusable" : "???"))))))));
0679     printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n",
0680            pbm->name,
0681            (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL,
0682            (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0,
0683            ((afsr & SCHIZO_PCIAFSR_CFG) ?
0684         "Config" :
0685         ((afsr & SCHIZO_PCIAFSR_MEM) ?
0686          "Memory" :
0687          ((afsr & SCHIZO_PCIAFSR_IO) ?
0688           "I/O" : "???"))));
0689     printk("%s: PCI AFAR [%016lx]\n",
0690            pbm->name, afar);
0691     printk("%s: PCI Secondary errors [",
0692            pbm->name);
0693     reported = 0;
0694     if (afsr & SCHIZO_PCIAFSR_SMA) {
0695         reported++;
0696         printk("(Master Abort)");
0697     }
0698     if (afsr & SCHIZO_PCIAFSR_STA) {
0699         reported++;
0700         printk("(Target Abort)");
0701     }
0702     if (afsr & SCHIZO_PCIAFSR_SRTRY) {
0703         reported++;
0704         printk("(Excessive Retries)");
0705     }
0706     if (afsr & SCHIZO_PCIAFSR_SPERR) {
0707         reported++;
0708         printk("(Parity Error)");
0709     }
0710     if (afsr & SCHIZO_PCIAFSR_STTO) {
0711         reported++;
0712         printk("(Timeout)");
0713     }
0714     if (afsr & SCHIZO_PCIAFSR_SUNUS) {
0715         reported++;
0716         printk("(Bus Unusable)");
0717     }
0718     if (!reported)
0719         printk("(none)");
0720     printk("]\n");
0721 
0722     /* For the error types shown, scan PBM's PCI bus for devices
0723      * which have logged that error type.
0724      */
0725 
0726     /* If we see a Target Abort, this could be the result of an
0727      * IOMMU translation error of some sort.  It is extremely
0728      * useful to log this information as usually it indicates
0729      * a bug in the IOMMU support code or a PCI device driver.
0730      */
0731     if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) {
0732         schizo_check_iommu_error(pbm, PCI_ERR);
0733         pci_scan_for_target_abort(pbm, pbm->pci_bus);
0734     }
0735     if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA))
0736         pci_scan_for_master_abort(pbm, pbm->pci_bus);
0737 
0738     /* For excessive retries, PSYCHO/PBM will abort the device
0739      * and there is no way to specifically check for excessive
0740      * retries in the config space status registers.  So what
0741      * we hope is that we'll catch it via the master/target
0742      * abort events.
0743      */
0744 
0745     if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR))
0746         pci_scan_for_parity_error(pbm, pbm->pci_bus);
0747 
0748     return IRQ_HANDLED;
0749 }
0750 
0751 #define SCHIZO_SAFARI_ERRLOG    0x10018UL
0752 
0753 #define SAFARI_ERRLOG_ERROUT    0x8000000000000000UL
0754 
0755 #define BUS_ERROR_BADCMD    0x4000000000000000UL /* Schizo/Tomatillo */
0756 #define BUS_ERROR_SSMDIS    0x2000000000000000UL /* Safari */
0757 #define BUS_ERROR_BADMA     0x1000000000000000UL /* Safari */
0758 #define BUS_ERROR_BADMB     0x0800000000000000UL /* Safari */
0759 #define BUS_ERROR_BADMC     0x0400000000000000UL /* Safari */
0760 #define BUS_ERROR_SNOOP_GR  0x0000000000200000UL /* Tomatillo */
0761 #define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */
0762 #define BUS_ERROR_SNOOP_RD  0x0000000000080000UL /* Tomatillo */
0763 #define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */
0764 #define BUS_ERROR_SNOOP_RDSA    0x0000000000010000UL /* Tomatillo */
0765 #define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */
0766 #define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */
0767 #define BUS_ERROR_CPU1PS    0x0000000000002000UL /* Safari */
0768 #define BUS_ERROR_WDATA_PERR    0x0000000000002000UL /* Tomatillo */
0769 #define BUS_ERROR_CPU1PB    0x0000000000001000UL /* Safari */
0770 #define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */
0771 #define BUS_ERROR_CPU0PS    0x0000000000000800UL /* Safari */
0772 #define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */
0773 #define BUS_ERROR_CPU0PB    0x0000000000000400UL /* Safari */
0774 #define BUS_ERROR_JBUS_ILL_B    0x0000000000000400UL /* Tomatillo */
0775 #define BUS_ERROR_CIQTO     0x0000000000000200UL /* Safari */
0776 #define BUS_ERROR_LPQTO     0x0000000000000100UL /* Safari */
0777 #define BUS_ERROR_JBUS_ILL_C    0x0000000000000100UL /* Tomatillo */
0778 #define BUS_ERROR_SFPQTO    0x0000000000000080UL /* Safari */
0779 #define BUS_ERROR_UFPQTO    0x0000000000000040UL /* Safari */
0780 #define BUS_ERROR_RD_PERR   0x0000000000000040UL /* Tomatillo */
0781 #define BUS_ERROR_APERR     0x0000000000000020UL /* Safari/Tomatillo */
0782 #define BUS_ERROR_UNMAP     0x0000000000000010UL /* Safari/Tomatillo */
0783 #define BUS_ERROR_BUSERR    0x0000000000000004UL /* Safari/Tomatillo */
0784 #define BUS_ERROR_TIMEOUT   0x0000000000000002UL /* Safari/Tomatillo */
0785 #define BUS_ERROR_ILL       0x0000000000000001UL /* Safari */
0786 
0787 /* We only expect UNMAP errors here.  The rest of the Safari errors
0788  * are marked fatal and thus cause a system reset.
0789  */
0790 static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id)
0791 {
0792     struct pci_pbm_info *pbm = dev_id;
0793     u64 errlog;
0794 
0795     errlog = upa_readq(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
0796     upa_writeq(errlog & ~(SAFARI_ERRLOG_ERROUT),
0797            pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
0798 
0799     if (!(errlog & BUS_ERROR_UNMAP)) {
0800         printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016llx]\n",
0801                pbm->name, errlog);
0802 
0803         return IRQ_HANDLED;
0804     }
0805 
0806     printk("%s: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n",
0807            pbm->name);
0808     schizo_check_iommu_error(pbm, SAFARI_ERR);
0809 
0810     return IRQ_HANDLED;
0811 }
0812 
0813 /* Nearly identical to PSYCHO equivalents... */
0814 #define SCHIZO_ECC_CTRL     0x10020UL
0815 #define  SCHIZO_ECCCTRL_EE   0x8000000000000000UL /* Enable ECC Checking */
0816 #define  SCHIZO_ECCCTRL_UE   0x4000000000000000UL /* Enable UE Interrupts */
0817 #define  SCHIZO_ECCCTRL_CE   0x2000000000000000UL /* Enable CE INterrupts */
0818 
0819 #define SCHIZO_SAFARI_ERRCTRL   0x10008UL
0820 #define  SCHIZO_SAFERRCTRL_EN    0x8000000000000000UL
0821 #define SCHIZO_SAFARI_IRQCTRL   0x10010UL
0822 #define  SCHIZO_SAFIRQCTRL_EN    0x8000000000000000UL
0823 
0824 static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino)
0825 {
0826     ino &= IMAP_INO;
0827 
0828     if (pbm->ino_bitmap & (1UL << ino))
0829         return 1;
0830 
0831     return 0;
0832 }
0833 
0834 /* How the Tomatillo IRQs are routed around is pure guesswork here.
0835  *
0836  * All the Tomatillo devices I see in prtconf dumps seem to have only
0837  * a single PCI bus unit attached to it.  It would seem they are separate
0838  * devices because their PortID (ie. JBUS ID) values are all different
0839  * and thus the registers are mapped to totally different locations.
0840  *
0841  * However, two Tomatillo's look "similar" in that the only difference
0842  * in their PortID is the lowest bit.
0843  *
0844  * So if we were to ignore this lower bit, it certainly looks like two
0845  * PCI bus units of the same Tomatillo.  I still have not really
0846  * figured this out...
0847  */
0848 static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
0849 {
0850     struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node);
0851     u64 tmp, err_mask, err_no_mask;
0852     int err;
0853 
0854     /* Tomatillo IRQ property layout is:
0855      * 0: PCIERR
0856      * 1: UE ERR
0857      * 2: CE ERR
0858      * 3: SERR
0859      * 4: POWER FAIL?
0860      */
0861 
0862     if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
0863         err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0,
0864                   "TOMATILLO_UE", pbm);
0865         if (err)
0866             printk(KERN_WARNING "%s: Could not register UE, "
0867                    "err=%d\n", pbm->name, err);
0868     }
0869     if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
0870         err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0,
0871                   "TOMATILLO_CE", pbm);
0872         if (err)
0873             printk(KERN_WARNING "%s: Could not register CE, "
0874                    "err=%d\n", pbm->name, err);
0875     }
0876     err = 0;
0877     if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
0878         err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
0879                   "TOMATILLO_PCIERR", pbm);
0880     } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
0881         err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
0882                   "TOMATILLO_PCIERR", pbm);
0883     }
0884     if (err)
0885         printk(KERN_WARNING "%s: Could not register PCIERR, "
0886                "err=%d\n", pbm->name, err);
0887 
0888     if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
0889         err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0,
0890                   "TOMATILLO_SERR", pbm);
0891         if (err)
0892             printk(KERN_WARNING "%s: Could not register SERR, "
0893                    "err=%d\n", pbm->name, err);
0894     }
0895 
0896     /* Enable UE and CE interrupts for controller. */
0897     upa_writeq((SCHIZO_ECCCTRL_EE |
0898             SCHIZO_ECCCTRL_UE |
0899             SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL);
0900 
0901     /* Enable PCI Error interrupts and clear error
0902      * bits.
0903      */
0904     err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
0905             SCHIZO_PCICTRL_TTO_ERR |
0906             SCHIZO_PCICTRL_RTRY_ERR |
0907             SCHIZO_PCICTRL_SERR |
0908             SCHIZO_PCICTRL_EEN);
0909 
0910     err_no_mask = SCHIZO_PCICTRL_DTO_ERR;
0911 
0912     tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
0913     tmp |= err_mask;
0914     tmp &= ~err_no_mask;
0915     upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
0916 
0917     err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
0918             SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
0919             SCHIZO_PCIAFSR_PTTO |
0920             SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
0921             SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
0922             SCHIZO_PCIAFSR_STTO);
0923 
0924     upa_writeq(err_mask, pbm->pbm_regs + SCHIZO_PCI_AFSR);
0925 
0926     err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR |
0927             BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD |
0928             BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA |
0929             BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO |
0930             BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR |
0931             BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B |
0932             BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR |
0933             BUS_ERROR_APERR | BUS_ERROR_UNMAP |
0934             BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT);
0935 
0936     upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask),
0937            pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL);
0938 
0939     upa_writeq((SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)),
0940            pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL);
0941 }
0942 
0943 static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
0944 {
0945     struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node);
0946     u64 tmp, err_mask, err_no_mask;
0947     int err;
0948 
0949     /* Schizo IRQ property layout is:
0950      * 0: PCIERR
0951      * 1: UE ERR
0952      * 2: CE ERR
0953      * 3: SERR
0954      * 4: POWER FAIL?
0955      */
0956 
0957     if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
0958         err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0,
0959                   "SCHIZO_UE", pbm);
0960         if (err)
0961             printk(KERN_WARNING "%s: Could not register UE, "
0962                    "err=%d\n", pbm->name, err);
0963     }
0964     if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
0965         err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0,
0966                   "SCHIZO_CE", pbm);
0967         if (err)
0968             printk(KERN_WARNING "%s: Could not register CE, "
0969                    "err=%d\n", pbm->name, err);
0970     }
0971     err = 0;
0972     if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
0973         err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
0974                   "SCHIZO_PCIERR", pbm);
0975     } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
0976         err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
0977                   "SCHIZO_PCIERR", pbm);
0978     }
0979     if (err)
0980         printk(KERN_WARNING "%s: Could not register PCIERR, "
0981                "err=%d\n", pbm->name, err);
0982 
0983     if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
0984         err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0,
0985                   "SCHIZO_SERR", pbm);
0986         if (err)
0987             printk(KERN_WARNING "%s: Could not register SERR, "
0988                    "err=%d\n", pbm->name, err);
0989     }
0990 
0991     /* Enable UE and CE interrupts for controller. */
0992     upa_writeq((SCHIZO_ECCCTRL_EE |
0993             SCHIZO_ECCCTRL_UE |
0994             SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL);
0995 
0996     err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
0997             SCHIZO_PCICTRL_ESLCK |
0998             SCHIZO_PCICTRL_TTO_ERR |
0999             SCHIZO_PCICTRL_RTRY_ERR |
1000             SCHIZO_PCICTRL_SBH_ERR |
1001             SCHIZO_PCICTRL_SERR |
1002             SCHIZO_PCICTRL_EEN);
1003 
1004     err_no_mask = (SCHIZO_PCICTRL_DTO_ERR |
1005                SCHIZO_PCICTRL_SBH_INT);
1006 
1007     /* Enable PCI Error interrupts and clear error
1008      * bits for each PBM.
1009      */
1010     tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1011     tmp |= err_mask;
1012     tmp &= ~err_no_mask;
1013     upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
1014 
1015     upa_writeq((SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1016             SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1017             SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1018             SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1019             SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1020             SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS),
1021            pbm->pbm_regs + SCHIZO_PCI_AFSR);
1022 
1023     /* Make all Safari error conditions fatal except unmapped
1024      * errors which we make generate interrupts.
1025      */
1026     err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS |
1027             BUS_ERROR_BADMA | BUS_ERROR_BADMB |
1028             BUS_ERROR_BADMC |
1029             BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1030             BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB |
1031             BUS_ERROR_CIQTO |
1032             BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO |
1033             BUS_ERROR_UFPQTO | BUS_ERROR_APERR |
1034             BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT |
1035             BUS_ERROR_ILL);
1036 #if 1
1037     /* XXX Something wrong with some Excalibur systems
1038      * XXX Sun is shipping.  The behavior on a 2-cpu
1039      * XXX machine is that both CPU1 parity error bits
1040      * XXX are set and are immediately set again when
1041      * XXX their error status bits are cleared.  Just
1042      * XXX ignore them for now.  -DaveM
1043      */
1044     err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1045               BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB);
1046 #endif
1047 
1048     upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask),
1049            pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL);
1050 }
1051 
1052 static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1053 {
1054     u8 *addr;
1055 
1056     /* Set cache-line size to 64 bytes, this is actually
1057      * a nop but I do it for completeness.
1058      */
1059     addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1060                     0, PCI_CACHE_LINE_SIZE);
1061     pci_config_write8(addr, 64 / sizeof(u32));
1062 
1063     /* Set PBM latency timer to 64 PCI clocks. */
1064     addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1065                     0, PCI_LATENCY_TIMER);
1066     pci_config_write8(addr, 64);
1067 }
1068 
1069 static void schizo_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
1070 {
1071     pbm_config_busmastering(pbm);
1072     pbm->is_66mhz_capable =
1073         (of_find_property(pbm->op->dev.of_node, "66mhz-capable", NULL)
1074          != NULL);
1075 
1076     pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
1077 
1078     if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1079         tomatillo_register_error_handlers(pbm);
1080     else
1081         schizo_register_error_handlers(pbm);
1082 }
1083 
1084 #define SCHIZO_STRBUF_CONTROL       (0x02800UL)
1085 #define SCHIZO_STRBUF_FLUSH     (0x02808UL)
1086 #define SCHIZO_STRBUF_FSYNC     (0x02810UL)
1087 #define SCHIZO_STRBUF_CTXFLUSH      (0x02818UL)
1088 #define SCHIZO_STRBUF_CTXMATCH      (0x10000UL)
1089 
1090 static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
1091 {
1092     unsigned long base = pbm->pbm_regs;
1093     u64 control;
1094 
1095     if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1096         /* TOMATILLO lacks streaming cache.  */
1097         return;
1098     }
1099 
1100     /* SCHIZO has context flushing. */
1101     pbm->stc.strbuf_control     = base + SCHIZO_STRBUF_CONTROL;
1102     pbm->stc.strbuf_pflush      = base + SCHIZO_STRBUF_FLUSH;
1103     pbm->stc.strbuf_fsync       = base + SCHIZO_STRBUF_FSYNC;
1104     pbm->stc.strbuf_ctxflush    = base + SCHIZO_STRBUF_CTXFLUSH;
1105     pbm->stc.strbuf_ctxmatch_base   = base + SCHIZO_STRBUF_CTXMATCH;
1106 
1107     pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1108         ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1109           + 63UL)
1110          & ~63UL);
1111     pbm->stc.strbuf_flushflag_pa = (unsigned long)
1112         __pa(pbm->stc.strbuf_flushflag);
1113 
1114     /* Turn off LRU locking and diag mode, enable the
1115      * streaming buffer and leave the rerun-disable
1116      * setting however OBP set it.
1117      */
1118     control = upa_readq(pbm->stc.strbuf_control);
1119     control &= ~(SCHIZO_STRBUF_CTRL_LPTR |
1120              SCHIZO_STRBUF_CTRL_LENAB |
1121              SCHIZO_STRBUF_CTRL_DENAB);
1122     control |= SCHIZO_STRBUF_CTRL_ENAB;
1123     upa_writeq(control, pbm->stc.strbuf_control);
1124 
1125     pbm->stc.strbuf_enabled = 1;
1126 }
1127 
1128 #define SCHIZO_IOMMU_CONTROL        (0x00200UL)
1129 #define SCHIZO_IOMMU_TSBBASE        (0x00208UL)
1130 #define SCHIZO_IOMMU_FLUSH      (0x00210UL)
1131 #define SCHIZO_IOMMU_CTXFLUSH       (0x00218UL)
1132 
1133 static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1134 {
1135     static const u32 vdma_default[] = { 0xc0000000, 0x40000000 };
1136     unsigned long i, tagbase, database;
1137     struct iommu *iommu = pbm->iommu;
1138     int tsbsize, err;
1139     const u32 *vdma;
1140     u32 dma_mask;
1141     u64 control;
1142 
1143     vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL);
1144     if (!vdma)
1145         vdma = vdma_default;
1146 
1147     dma_mask = vdma[0];
1148     switch (vdma[1]) {
1149         case 0x20000000:
1150             dma_mask |= 0x1fffffff;
1151             tsbsize = 64;
1152             break;
1153 
1154         case 0x40000000:
1155             dma_mask |= 0x3fffffff;
1156             tsbsize = 128;
1157             break;
1158 
1159         case 0x80000000:
1160             dma_mask |= 0x7fffffff;
1161             tsbsize = 128;
1162             break;
1163 
1164         default:
1165             printk(KERN_ERR PFX "Strange virtual-dma size.\n");
1166             return -EINVAL;
1167     }
1168 
1169     /* Register addresses, SCHIZO has iommu ctx flushing. */
1170     iommu->iommu_control  = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;
1171     iommu->iommu_tsbbase  = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE;
1172     iommu->iommu_flush    = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH;
1173     iommu->iommu_tags     = iommu->iommu_flush + (0xa580UL - 0x0210UL);
1174     iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH;
1175 
1176     /* We use the main control/status register of SCHIZO as the write
1177      * completion register.
1178      */
1179     iommu->write_complete_reg = pbm->controller_regs + 0x10000UL;
1180 
1181     /*
1182      * Invalidate TLB Entries.
1183      */
1184     control = upa_readq(iommu->iommu_control);
1185     control |= SCHIZO_IOMMU_CTRL_DENAB;
1186     upa_writeq(control, iommu->iommu_control);
1187 
1188     tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA;
1189 
1190     for (i = 0; i < 16; i++) {
1191         upa_writeq(0, pbm->pbm_regs + tagbase + (i * 8UL));
1192         upa_writeq(0, pbm->pbm_regs + database + (i * 8UL));
1193     }
1194 
1195     /* Leave diag mode enabled for full-flushing done
1196      * in pci_iommu.c
1197      */
1198     err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
1199                    pbm->numa_node);
1200     if (err) {
1201         printk(KERN_ERR PFX "iommu_table_init() fails with %d\n", err);
1202         return err;
1203     }
1204 
1205     upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
1206 
1207     control = upa_readq(iommu->iommu_control);
1208     control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
1209     switch (tsbsize) {
1210     case 64:
1211         control |= SCHIZO_IOMMU_TSBSZ_64K;
1212         break;
1213     case 128:
1214         control |= SCHIZO_IOMMU_TSBSZ_128K;
1215         break;
1216     }
1217 
1218     control |= SCHIZO_IOMMU_CTRL_ENAB;
1219     upa_writeq(control, iommu->iommu_control);
1220 
1221     return 0;
1222 }
1223 
1224 #define SCHIZO_PCI_IRQ_RETRY    (0x1a00UL)
1225 #define  SCHIZO_IRQ_RETRY_INF    0xffUL
1226 
1227 #define SCHIZO_PCI_DIAG         (0x2020UL)
1228 #define  SCHIZO_PCIDIAG_D_BADECC    (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */
1229 #define  SCHIZO_PCIDIAG_D_BYPASS    (1UL <<  9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */
1230 #define  SCHIZO_PCIDIAG_D_TTO       (1UL <<  8UL) /* Disable TTO errors (Schizo/Tomatillo) */
1231 #define  SCHIZO_PCIDIAG_D_RTRYARB   (1UL <<  7UL) /* Disable retry arbitration (Schizo) */
1232 #define  SCHIZO_PCIDIAG_D_RETRY     (1UL <<  6UL) /* Disable retry limit (Schizo/Tomatillo) */
1233 #define  SCHIZO_PCIDIAG_D_INTSYNC   (1UL <<  5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */
1234 #define  SCHIZO_PCIDIAG_I_DMA_PARITY    (1UL <<  3UL) /* Invert DMA parity (Schizo/Tomatillo) */
1235 #define  SCHIZO_PCIDIAG_I_PIOD_PARITY   (1UL <<  2UL) /* Invert PIO data parity (Schizo/Tomatillo) */
1236 #define  SCHIZO_PCIDIAG_I_PIOA_PARITY   (1UL <<  1UL) /* Invert PIO address parity (Schizo/Tomatillo) */
1237 
1238 #define TOMATILLO_PCI_IOC_CSR       (0x2248UL)
1239 #define TOMATILLO_IOC_PART_WPENAB   0x0000000000080000UL
1240 #define TOMATILLO_IOC_RDMULT_PENAB  0x0000000000040000UL
1241 #define TOMATILLO_IOC_RDONE_PENAB   0x0000000000020000UL
1242 #define TOMATILLO_IOC_RDLINE_PENAB  0x0000000000010000UL
1243 #define TOMATILLO_IOC_RDMULT_PLEN   0x000000000000c000UL
1244 #define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL
1245 #define TOMATILLO_IOC_RDONE_PLEN    0x0000000000003000UL
1246 #define TOMATILLO_IOC_RDONE_PLEN_SHIFT  12UL
1247 #define TOMATILLO_IOC_RDLINE_PLEN   0x0000000000000c00UL
1248 #define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL
1249 #define TOMATILLO_IOC_PREF_OFF      0x00000000000003f8UL
1250 #define TOMATILLO_IOC_PREF_OFF_SHIFT    3UL
1251 #define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL
1252 #define TOMATILLO_IOC_RDONE_CPENAB  0x0000000000000002UL
1253 #define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL
1254 
1255 #define TOMATILLO_PCI_IOC_TDIAG     (0x2250UL)
1256 #define TOMATILLO_PCI_IOC_DDIAG     (0x2290UL)
1257 
1258 static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1259 {
1260     u64 tmp;
1261 
1262     upa_writeq(5, pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY);
1263 
1264     tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1265 
1266     /* Enable arbiter for all PCI slots.  */
1267     tmp |= 0xff;
1268 
1269     if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1270         pbm->chip_version >= 0x2)
1271         tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT;
1272 
1273     if (!of_find_property(pbm->op->dev.of_node, "no-bus-parking", NULL))
1274         tmp |= SCHIZO_PCICTRL_PARK;
1275     else
1276         tmp &= ~SCHIZO_PCICTRL_PARK;
1277 
1278     if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1279         pbm->chip_version <= 0x1)
1280         tmp |= SCHIZO_PCICTRL_DTO_INT;
1281     else
1282         tmp &= ~SCHIZO_PCICTRL_DTO_INT;
1283 
1284     if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1285         tmp |= (SCHIZO_PCICTRL_MRM_PREF |
1286             SCHIZO_PCICTRL_RDO_PREF |
1287             SCHIZO_PCICTRL_RDL_PREF);
1288 
1289     upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
1290 
1291     tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_DIAG);
1292     tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB |
1293          SCHIZO_PCIDIAG_D_RETRY |
1294          SCHIZO_PCIDIAG_D_INTSYNC);
1295     upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_DIAG);
1296 
1297     if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1298         /* Clear prefetch lengths to workaround a bug in
1299          * Jalapeno...
1300          */
1301         tmp = (TOMATILLO_IOC_PART_WPENAB |
1302                (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) |
1303                TOMATILLO_IOC_RDMULT_CPENAB |
1304                TOMATILLO_IOC_RDONE_CPENAB |
1305                TOMATILLO_IOC_RDLINE_CPENAB);
1306 
1307         upa_writeq(tmp, pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR);
1308     }
1309 }
1310 
1311 static int schizo_pbm_init(struct pci_pbm_info *pbm,
1312                struct platform_device *op, u32 portid,
1313                int chip_type)
1314 {
1315     const struct linux_prom64_registers *regs;
1316     struct device_node *dp = op->dev.of_node;
1317     const char *chipset_name;
1318     int err;
1319 
1320     switch (chip_type) {
1321     case PBM_CHIP_TYPE_TOMATILLO:
1322         chipset_name = "TOMATILLO";
1323         break;
1324 
1325     case PBM_CHIP_TYPE_SCHIZO_PLUS:
1326         chipset_name = "SCHIZO+";
1327         break;
1328 
1329     case PBM_CHIP_TYPE_SCHIZO:
1330     default:
1331         chipset_name = "SCHIZO";
1332         break;
1333     }
1334 
1335     /* For SCHIZO, three OBP regs:
1336      * 1) PBM controller regs
1337      * 2) Schizo front-end controller regs (same for both PBMs)
1338      * 3) PBM PCI config space
1339      *
1340      * For TOMATILLO, four OBP regs:
1341      * 1) PBM controller regs
1342      * 2) Tomatillo front-end controller regs
1343      * 3) PBM PCI config space
1344      * 4) Ichip regs
1345      */
1346     regs = of_get_property(dp, "reg", NULL);
1347 
1348     pbm->next = pci_pbm_root;
1349     pci_pbm_root = pbm;
1350 
1351     pbm->numa_node = NUMA_NO_NODE;
1352 
1353     pbm->pci_ops = &sun4u_pci_ops;
1354     pbm->config_space_reg_bits = 8;
1355 
1356     pbm->index = pci_num_pbms++;
1357 
1358     pbm->portid = portid;
1359     pbm->op = op;
1360 
1361     pbm->chip_type = chip_type;
1362     pbm->chip_version = of_getintprop_default(dp, "version#", 0);
1363     pbm->chip_revision = of_getintprop_default(dp, "module-version#", 0);
1364 
1365     pbm->pbm_regs = regs[0].phys_addr;
1366     pbm->controller_regs = regs[1].phys_addr - 0x10000UL;
1367 
1368     if (chip_type == PBM_CHIP_TYPE_TOMATILLO)
1369         pbm->sync_reg = regs[3].phys_addr + 0x1a18UL;
1370 
1371     pbm->name = dp->full_name;
1372 
1373     printk("%s: %s PCI Bus Module ver[%x:%x]\n",
1374            pbm->name, chipset_name,
1375            pbm->chip_version, pbm->chip_revision);
1376 
1377     schizo_pbm_hw_init(pbm);
1378 
1379     pci_determine_mem_io_space(pbm);
1380 
1381     pci_get_pbm_props(pbm);
1382 
1383     err = schizo_pbm_iommu_init(pbm);
1384     if (err)
1385         return err;
1386 
1387     schizo_pbm_strbuf_init(pbm);
1388 
1389     schizo_scan_bus(pbm, &op->dev);
1390 
1391     return 0;
1392 }
1393 
1394 static inline int portid_compare(u32 x, u32 y, int chip_type)
1395 {
1396     if (chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1397         if (x == (y ^ 1))
1398             return 1;
1399         return 0;
1400     }
1401     return (x == y);
1402 }
1403 
1404 static struct pci_pbm_info *schizo_find_sibling(u32 portid, int chip_type)
1405 {
1406     struct pci_pbm_info *pbm;
1407 
1408     for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1409         if (portid_compare(pbm->portid, portid, chip_type))
1410             return pbm;
1411     }
1412     return NULL;
1413 }
1414 
1415 static int __schizo_init(struct platform_device *op, unsigned long chip_type)
1416 {
1417     struct device_node *dp = op->dev.of_node;
1418     struct pci_pbm_info *pbm;
1419     struct iommu *iommu;
1420     u32 portid;
1421     int err;
1422 
1423     portid = of_getintprop_default(dp, "portid", 0xff);
1424 
1425     err = -ENOMEM;
1426     pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
1427     if (!pbm) {
1428         printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
1429         goto out_err;
1430     }
1431 
1432     pbm->sibling = schizo_find_sibling(portid, chip_type);
1433 
1434     iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
1435     if (!iommu) {
1436         printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n");
1437         goto out_free_pbm;
1438     }
1439 
1440     pbm->iommu = iommu;
1441 
1442     if (schizo_pbm_init(pbm, op, portid, chip_type))
1443         goto out_free_iommu;
1444 
1445     if (pbm->sibling)
1446         pbm->sibling->sibling = pbm;
1447 
1448     dev_set_drvdata(&op->dev, pbm);
1449 
1450     return 0;
1451 
1452 out_free_iommu:
1453     kfree(pbm->iommu);
1454 
1455 out_free_pbm:
1456     kfree(pbm);
1457 
1458 out_err:
1459     return err;
1460 }
1461 
1462 static const struct of_device_id schizo_match[];
1463 static int schizo_probe(struct platform_device *op)
1464 {
1465     const struct of_device_id *match;
1466 
1467     match = of_match_device(schizo_match, &op->dev);
1468     if (!match)
1469         return -EINVAL;
1470     return __schizo_init(op, (unsigned long)match->data);
1471 }
1472 
1473 /* The ordering of this table is very important.  Some Tomatillo
1474  * nodes announce that they are compatible with both pci108e,a801
1475  * and pci108e,8001.  So list the chips in reverse chronological
1476  * order.
1477  */
1478 static const struct of_device_id schizo_match[] = {
1479     {
1480         .name = "pci",
1481         .compatible = "pci108e,a801",
1482         .data = (void *) PBM_CHIP_TYPE_TOMATILLO,
1483     },
1484     {
1485         .name = "pci",
1486         .compatible = "pci108e,8002",
1487         .data = (void *) PBM_CHIP_TYPE_SCHIZO_PLUS,
1488     },
1489     {
1490         .name = "pci",
1491         .compatible = "pci108e,8001",
1492         .data = (void *) PBM_CHIP_TYPE_SCHIZO,
1493     },
1494     {},
1495 };
1496 
1497 static struct platform_driver schizo_driver = {
1498     .driver = {
1499         .name = DRIVER_NAME,
1500         .of_match_table = schizo_match,
1501     },
1502     .probe      = schizo_probe,
1503 };
1504 
1505 static int __init schizo_init(void)
1506 {
1507     return platform_driver_register(&schizo_driver);
1508 }
1509 
1510 subsys_initcall(schizo_init);
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