Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* pci_sabre.c: Sabre specific PCI controller support.
0003  *
0004  * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
0005  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
0006  * Copyright (C) 1999 Jakub Jelinek   (jakub@redhat.com)
0007  */
0008 
0009 #include <linux/kernel.h>
0010 #include <linux/types.h>
0011 #include <linux/pci.h>
0012 #include <linux/init.h>
0013 #include <linux/export.h>
0014 #include <linux/slab.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/of_device.h>
0017 
0018 #include <asm/apb.h>
0019 #include <asm/iommu.h>
0020 #include <asm/irq.h>
0021 #include <asm/prom.h>
0022 #include <asm/upa.h>
0023 
0024 #include "pci_impl.h"
0025 #include "iommu_common.h"
0026 #include "psycho_common.h"
0027 
0028 #define DRIVER_NAME "sabre"
0029 #define PFX     DRIVER_NAME ": "
0030 
0031 /* SABRE PCI controller register offsets and definitions. */
0032 #define SABRE_UE_AFSR       0x0030UL
0033 #define  SABRE_UEAFSR_PDRD   0x4000000000000000UL   /* Primary PCI DMA Read */
0034 #define  SABRE_UEAFSR_PDWR   0x2000000000000000UL   /* Primary PCI DMA Write */
0035 #define  SABRE_UEAFSR_SDRD   0x0800000000000000UL   /* Secondary PCI DMA Read */
0036 #define  SABRE_UEAFSR_SDWR   0x0400000000000000UL   /* Secondary PCI DMA Write */
0037 #define  SABRE_UEAFSR_SDTE   0x0200000000000000UL   /* Secondary DMA Translation Error */
0038 #define  SABRE_UEAFSR_PDTE   0x0100000000000000UL   /* Primary DMA Translation Error */
0039 #define  SABRE_UEAFSR_BMSK   0x0000ffff00000000UL   /* Bytemask */
0040 #define  SABRE_UEAFSR_OFF    0x00000000e0000000UL   /* Offset (AFAR bits [5:3] */
0041 #define  SABRE_UEAFSR_BLK    0x0000000000800000UL   /* Was block operation */
0042 #define SABRE_UECE_AFAR     0x0038UL
0043 #define SABRE_CE_AFSR       0x0040UL
0044 #define  SABRE_CEAFSR_PDRD   0x4000000000000000UL   /* Primary PCI DMA Read */
0045 #define  SABRE_CEAFSR_PDWR   0x2000000000000000UL   /* Primary PCI DMA Write */
0046 #define  SABRE_CEAFSR_SDRD   0x0800000000000000UL   /* Secondary PCI DMA Read */
0047 #define  SABRE_CEAFSR_SDWR   0x0400000000000000UL   /* Secondary PCI DMA Write */
0048 #define  SABRE_CEAFSR_ESYND  0x00ff000000000000UL   /* ECC Syndrome */
0049 #define  SABRE_CEAFSR_BMSK   0x0000ffff00000000UL   /* Bytemask */
0050 #define  SABRE_CEAFSR_OFF    0x00000000e0000000UL   /* Offset */
0051 #define  SABRE_CEAFSR_BLK    0x0000000000800000UL   /* Was block operation */
0052 #define SABRE_UECE_AFAR_ALIAS   0x0048UL    /* Aliases to 0x0038 */
0053 #define SABRE_IOMMU_CONTROL 0x0200UL
0054 #define  SABRE_IOMMUCTRL_ERRSTS  0x0000000006000000UL   /* Error status bits */
0055 #define  SABRE_IOMMUCTRL_ERR     0x0000000001000000UL   /* Error present in IOTLB */
0056 #define  SABRE_IOMMUCTRL_LCKEN   0x0000000000800000UL   /* IOTLB lock enable */
0057 #define  SABRE_IOMMUCTRL_LCKPTR  0x0000000000780000UL   /* IOTLB lock pointer */
0058 #define  SABRE_IOMMUCTRL_TSBSZ   0x0000000000070000UL   /* TSB Size */
0059 #define  SABRE_IOMMU_TSBSZ_1K   0x0000000000000000
0060 #define  SABRE_IOMMU_TSBSZ_2K   0x0000000000010000
0061 #define  SABRE_IOMMU_TSBSZ_4K   0x0000000000020000
0062 #define  SABRE_IOMMU_TSBSZ_8K   0x0000000000030000
0063 #define  SABRE_IOMMU_TSBSZ_16K  0x0000000000040000
0064 #define  SABRE_IOMMU_TSBSZ_32K  0x0000000000050000
0065 #define  SABRE_IOMMU_TSBSZ_64K  0x0000000000060000
0066 #define  SABRE_IOMMU_TSBSZ_128K 0x0000000000070000
0067 #define  SABRE_IOMMUCTRL_TBWSZ   0x0000000000000004UL   /* TSB assumed page size */
0068 #define  SABRE_IOMMUCTRL_DENAB   0x0000000000000002UL   /* Diagnostic Mode Enable */
0069 #define  SABRE_IOMMUCTRL_ENAB    0x0000000000000001UL   /* IOMMU Enable */
0070 #define SABRE_IOMMU_TSBBASE 0x0208UL
0071 #define SABRE_IOMMU_FLUSH   0x0210UL
0072 #define SABRE_IMAP_A_SLOT0  0x0c00UL
0073 #define SABRE_IMAP_B_SLOT0  0x0c20UL
0074 #define SABRE_IMAP_SCSI     0x1000UL
0075 #define SABRE_IMAP_ETH      0x1008UL
0076 #define SABRE_IMAP_BPP      0x1010UL
0077 #define SABRE_IMAP_AU_REC   0x1018UL
0078 #define SABRE_IMAP_AU_PLAY  0x1020UL
0079 #define SABRE_IMAP_PFAIL    0x1028UL
0080 #define SABRE_IMAP_KMS      0x1030UL
0081 #define SABRE_IMAP_FLPY     0x1038UL
0082 #define SABRE_IMAP_SHW      0x1040UL
0083 #define SABRE_IMAP_KBD      0x1048UL
0084 #define SABRE_IMAP_MS       0x1050UL
0085 #define SABRE_IMAP_SER      0x1058UL
0086 #define SABRE_IMAP_UE       0x1070UL
0087 #define SABRE_IMAP_CE       0x1078UL
0088 #define SABRE_IMAP_PCIERR   0x1080UL
0089 #define SABRE_IMAP_GFX      0x1098UL
0090 #define SABRE_IMAP_EUPA     0x10a0UL
0091 #define SABRE_ICLR_A_SLOT0  0x1400UL
0092 #define SABRE_ICLR_B_SLOT0  0x1480UL
0093 #define SABRE_ICLR_SCSI     0x1800UL
0094 #define SABRE_ICLR_ETH      0x1808UL
0095 #define SABRE_ICLR_BPP      0x1810UL
0096 #define SABRE_ICLR_AU_REC   0x1818UL
0097 #define SABRE_ICLR_AU_PLAY  0x1820UL
0098 #define SABRE_ICLR_PFAIL    0x1828UL
0099 #define SABRE_ICLR_KMS      0x1830UL
0100 #define SABRE_ICLR_FLPY     0x1838UL
0101 #define SABRE_ICLR_SHW      0x1840UL
0102 #define SABRE_ICLR_KBD      0x1848UL
0103 #define SABRE_ICLR_MS       0x1850UL
0104 #define SABRE_ICLR_SER      0x1858UL
0105 #define SABRE_ICLR_UE       0x1870UL
0106 #define SABRE_ICLR_CE       0x1878UL
0107 #define SABRE_ICLR_PCIERR   0x1880UL
0108 #define SABRE_WRSYNC        0x1c20UL
0109 #define SABRE_PCICTRL       0x2000UL
0110 #define  SABRE_PCICTRL_MRLEN     0x0000001000000000UL   /* Use MemoryReadLine for block loads/stores */
0111 #define  SABRE_PCICTRL_SERR  0x0000000400000000UL   /* Set when SERR asserted on PCI bus */
0112 #define  SABRE_PCICTRL_ARBPARK   0x0000000000200000UL   /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
0113 #define  SABRE_PCICTRL_CPUPRIO   0x0000000000100000UL   /* Ultra-IIi granted every other bus cycle */
0114 #define  SABRE_PCICTRL_ARBPRIO   0x00000000000f0000UL   /* Slot which is granted every other bus cycle */
0115 #define  SABRE_PCICTRL_ERREN     0x0000000000000100UL   /* PCI Error Interrupt Enable */
0116 #define  SABRE_PCICTRL_RTRYWE    0x0000000000000080UL   /* DMA Flow Control 0=wait-if-possible 1=retry */
0117 #define  SABRE_PCICTRL_AEN   0x000000000000000fUL   /* Slot PCI arbitration enables */
0118 #define SABRE_PIOAFSR       0x2010UL
0119 #define  SABRE_PIOAFSR_PMA   0x8000000000000000UL   /* Primary Master Abort */
0120 #define  SABRE_PIOAFSR_PTA   0x4000000000000000UL   /* Primary Target Abort */
0121 #define  SABRE_PIOAFSR_PRTRY     0x2000000000000000UL   /* Primary Excessive Retries */
0122 #define  SABRE_PIOAFSR_PPERR     0x1000000000000000UL   /* Primary Parity Error */
0123 #define  SABRE_PIOAFSR_SMA   0x0800000000000000UL   /* Secondary Master Abort */
0124 #define  SABRE_PIOAFSR_STA   0x0400000000000000UL   /* Secondary Target Abort */
0125 #define  SABRE_PIOAFSR_SRTRY     0x0200000000000000UL   /* Secondary Excessive Retries */
0126 #define  SABRE_PIOAFSR_SPERR     0x0100000000000000UL   /* Secondary Parity Error */
0127 #define  SABRE_PIOAFSR_BMSK  0x0000ffff00000000UL   /* Byte Mask */
0128 #define  SABRE_PIOAFSR_BLK   0x0000000080000000UL   /* Was Block Operation */
0129 #define SABRE_PIOAFAR       0x2018UL
0130 #define SABRE_PCIDIAG       0x2020UL
0131 #define  SABRE_PCIDIAG_DRTRY     0x0000000000000040UL   /* Disable PIO Retry Limit */
0132 #define  SABRE_PCIDIAG_IPAPAR    0x0000000000000008UL   /* Invert PIO Address Parity */
0133 #define  SABRE_PCIDIAG_IPDPAR    0x0000000000000004UL   /* Invert PIO Data Parity */
0134 #define  SABRE_PCIDIAG_IDDPAR    0x0000000000000002UL   /* Invert DMA Data Parity */
0135 #define  SABRE_PCIDIAG_ELPBK     0x0000000000000001UL   /* Loopback Enable - not supported */
0136 #define SABRE_PCITASR       0x2028UL
0137 #define  SABRE_PCITASR_EF    0x0000000000000080UL   /* Respond to 0xe0000000-0xffffffff */
0138 #define  SABRE_PCITASR_CD    0x0000000000000040UL   /* Respond to 0xc0000000-0xdfffffff */
0139 #define  SABRE_PCITASR_AB    0x0000000000000020UL   /* Respond to 0xa0000000-0xbfffffff */
0140 #define  SABRE_PCITASR_89    0x0000000000000010UL   /* Respond to 0x80000000-0x9fffffff */
0141 #define  SABRE_PCITASR_67    0x0000000000000008UL   /* Respond to 0x60000000-0x7fffffff */
0142 #define  SABRE_PCITASR_45    0x0000000000000004UL   /* Respond to 0x40000000-0x5fffffff */
0143 #define  SABRE_PCITASR_23    0x0000000000000002UL   /* Respond to 0x20000000-0x3fffffff */
0144 #define  SABRE_PCITASR_01    0x0000000000000001UL   /* Respond to 0x00000000-0x1fffffff */
0145 #define SABRE_PIOBUF_DIAG   0x5000UL
0146 #define SABRE_DMABUF_DIAGLO 0x5100UL
0147 #define SABRE_DMABUF_DIAGHI 0x51c0UL
0148 #define SABRE_IMAP_GFX_ALIAS    0x6000UL    /* Aliases to 0x1098 */
0149 #define SABRE_IMAP_EUPA_ALIAS   0x8000UL    /* Aliases to 0x10a0 */
0150 #define SABRE_IOMMU_VADIAG  0xa400UL
0151 #define SABRE_IOMMU_TCDIAG  0xa408UL
0152 #define SABRE_IOMMU_TAG     0xa580UL
0153 #define  SABRE_IOMMUTAG_ERRSTS   0x0000000001800000UL   /* Error status bits */
0154 #define  SABRE_IOMMUTAG_ERR  0x0000000000400000UL   /* Error present */
0155 #define  SABRE_IOMMUTAG_WRITE    0x0000000000200000UL   /* Page is writable */
0156 #define  SABRE_IOMMUTAG_STREAM   0x0000000000100000UL   /* Streamable bit - unused */
0157 #define  SABRE_IOMMUTAG_SIZE     0x0000000000080000UL   /* 0=8k 1=16k */
0158 #define  SABRE_IOMMUTAG_VPN  0x000000000007ffffUL   /* Virtual Page Number [31:13] */
0159 #define SABRE_IOMMU_DATA    0xa600UL
0160 #define SABRE_IOMMUDATA_VALID    0x0000000040000000UL   /* Valid */
0161 #define SABRE_IOMMUDATA_USED     0x0000000020000000UL   /* Used (for LRU algorithm) */
0162 #define SABRE_IOMMUDATA_CACHE    0x0000000010000000UL   /* Cacheable */
0163 #define SABRE_IOMMUDATA_PPN  0x00000000001fffffUL   /* Physical Page Number [33:13] */
0164 #define SABRE_PCI_IRQSTATE  0xa800UL
0165 #define SABRE_OBIO_IRQSTATE 0xa808UL
0166 #define SABRE_FFBCFG        0xf000UL
0167 #define  SABRE_FFBCFG_SPRQS  0x000000000f000000 /* Slave P_RQST queue size */
0168 #define  SABRE_FFBCFG_ONEREAD    0x0000000000004000 /* Slave supports one outstanding read */
0169 #define SABRE_MCCTRL0       0xf010UL
0170 #define  SABRE_MCCTRL0_RENAB     0x0000000080000000 /* Refresh Enable */
0171 #define  SABRE_MCCTRL0_EENAB     0x0000000010000000 /* Enable all ECC functions */
0172 #define  SABRE_MCCTRL0_11BIT     0x0000000000001000 /* Enable 11-bit column addressing */
0173 #define  SABRE_MCCTRL0_DPP   0x0000000000000f00 /* DIMM Pair Present Bits */
0174 #define  SABRE_MCCTRL0_RINTVL    0x00000000000000ff /* Refresh Interval */
0175 #define SABRE_MCCTRL1       0xf018UL
0176 #define  SABRE_MCCTRL1_AMDC  0x0000000038000000 /* Advance Memdata Clock */
0177 #define  SABRE_MCCTRL1_ARDC  0x0000000007000000 /* Advance DRAM Read Data Clock */
0178 #define  SABRE_MCCTRL1_CSR   0x0000000000e00000 /* CAS to RAS delay for CBR refresh */
0179 #define  SABRE_MCCTRL1_CASRW     0x00000000001c0000 /* CAS length for read/write */
0180 #define  SABRE_MCCTRL1_RCD   0x0000000000038000 /* RAS to CAS delay */
0181 #define  SABRE_MCCTRL1_CP    0x0000000000007000 /* CAS Precharge */
0182 #define  SABRE_MCCTRL1_RP    0x0000000000000e00 /* RAS Precharge */
0183 #define  SABRE_MCCTRL1_RAS   0x00000000000001c0 /* Length of RAS for refresh */
0184 #define  SABRE_MCCTRL1_CASRW2    0x0000000000000038 /* Must be same as CASRW */
0185 #define  SABRE_MCCTRL1_RSC   0x0000000000000007 /* RAS after CAS hold time */
0186 #define SABRE_RESETCTRL     0xf020UL
0187 
0188 #define SABRE_CONFIGSPACE   0x001000000UL
0189 #define SABRE_IOSPACE       0x002000000UL
0190 #define SABRE_IOSPACE_SIZE  0x000ffffffUL
0191 #define SABRE_MEMSPACE      0x100000000UL
0192 #define SABRE_MEMSPACE_SIZE 0x07fffffffUL
0193 
0194 static int hummingbird_p;
0195 static struct pci_bus *sabre_root_bus;
0196 
0197 static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
0198 {
0199     struct pci_pbm_info *pbm = dev_id;
0200     unsigned long afsr_reg = pbm->controller_regs + SABRE_UE_AFSR;
0201     unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
0202     unsigned long afsr, afar, error_bits;
0203     int reported;
0204 
0205     /* Latch uncorrectable error status. */
0206     afar = upa_readq(afar_reg);
0207     afsr = upa_readq(afsr_reg);
0208 
0209     /* Clear the primary/secondary error status bits. */
0210     error_bits = afsr &
0211         (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
0212          SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
0213          SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE);
0214     if (!error_bits)
0215         return IRQ_NONE;
0216     upa_writeq(error_bits, afsr_reg);
0217 
0218     /* Log the error. */
0219     printk("%s: Uncorrectable Error, primary error type[%s%s]\n",
0220            pbm->name,
0221            ((error_bits & SABRE_UEAFSR_PDRD) ?
0222         "DMA Read" :
0223         ((error_bits & SABRE_UEAFSR_PDWR) ?
0224          "DMA Write" : "???")),
0225            ((error_bits & SABRE_UEAFSR_PDTE) ?
0226         ":Translation Error" : ""));
0227     printk("%s: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n",
0228            pbm->name,
0229            (afsr & SABRE_UEAFSR_BMSK) >> 32UL,
0230            (afsr & SABRE_UEAFSR_OFF) >> 29UL,
0231            ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0));
0232     printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
0233     printk("%s: UE Secondary errors [", pbm->name);
0234     reported = 0;
0235     if (afsr & SABRE_UEAFSR_SDRD) {
0236         reported++;
0237         printk("(DMA Read)");
0238     }
0239     if (afsr & SABRE_UEAFSR_SDWR) {
0240         reported++;
0241         printk("(DMA Write)");
0242     }
0243     if (afsr & SABRE_UEAFSR_SDTE) {
0244         reported++;
0245         printk("(Translation Error)");
0246     }
0247     if (!reported)
0248         printk("(none)");
0249     printk("]\n");
0250 
0251     /* Interrogate IOMMU for error status. */
0252     psycho_check_iommu_error(pbm, afsr, afar, UE_ERR);
0253 
0254     return IRQ_HANDLED;
0255 }
0256 
0257 static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
0258 {
0259     struct pci_pbm_info *pbm = dev_id;
0260     unsigned long afsr_reg = pbm->controller_regs + SABRE_CE_AFSR;
0261     unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
0262     unsigned long afsr, afar, error_bits;
0263     int reported;
0264 
0265     /* Latch error status. */
0266     afar = upa_readq(afar_reg);
0267     afsr = upa_readq(afsr_reg);
0268 
0269     /* Clear primary/secondary error status bits. */
0270     error_bits = afsr &
0271         (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
0272          SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR);
0273     if (!error_bits)
0274         return IRQ_NONE;
0275     upa_writeq(error_bits, afsr_reg);
0276 
0277     /* Log the error. */
0278     printk("%s: Correctable Error, primary error type[%s]\n",
0279            pbm->name,
0280            ((error_bits & SABRE_CEAFSR_PDRD) ?
0281         "DMA Read" :
0282         ((error_bits & SABRE_CEAFSR_PDWR) ?
0283          "DMA Write" : "???")));
0284 
0285     /* XXX Use syndrome and afar to print out module string just like
0286      * XXX UDB CE trap handler does... -DaveM
0287      */
0288     printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
0289            "was_block(%d)\n",
0290            pbm->name,
0291            (afsr & SABRE_CEAFSR_ESYND) >> 48UL,
0292            (afsr & SABRE_CEAFSR_BMSK) >> 32UL,
0293            (afsr & SABRE_CEAFSR_OFF) >> 29UL,
0294            ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0));
0295     printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
0296     printk("%s: CE Secondary errors [", pbm->name);
0297     reported = 0;
0298     if (afsr & SABRE_CEAFSR_SDRD) {
0299         reported++;
0300         printk("(DMA Read)");
0301     }
0302     if (afsr & SABRE_CEAFSR_SDWR) {
0303         reported++;
0304         printk("(DMA Write)");
0305     }
0306     if (!reported)
0307         printk("(none)");
0308     printk("]\n");
0309 
0310     return IRQ_HANDLED;
0311 }
0312 
0313 static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
0314 {
0315     struct device_node *dp = pbm->op->dev.of_node;
0316     struct platform_device *op;
0317     unsigned long base = pbm->controller_regs;
0318     u64 tmp;
0319     int err;
0320 
0321     if (pbm->chip_type == PBM_CHIP_TYPE_SABRE)
0322         dp = dp->parent;
0323 
0324     op = of_find_device_by_node(dp);
0325     if (!op)
0326         return;
0327 
0328     /* Sabre/Hummingbird IRQ property layout is:
0329      * 0: PCI ERR
0330      * 1: UE ERR
0331      * 2: CE ERR
0332      * 3: POWER FAIL
0333      */
0334     if (op->archdata.num_irqs < 4)
0335         return;
0336 
0337     /* We clear the error bits in the appropriate AFSR before
0338      * registering the handler so that we don't get spurious
0339      * interrupts.
0340      */
0341     upa_writeq((SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
0342             SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
0343             SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE),
0344            base + SABRE_UE_AFSR);
0345 
0346     err = request_irq(op->archdata.irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm);
0347     if (err)
0348         printk(KERN_WARNING "%s: Couldn't register UE, err=%d.\n",
0349                pbm->name, err);
0350 
0351     upa_writeq((SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
0352             SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR),
0353            base + SABRE_CE_AFSR);
0354 
0355 
0356     err = request_irq(op->archdata.irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm);
0357     if (err)
0358         printk(KERN_WARNING "%s: Couldn't register CE, err=%d.\n",
0359                pbm->name, err);
0360     err = request_irq(op->archdata.irqs[0], psycho_pcierr_intr, 0,
0361               "SABRE_PCIERR", pbm);
0362     if (err)
0363         printk(KERN_WARNING "%s: Couldn't register PCIERR, err=%d.\n",
0364                pbm->name, err);
0365 
0366     tmp = upa_readq(base + SABRE_PCICTRL);
0367     tmp |= SABRE_PCICTRL_ERREN;
0368     upa_writeq(tmp, base + SABRE_PCICTRL);
0369 }
0370 
0371 static void apb_init(struct pci_bus *sabre_bus)
0372 {
0373     struct pci_dev *pdev;
0374 
0375     list_for_each_entry(pdev, &sabre_bus->devices, bus_list) {
0376         if (pdev->vendor == PCI_VENDOR_ID_SUN &&
0377             pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {
0378             u16 word16;
0379 
0380             pci_read_config_word(pdev, PCI_COMMAND, &word16);
0381             word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
0382                 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
0383                 PCI_COMMAND_IO;
0384             pci_write_config_word(pdev, PCI_COMMAND, word16);
0385 
0386             /* Status register bits are "write 1 to clear". */
0387             pci_write_config_word(pdev, PCI_STATUS, 0xffff);
0388             pci_write_config_word(pdev, PCI_SEC_STATUS, 0xffff);
0389 
0390             /* Use a primary/seconday latency timer value
0391              * of 64.
0392              */
0393             pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
0394             pci_write_config_byte(pdev, PCI_SEC_LATENCY_TIMER, 64);
0395 
0396             /* Enable reporting/forwarding of master aborts,
0397              * parity, and SERR.
0398              */
0399             pci_write_config_byte(pdev, PCI_BRIDGE_CONTROL,
0400                           (PCI_BRIDGE_CTL_PARITY |
0401                            PCI_BRIDGE_CTL_SERR |
0402                            PCI_BRIDGE_CTL_MASTER_ABORT));
0403         }
0404     }
0405 }
0406 
0407 static void sabre_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
0408 {
0409     static int once;
0410 
0411     /* The APB bridge speaks to the Sabre host PCI bridge
0412      * at 66Mhz, but the front side of APB runs at 33Mhz
0413      * for both segments.
0414      *
0415      * Hummingbird systems do not use APB, so they run
0416      * at 66MHZ.
0417      */
0418     if (hummingbird_p)
0419         pbm->is_66mhz_capable = 1;
0420     else
0421         pbm->is_66mhz_capable = 0;
0422 
0423     /* This driver has not been verified to handle
0424      * multiple SABREs yet, so trap this.
0425      *
0426      * Also note that the SABRE host bridge is hardwired
0427      * to live at bus 0.
0428      */
0429     if (once != 0) {
0430         printk(KERN_ERR PFX "Multiple controllers unsupported.\n");
0431         return;
0432     }
0433     once++;
0434 
0435     pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
0436     if (!pbm->pci_bus)
0437         return;
0438 
0439     sabre_root_bus = pbm->pci_bus;
0440 
0441     apb_init(pbm->pci_bus);
0442 
0443     sabre_register_error_handlers(pbm);
0444 }
0445 
0446 static void sabre_pbm_init(struct pci_pbm_info *pbm,
0447                struct platform_device *op)
0448 {
0449     psycho_pbm_init_common(pbm, op, "SABRE", PBM_CHIP_TYPE_SABRE);
0450     pbm->pci_afsr = pbm->controller_regs + SABRE_PIOAFSR;
0451     pbm->pci_afar = pbm->controller_regs + SABRE_PIOAFAR;
0452     pbm->pci_csr = pbm->controller_regs + SABRE_PCICTRL;
0453     sabre_scan_bus(pbm, &op->dev);
0454 }
0455 
0456 static const struct of_device_id sabre_match[];
0457 static int sabre_probe(struct platform_device *op)
0458 {
0459     const struct of_device_id *match;
0460     const struct linux_prom64_registers *pr_regs;
0461     struct device_node *dp = op->dev.of_node;
0462     struct pci_pbm_info *pbm;
0463     u32 upa_portid, dma_mask;
0464     struct iommu *iommu;
0465     int tsbsize, err;
0466     const u32 *vdma;
0467     u64 clear_irq;
0468 
0469     match = of_match_device(sabre_match, &op->dev);
0470     hummingbird_p = match && (match->data != NULL);
0471     if (!hummingbird_p) {
0472         struct device_node *cpu_dp;
0473 
0474         /* Of course, Sun has to encode things a thousand
0475          * different ways, inconsistently.
0476          */
0477         for_each_node_by_type(cpu_dp, "cpu") {
0478             if (of_node_name_eq(cpu_dp, "SUNW,UltraSPARC-IIe"))
0479                 hummingbird_p = 1;
0480         }
0481     }
0482 
0483     err = -ENOMEM;
0484     pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
0485     if (!pbm) {
0486         printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
0487         goto out_err;
0488     }
0489 
0490     iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
0491     if (!iommu) {
0492         printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
0493         goto out_free_controller;
0494     }
0495 
0496     pbm->iommu = iommu;
0497 
0498     upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
0499 
0500     pbm->portid = upa_portid;
0501 
0502     /*
0503      * Map in SABRE register set and report the presence of this SABRE.
0504      */
0505     
0506     pr_regs = of_get_property(dp, "reg", NULL);
0507     err = -ENODEV;
0508     if (!pr_regs) {
0509         printk(KERN_ERR PFX "No reg property\n");
0510         goto out_free_iommu;
0511     }
0512 
0513     /*
0514      * First REG in property is base of entire SABRE register space.
0515      */
0516     pbm->controller_regs = pr_regs[0].phys_addr;
0517 
0518     /* Clear interrupts */
0519 
0520     /* PCI first */
0521     for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)
0522         upa_writeq(0x0UL, pbm->controller_regs + clear_irq);
0523 
0524     /* Then OBIO */
0525     for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)
0526         upa_writeq(0x0UL, pbm->controller_regs + clear_irq);
0527 
0528     /* Error interrupts are enabled later after the bus scan. */
0529     upa_writeq((SABRE_PCICTRL_MRLEN   | SABRE_PCICTRL_SERR |
0530             SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN),
0531            pbm->controller_regs + SABRE_PCICTRL);
0532 
0533     /* Now map in PCI config space for entire SABRE. */
0534     pbm->config_space = pbm->controller_regs + SABRE_CONFIGSPACE;
0535 
0536     vdma = of_get_property(dp, "virtual-dma", NULL);
0537     if (!vdma) {
0538         printk(KERN_ERR PFX "No virtual-dma property\n");
0539         goto out_free_iommu;
0540     }
0541 
0542     dma_mask = vdma[0];
0543     switch(vdma[1]) {
0544         case 0x20000000:
0545             dma_mask |= 0x1fffffff;
0546             tsbsize = 64;
0547             break;
0548         case 0x40000000:
0549             dma_mask |= 0x3fffffff;
0550             tsbsize = 128;
0551             break;
0552 
0553         case 0x80000000:
0554             dma_mask |= 0x7fffffff;
0555             tsbsize = 128;
0556             break;
0557         default:
0558             printk(KERN_ERR PFX "Strange virtual-dma size.\n");
0559             goto out_free_iommu;
0560     }
0561 
0562     err = psycho_iommu_init(pbm, tsbsize, vdma[0], dma_mask, SABRE_WRSYNC);
0563     if (err)
0564         goto out_free_iommu;
0565 
0566     /*
0567      * Look for APB underneath.
0568      */
0569     sabre_pbm_init(pbm, op);
0570 
0571     pbm->next = pci_pbm_root;
0572     pci_pbm_root = pbm;
0573 
0574     dev_set_drvdata(&op->dev, pbm);
0575 
0576     return 0;
0577 
0578 out_free_iommu:
0579     kfree(pbm->iommu);
0580 
0581 out_free_controller:
0582     kfree(pbm);
0583 
0584 out_err:
0585     return err;
0586 }
0587 
0588 static const struct of_device_id sabre_match[] = {
0589     {
0590         .name = "pci",
0591         .compatible = "pci108e,a001",
0592         .data = (void *) 1,
0593     },
0594     {
0595         .name = "pci",
0596         .compatible = "pci108e,a000",
0597     },
0598     {},
0599 };
0600 
0601 static struct platform_driver sabre_driver = {
0602     .driver = {
0603         .name = DRIVER_NAME,
0604         .of_match_table = sabre_match,
0605     },
0606     .probe      = sabre_probe,
0607 };
0608 
0609 static int __init sabre_init(void)
0610 {
0611     return platform_driver_register(&sabre_driver);
0612 }
0613 
0614 subsys_initcall(sabre_init);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!