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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* pci_psycho.c: PSYCHO/U2P specific PCI controller support.
0003  *
0004  * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
0005  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
0006  * Copyright (C) 1999 Jakub Jelinek   (jakub@redhat.com)
0007  */
0008 
0009 #include <linux/kernel.h>
0010 #include <linux/types.h>
0011 #include <linux/pci.h>
0012 #include <linux/init.h>
0013 #include <linux/export.h>
0014 #include <linux/slab.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/of_device.h>
0017 
0018 #include <asm/iommu.h>
0019 #include <asm/irq.h>
0020 #include <asm/starfire.h>
0021 #include <asm/prom.h>
0022 #include <asm/upa.h>
0023 
0024 #include "pci_impl.h"
0025 #include "iommu_common.h"
0026 #include "psycho_common.h"
0027 
0028 #define DRIVER_NAME "psycho"
0029 #define PFX     DRIVER_NAME ": "
0030 
0031 /* Misc. PSYCHO PCI controller register offsets and definitions. */
0032 #define PSYCHO_CONTROL      0x0010UL
0033 #define  PSYCHO_CONTROL_IMPL     0xf000000000000000UL /* Implementation of this PSYCHO*/
0034 #define  PSYCHO_CONTROL_VER  0x0f00000000000000UL /* Version of this PSYCHO       */
0035 #define  PSYCHO_CONTROL_MID  0x00f8000000000000UL /* UPA Module ID of PSYCHO      */
0036 #define  PSYCHO_CONTROL_IGN  0x0007c00000000000UL /* Interrupt Group Number       */
0037 #define  PSYCHO_CONTROL_RESV     0x00003ffffffffff0UL /* Reserved                     */
0038 #define  PSYCHO_CONTROL_APCKEN   0x0000000000000008UL /* Address Parity Check Enable  */
0039 #define  PSYCHO_CONTROL_APERR    0x0000000000000004UL /* Incoming System Addr Parerr  */
0040 #define  PSYCHO_CONTROL_IAP  0x0000000000000002UL /* Invert UPA Parity            */
0041 #define  PSYCHO_CONTROL_MODE     0x0000000000000001UL /* PSYCHO clock mode            */
0042 #define PSYCHO_PCIA_CTRL    0x2000UL
0043 #define PSYCHO_PCIB_CTRL    0x4000UL
0044 #define  PSYCHO_PCICTRL_RESV1    0xfffffff000000000UL /* Reserved                     */
0045 #define  PSYCHO_PCICTRL_SBH_ERR  0x0000000800000000UL /* Streaming byte hole error    */
0046 #define  PSYCHO_PCICTRL_SERR     0x0000000400000000UL /* SERR signal asserted         */
0047 #define  PSYCHO_PCICTRL_SPEED    0x0000000200000000UL /* PCI speed (1 is U2P clock)   */
0048 #define  PSYCHO_PCICTRL_RESV2    0x00000001ffc00000UL /* Reserved                     */
0049 #define  PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking      */
0050 #define  PSYCHO_PCICTRL_RESV3    0x00000000001ff800UL /* Reserved                     */
0051 #define  PSYCHO_PCICTRL_SBH_INT  0x0000000000000400UL /* Streaming byte hole int enab */
0052 #define  PSYCHO_PCICTRL_WEN  0x0000000000000200UL /* Power Mgmt Wake Enable       */
0053 #define  PSYCHO_PCICTRL_EEN  0x0000000000000100UL /* PCI Error Interrupt Enable   */
0054 #define  PSYCHO_PCICTRL_RESV4    0x00000000000000c0UL /* Reserved                     */
0055 #define  PSYCHO_PCICTRL_AEN  0x000000000000003fUL /* PCI DVMA Arbitration Enable  */
0056 
0057 /* PSYCHO error handling support. */
0058 
0059 /* Helper function of IOMMU error checking, which checks out
0060  * the state of the streaming buffers.  The IOMMU lock is
0061  * held when this is called.
0062  *
0063  * For the PCI error case we know which PBM (and thus which
0064  * streaming buffer) caused the error, but for the uncorrectable
0065  * error case we do not.  So we always check both streaming caches.
0066  */
0067 #define PSYCHO_STRBUF_CONTROL_A 0x2800UL
0068 #define PSYCHO_STRBUF_CONTROL_B 0x4800UL
0069 #define  PSYCHO_STRBUF_CTRL_LPTR    0x00000000000000f0UL /* LRU Lock Pointer */
0070 #define  PSYCHO_STRBUF_CTRL_LENAB   0x0000000000000008UL /* LRU Lock Enable */
0071 #define  PSYCHO_STRBUF_CTRL_RRDIS   0x0000000000000004UL /* Rerun Disable */
0072 #define  PSYCHO_STRBUF_CTRL_DENAB   0x0000000000000002UL /* Diagnostic Mode Enable */
0073 #define  PSYCHO_STRBUF_CTRL_ENAB    0x0000000000000001UL /* Streaming Buffer Enable */
0074 #define PSYCHO_STRBUF_FLUSH_A   0x2808UL
0075 #define PSYCHO_STRBUF_FLUSH_B   0x4808UL
0076 #define PSYCHO_STRBUF_FSYNC_A   0x2810UL
0077 #define PSYCHO_STRBUF_FSYNC_B   0x4810UL
0078 #define PSYCHO_STC_DATA_A   0xb000UL
0079 #define PSYCHO_STC_DATA_B   0xc000UL
0080 #define PSYCHO_STC_ERR_A    0xb400UL
0081 #define PSYCHO_STC_ERR_B    0xc400UL
0082 #define PSYCHO_STC_TAG_A    0xb800UL
0083 #define PSYCHO_STC_TAG_B    0xc800UL
0084 #define PSYCHO_STC_LINE_A   0xb900UL
0085 #define PSYCHO_STC_LINE_B   0xc900UL
0086 
0087 /* When an Uncorrectable Error or a PCI Error happens, we
0088  * interrogate the IOMMU state to see if it is the cause.
0089  */
0090 #define PSYCHO_IOMMU_CONTROL    0x0200UL
0091 #define  PSYCHO_IOMMU_CTRL_RESV     0xfffffffff9000000UL /* Reserved                      */
0092 #define  PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status      */
0093 #define  PSYCHO_IOMMU_CTRL_XLTEERR  0x0000000001000000UL /* Translation Error encountered */
0094 #define  PSYCHO_IOMMU_CTRL_LCKEN    0x0000000000800000UL /* Enable translation locking    */
0095 #define  PSYCHO_IOMMU_CTRL_LCKPTR   0x0000000000780000UL /* Translation lock pointer      */
0096 #define  PSYCHO_IOMMU_CTRL_TSBSZ    0x0000000000070000UL /* TSB Size                      */
0097 #define  PSYCHO_IOMMU_TSBSZ_1K      0x0000000000000000UL /* TSB Table 1024 8-byte entries */
0098 #define  PSYCHO_IOMMU_TSBSZ_2K      0x0000000000010000UL /* TSB Table 2048 8-byte entries */
0099 #define  PSYCHO_IOMMU_TSBSZ_4K      0x0000000000020000UL /* TSB Table 4096 8-byte entries */
0100 #define  PSYCHO_IOMMU_TSBSZ_8K      0x0000000000030000UL /* TSB Table 8192 8-byte entries */
0101 #define  PSYCHO_IOMMU_TSBSZ_16K     0x0000000000040000UL /* TSB Table 16k 8-byte entries  */
0102 #define  PSYCHO_IOMMU_TSBSZ_32K     0x0000000000050000UL /* TSB Table 32k 8-byte entries  */
0103 #define  PSYCHO_IOMMU_TSBSZ_64K     0x0000000000060000UL /* TSB Table 64k 8-byte entries  */
0104 #define  PSYCHO_IOMMU_TSBSZ_128K    0x0000000000070000UL /* TSB Table 128k 8-byte entries */
0105 #define  PSYCHO_IOMMU_CTRL_RESV2    0x000000000000fff8UL /* Reserved                      */
0106 #define  PSYCHO_IOMMU_CTRL_TBWSZ    0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
0107 #define  PSYCHO_IOMMU_CTRL_DENAB    0x0000000000000002UL /* Diagnostic mode enable        */
0108 #define  PSYCHO_IOMMU_CTRL_ENAB     0x0000000000000001UL /* IOMMU Enable                  */
0109 #define PSYCHO_IOMMU_TSBBASE    0x0208UL
0110 #define PSYCHO_IOMMU_FLUSH  0x0210UL
0111 #define PSYCHO_IOMMU_TAG    0xa580UL
0112 #define PSYCHO_IOMMU_DATA   0xa600UL
0113 
0114 /* Uncorrectable Errors.  Cause of the error and the address are
0115  * recorded in the UE_AFSR and UE_AFAR of PSYCHO.  They are errors
0116  * relating to UPA interface transactions.
0117  */
0118 #define PSYCHO_UE_AFSR  0x0030UL
0119 #define  PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause         */
0120 #define  PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause   */
0121 #define  PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause  */
0122 #define  PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause       */
0123 #define  PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
0124 #define  PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
0125 #define  PSYCHO_UEAFSR_RESV1    0x03ff000000000000UL /* Reserved                     */
0126 #define  PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer  */
0127 #define  PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset            */
0128 #define  PSYCHO_UEAFSR_MID  0x000000001f000000UL /* UPA MID causing the fault    */
0129 #define  PSYCHO_UEAFSR_BLK  0x0000000000800000UL /* Trans was block operation    */
0130 #define  PSYCHO_UEAFSR_RESV2    0x00000000007fffffUL /* Reserved                     */
0131 #define PSYCHO_UE_AFAR  0x0038UL
0132 
0133 static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
0134 {
0135     struct pci_pbm_info *pbm = dev_id;
0136     unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR;
0137     unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR;
0138     unsigned long afsr, afar, error_bits;
0139     int reported;
0140 
0141     /* Latch uncorrectable error status. */
0142     afar = upa_readq(afar_reg);
0143     afsr = upa_readq(afsr_reg);
0144 
0145     /* Clear the primary/secondary error status bits. */
0146     error_bits = afsr &
0147         (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR |
0148          PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
0149     if (!error_bits)
0150         return IRQ_NONE;
0151     upa_writeq(error_bits, afsr_reg);
0152 
0153     /* Log the error. */
0154     printk("%s: Uncorrectable Error, primary error type[%s]\n",
0155            pbm->name,
0156            (((error_bits & PSYCHO_UEAFSR_PPIO) ?
0157          "PIO" :
0158          ((error_bits & PSYCHO_UEAFSR_PDRD) ?
0159           "DMA Read" :
0160           ((error_bits & PSYCHO_UEAFSR_PDWR) ?
0161            "DMA Write" : "???")))));
0162     printk("%s: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
0163            pbm->name,
0164            (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
0165            (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
0166            (afsr & PSYCHO_UEAFSR_MID) >> 24UL,
0167            ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
0168     printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
0169     printk("%s: UE Secondary errors [", pbm->name);
0170     reported = 0;
0171     if (afsr & PSYCHO_UEAFSR_SPIO) {
0172         reported++;
0173         printk("(PIO)");
0174     }
0175     if (afsr & PSYCHO_UEAFSR_SDRD) {
0176         reported++;
0177         printk("(DMA Read)");
0178     }
0179     if (afsr & PSYCHO_UEAFSR_SDWR) {
0180         reported++;
0181         printk("(DMA Write)");
0182     }
0183     if (!reported)
0184         printk("(none)");
0185     printk("]\n");
0186 
0187     /* Interrogate both IOMMUs for error status. */
0188     psycho_check_iommu_error(pbm, afsr, afar, UE_ERR);
0189     if (pbm->sibling)
0190         psycho_check_iommu_error(pbm->sibling, afsr, afar, UE_ERR);
0191 
0192     return IRQ_HANDLED;
0193 }
0194 
0195 /* Correctable Errors. */
0196 #define PSYCHO_CE_AFSR  0x0040UL
0197 #define  PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause         */
0198 #define  PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause   */
0199 #define  PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause  */
0200 #define  PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause       */
0201 #define  PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
0202 #define  PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
0203 #define  PSYCHO_CEAFSR_RESV1    0x0300000000000000UL /* Reserved                     */
0204 #define  PSYCHO_CEAFSR_ESYND    0x00ff000000000000UL /* Syndrome Bits                */
0205 #define  PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer  */
0206 #define  PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset                */
0207 #define  PSYCHO_CEAFSR_MID  0x000000001f000000UL /* UPA MID causing the fault    */
0208 #define  PSYCHO_CEAFSR_BLK  0x0000000000800000UL /* Trans was block operation    */
0209 #define  PSYCHO_CEAFSR_RESV2    0x00000000007fffffUL /* Reserved                     */
0210 #define PSYCHO_CE_AFAR  0x0040UL
0211 
0212 static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
0213 {
0214     struct pci_pbm_info *pbm = dev_id;
0215     unsigned long afsr_reg = pbm->controller_regs + PSYCHO_CE_AFSR;
0216     unsigned long afar_reg = pbm->controller_regs + PSYCHO_CE_AFAR;
0217     unsigned long afsr, afar, error_bits;
0218     int reported;
0219 
0220     /* Latch error status. */
0221     afar = upa_readq(afar_reg);
0222     afsr = upa_readq(afsr_reg);
0223 
0224     /* Clear primary/secondary error status bits. */
0225     error_bits = afsr &
0226         (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR |
0227          PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
0228     if (!error_bits)
0229         return IRQ_NONE;
0230     upa_writeq(error_bits, afsr_reg);
0231 
0232     /* Log the error. */
0233     printk("%s: Correctable Error, primary error type[%s]\n",
0234            pbm->name,
0235            (((error_bits & PSYCHO_CEAFSR_PPIO) ?
0236          "PIO" :
0237          ((error_bits & PSYCHO_CEAFSR_PDRD) ?
0238           "DMA Read" :
0239           ((error_bits & PSYCHO_CEAFSR_PDWR) ?
0240            "DMA Write" : "???")))));
0241 
0242     /* XXX Use syndrome and afar to print out module string just like
0243      * XXX UDB CE trap handler does... -DaveM
0244      */
0245     printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
0246            "UPA_MID[%02lx] was_block(%d)\n",
0247            pbm->name,
0248            (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
0249            (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
0250            (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
0251            (afsr & PSYCHO_CEAFSR_MID) >> 24UL,
0252            ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
0253     printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
0254     printk("%s: CE Secondary errors [", pbm->name);
0255     reported = 0;
0256     if (afsr & PSYCHO_CEAFSR_SPIO) {
0257         reported++;
0258         printk("(PIO)");
0259     }
0260     if (afsr & PSYCHO_CEAFSR_SDRD) {
0261         reported++;
0262         printk("(DMA Read)");
0263     }
0264     if (afsr & PSYCHO_CEAFSR_SDWR) {
0265         reported++;
0266         printk("(DMA Write)");
0267     }
0268     if (!reported)
0269         printk("(none)");
0270     printk("]\n");
0271 
0272     return IRQ_HANDLED;
0273 }
0274 
0275 /* PCI Errors.  They are signalled by the PCI bus module since they
0276  * are associated with a specific bus segment.
0277  */
0278 #define PSYCHO_PCI_AFSR_A   0x2010UL
0279 #define PSYCHO_PCI_AFSR_B   0x4010UL
0280 #define PSYCHO_PCI_AFAR_A   0x2018UL
0281 #define PSYCHO_PCI_AFAR_B   0x4018UL
0282 
0283 /* XXX What about PowerFail/PowerManagement??? -DaveM */
0284 #define PSYCHO_ECC_CTRL     0x0020
0285 #define  PSYCHO_ECCCTRL_EE   0x8000000000000000UL /* Enable ECC Checking */
0286 #define  PSYCHO_ECCCTRL_UE   0x4000000000000000UL /* Enable UE Interrupts */
0287 #define  PSYCHO_ECCCTRL_CE   0x2000000000000000UL /* Enable CE INterrupts */
0288 static void psycho_register_error_handlers(struct pci_pbm_info *pbm)
0289 {
0290     struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node);
0291     unsigned long base = pbm->controller_regs;
0292     u64 tmp;
0293     int err;
0294 
0295     if (!op)
0296         return;
0297 
0298     /* Psycho interrupt property order is:
0299      * 0: PCIERR INO for this PBM
0300      * 1: UE ERR
0301      * 2: CE ERR
0302      * 3: POWER FAIL
0303      * 4: SPARE HARDWARE
0304      * 5: POWER MANAGEMENT
0305      */
0306 
0307     if (op->archdata.num_irqs < 6)
0308         return;
0309 
0310     /* We really mean to ignore the return result here.  Two
0311      * PCI controller share the same interrupt numbers and
0312      * drive the same front-end hardware.
0313      */
0314     err = request_irq(op->archdata.irqs[1], psycho_ue_intr, IRQF_SHARED,
0315               "PSYCHO_UE", pbm);
0316     err = request_irq(op->archdata.irqs[2], psycho_ce_intr, IRQF_SHARED,
0317               "PSYCHO_CE", pbm);
0318 
0319     /* This one, however, ought not to fail.  We can just warn
0320      * about it since the system can still operate properly even
0321      * if this fails.
0322      */
0323     err = request_irq(op->archdata.irqs[0], psycho_pcierr_intr, IRQF_SHARED,
0324               "PSYCHO_PCIERR", pbm);
0325     if (err)
0326         printk(KERN_WARNING "%s: Could not register PCIERR, "
0327                "err=%d\n", pbm->name, err);
0328 
0329     /* Enable UE and CE interrupts for controller. */
0330     upa_writeq((PSYCHO_ECCCTRL_EE |
0331             PSYCHO_ECCCTRL_UE |
0332             PSYCHO_ECCCTRL_CE), base + PSYCHO_ECC_CTRL);
0333 
0334     /* Enable PCI Error interrupts and clear error
0335      * bits for each PBM.
0336      */
0337     tmp = upa_readq(base + PSYCHO_PCIA_CTRL);
0338     tmp |= (PSYCHO_PCICTRL_SERR |
0339         PSYCHO_PCICTRL_SBH_ERR |
0340         PSYCHO_PCICTRL_EEN);
0341     tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
0342     upa_writeq(tmp, base + PSYCHO_PCIA_CTRL);
0343              
0344     tmp = upa_readq(base + PSYCHO_PCIB_CTRL);
0345     tmp |= (PSYCHO_PCICTRL_SERR |
0346         PSYCHO_PCICTRL_SBH_ERR |
0347         PSYCHO_PCICTRL_EEN);
0348     tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
0349     upa_writeq(tmp, base + PSYCHO_PCIB_CTRL);
0350 }
0351 
0352 /* PSYCHO boot time probing and initialization. */
0353 static void pbm_config_busmastering(struct pci_pbm_info *pbm)
0354 {
0355     u8 *addr;
0356 
0357     /* Set cache-line size to 64 bytes, this is actually
0358      * a nop but I do it for completeness.
0359      */
0360     addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
0361                     0, PCI_CACHE_LINE_SIZE);
0362     pci_config_write8(addr, 64 / sizeof(u32));
0363 
0364     /* Set PBM latency timer to 64 PCI clocks. */
0365     addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
0366                     0, PCI_LATENCY_TIMER);
0367     pci_config_write8(addr, 64);
0368 }
0369 
0370 static void psycho_scan_bus(struct pci_pbm_info *pbm,
0371                 struct device *parent)
0372 {
0373     pbm_config_busmastering(pbm);
0374     pbm->is_66mhz_capable = 0;
0375     pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
0376 
0377     /* After the PCI bus scan is complete, we can register
0378      * the error interrupt handlers.
0379      */
0380     psycho_register_error_handlers(pbm);
0381 }
0382 
0383 #define PSYCHO_IRQ_RETRY    0x1a00UL
0384 #define PSYCHO_PCIA_DIAG    0x2020UL
0385 #define PSYCHO_PCIB_DIAG    0x4020UL
0386 #define  PSYCHO_PCIDIAG_RESV     0xffffffffffffff80UL /* Reserved                     */
0387 #define  PSYCHO_PCIDIAG_DRETRY   0x0000000000000040UL /* Disable retry limit          */
0388 #define  PSYCHO_PCIDIAG_DISYNC   0x0000000000000020UL /* Disable DMA wr / irq sync    */
0389 #define  PSYCHO_PCIDIAG_DDWSYNC  0x0000000000000010UL /* Disable DMA wr / PIO rd sync */
0390 #define  PSYCHO_PCIDIAG_IDDPAR   0x0000000000000008UL /* Invert DMA data parity       */
0391 #define  PSYCHO_PCIDIAG_IPDPAR   0x0000000000000004UL /* Invert PIO data parity       */
0392 #define  PSYCHO_PCIDIAG_IPAPAR   0x0000000000000002UL /* Invert PIO address parity    */
0393 #define  PSYCHO_PCIDIAG_LPBACK   0x0000000000000001UL /* Enable loopback mode         */
0394 
0395 static void psycho_controller_hwinit(struct pci_pbm_info *pbm)
0396 {
0397     u64 tmp;
0398 
0399     upa_writeq(5, pbm->controller_regs + PSYCHO_IRQ_RETRY);
0400 
0401     /* Enable arbiter for all PCI slots. */
0402     tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_CTRL);
0403     tmp |= PSYCHO_PCICTRL_AEN;
0404     upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_CTRL);
0405 
0406     tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_CTRL);
0407     tmp |= PSYCHO_PCICTRL_AEN;
0408     upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_CTRL);
0409 
0410     /* Disable DMA write / PIO read synchronization on
0411      * both PCI bus segments.
0412      * [ U2P Erratum 1243770, STP2223BGA data sheet ]
0413      */
0414     tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_DIAG);
0415     tmp |= PSYCHO_PCIDIAG_DDWSYNC;
0416     upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_DIAG);
0417 
0418     tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_DIAG);
0419     tmp |= PSYCHO_PCIDIAG_DDWSYNC;
0420     upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_DIAG);
0421 }
0422 
0423 static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,
0424                    int is_pbm_a)
0425 {
0426     unsigned long base = pbm->controller_regs;
0427     u64 control;
0428 
0429     if (is_pbm_a) {
0430         pbm->stc.strbuf_control  = base + PSYCHO_STRBUF_CONTROL_A;
0431         pbm->stc.strbuf_pflush   = base + PSYCHO_STRBUF_FLUSH_A;
0432         pbm->stc.strbuf_fsync    = base + PSYCHO_STRBUF_FSYNC_A;
0433         pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_A;
0434         pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_A;
0435         pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_A;
0436     } else {
0437         pbm->stc.strbuf_control  = base + PSYCHO_STRBUF_CONTROL_B;
0438         pbm->stc.strbuf_pflush   = base + PSYCHO_STRBUF_FLUSH_B;
0439         pbm->stc.strbuf_fsync    = base + PSYCHO_STRBUF_FSYNC_B;
0440         pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_B;
0441         pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_B;
0442         pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_B;
0443     }
0444     /* PSYCHO's streaming buffer lacks ctx flushing. */
0445     pbm->stc.strbuf_ctxflush      = 0;
0446     pbm->stc.strbuf_ctxmatch_base = 0;
0447 
0448     pbm->stc.strbuf_flushflag = (volatile unsigned long *)
0449         ((((unsigned long)&pbm->stc.__flushflag_buf[0])
0450           + 63UL)
0451          & ~63UL);
0452     pbm->stc.strbuf_flushflag_pa = (unsigned long)
0453         __pa(pbm->stc.strbuf_flushflag);
0454 
0455     /* Enable the streaming buffer.  We have to be careful
0456      * just in case OBP left it with LRU locking enabled.
0457      *
0458      * It is possible to control if PBM will be rerun on
0459      * line misses.  Currently I just retain whatever setting
0460      * OBP left us with.  All checks so far show it having
0461      * a value of zero.
0462      */
0463 #undef PSYCHO_STRBUF_RERUN_ENABLE
0464 #undef PSYCHO_STRBUF_RERUN_DISABLE
0465     control = upa_readq(pbm->stc.strbuf_control);
0466     control |= PSYCHO_STRBUF_CTRL_ENAB;
0467     control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
0468 #ifdef PSYCHO_STRBUF_RERUN_ENABLE
0469     control &= ~(PSYCHO_STRBUF_CTRL_RRDIS);
0470 #else
0471 #ifdef PSYCHO_STRBUF_RERUN_DISABLE
0472     control |= PSYCHO_STRBUF_CTRL_RRDIS;
0473 #endif
0474 #endif
0475     upa_writeq(control, pbm->stc.strbuf_control);
0476 
0477     pbm->stc.strbuf_enabled = 1;
0478 }
0479 
0480 #define PSYCHO_IOSPACE_A    0x002000000UL
0481 #define PSYCHO_IOSPACE_B    0x002010000UL
0482 #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
0483 #define PSYCHO_MEMSPACE_A   0x100000000UL
0484 #define PSYCHO_MEMSPACE_B   0x180000000UL
0485 #define PSYCHO_MEMSPACE_SIZE    0x07fffffffUL
0486 
0487 static void psycho_pbm_init(struct pci_pbm_info *pbm,
0488                 struct platform_device *op, int is_pbm_a)
0489 {
0490     psycho_pbm_init_common(pbm, op, "PSYCHO", PBM_CHIP_TYPE_PSYCHO);
0491     psycho_pbm_strbuf_init(pbm, is_pbm_a);
0492     psycho_scan_bus(pbm, &op->dev);
0493 }
0494 
0495 static struct pci_pbm_info *psycho_find_sibling(u32 upa_portid)
0496 {
0497     struct pci_pbm_info *pbm;
0498 
0499     for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
0500         if (pbm->portid == upa_portid)
0501             return pbm;
0502     }
0503     return NULL;
0504 }
0505 
0506 #define PSYCHO_CONFIGSPACE  0x001000000UL
0507 
0508 static int psycho_probe(struct platform_device *op)
0509 {
0510     const struct linux_prom64_registers *pr_regs;
0511     struct device_node *dp = op->dev.of_node;
0512     struct pci_pbm_info *pbm;
0513     struct iommu *iommu;
0514     int is_pbm_a, err;
0515     u32 upa_portid;
0516 
0517     upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
0518 
0519     err = -ENOMEM;
0520     pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
0521     if (!pbm) {
0522         printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
0523         goto out_err;
0524     }
0525 
0526     pbm->sibling = psycho_find_sibling(upa_portid);
0527     if (pbm->sibling) {
0528         iommu = pbm->sibling->iommu;
0529     } else {
0530         iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
0531         if (!iommu) {
0532             printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
0533             goto out_free_controller;
0534         }
0535     }
0536 
0537     pbm->iommu = iommu;
0538     pbm->portid = upa_portid;
0539 
0540     pr_regs = of_get_property(dp, "reg", NULL);
0541     err = -ENODEV;
0542     if (!pr_regs) {
0543         printk(KERN_ERR PFX "No reg property.\n");
0544         goto out_free_iommu;
0545     }
0546 
0547     is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
0548 
0549     pbm->controller_regs = pr_regs[2].phys_addr;
0550     pbm->config_space = (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE);
0551 
0552     if (is_pbm_a) {
0553         pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_A;
0554         pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_A;
0555         pbm->pci_csr  = pbm->controller_regs + PSYCHO_PCIA_CTRL;
0556     } else {
0557         pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_B;
0558         pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_B;
0559         pbm->pci_csr  = pbm->controller_regs + PSYCHO_PCIB_CTRL;
0560     }
0561 
0562     psycho_controller_hwinit(pbm);
0563     if (!pbm->sibling) {
0564         err = psycho_iommu_init(pbm, 128, 0xc0000000,
0565                     0xffffffff, PSYCHO_CONTROL);
0566         if (err)
0567             goto out_free_iommu;
0568 
0569         /* If necessary, hook us up for starfire IRQ translations. */
0570         if (this_is_starfire)
0571             starfire_hookup(pbm->portid);
0572     }
0573 
0574     psycho_pbm_init(pbm, op, is_pbm_a);
0575 
0576     pbm->next = pci_pbm_root;
0577     pci_pbm_root = pbm;
0578 
0579     if (pbm->sibling)
0580         pbm->sibling->sibling = pbm;
0581 
0582     dev_set_drvdata(&op->dev, pbm);
0583 
0584     return 0;
0585 
0586 out_free_iommu:
0587     if (!pbm->sibling)
0588         kfree(pbm->iommu);
0589 
0590 out_free_controller:
0591     kfree(pbm);
0592 
0593 out_err:
0594     return err;
0595 }
0596 
0597 static const struct of_device_id psycho_match[] = {
0598     {
0599         .name = "pci",
0600         .compatible = "pci108e,8000",
0601     },
0602     {},
0603 };
0604 
0605 static struct platform_driver psycho_driver = {
0606     .driver = {
0607         .name = DRIVER_NAME,
0608         .of_match_table = psycho_match,
0609     },
0610     .probe      = psycho_probe,
0611 };
0612 
0613 static int __init psycho_init(void)
0614 {
0615     return platform_driver_register(&psycho_driver);
0616 }
0617 
0618 subsys_initcall(psycho_init);
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