sparc/kernel/pci_impl.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* pci_impl.h: Helper definitions for PCI controller support.
0003  *
0004  * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
0005  */
0006
0007 #ifndef PCI_IMPL_H
0008 #define PCI_IMPL_H
0009
0010 #include <linux/types.h>
0011 #include <linux/spinlock.h>
0012 #include <linux/pci.h>
0013 #include <linux/msi.h>
0014 #include <linux/of_device.h>
0015 #include <asm/io.h>
0016 #include <asm/prom.h>
0017 #include <asm/iommu.h>
0018
0019 /* The abstraction used here is that there are PCI controllers,
0020  * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
0021  * underneath.  Each PCI bus module uses an IOMMU (shared by both
0022  * PBMs of a controller, or per-PBM), and if a streaming buffer
0023  * is present, each PCI bus module has it's own. (ie. the IOMMU
0024  * might be shared between PBMs, the STC is never shared)
0025  * Furthermore, each PCI bus module controls it's own autonomous
0026  * PCI bus.
0027  */
0028
0029 #define PCI_STC_FLUSHFLAG_INIT(STC) \
0030     (*((STC)->strbuf_flushflag) = 0UL)
0031 #define PCI_STC_FLUSHFLAG_SET(STC) \
0032     (*((STC)->strbuf_flushflag) != 0UL)
0033
0034 #ifdef CONFIG_PCI_MSI
0035 struct pci_pbm_info;
0036 struct sparc64_msiq_ops {
0037     int (*get_head)(struct pci_pbm_info *pbm, unsigned long msiqid,
0038             unsigned long *head);
0039     int (*dequeue_msi)(struct pci_pbm_info *pbm, unsigned long msiqid,
0040                unsigned long *head, unsigned long *msi);
0041     int (*set_head)(struct pci_pbm_info *pbm, unsigned long msiqid,
0042             unsigned long head);
0043     int (*msi_setup)(struct pci_pbm_info *pbm, unsigned long msiqid,
0044              unsigned long msi, int is_msi64);
0045     int (*msi_teardown)(struct pci_pbm_info *pbm, unsigned long msi);
0046     int (*msiq_alloc)(struct pci_pbm_info *pbm);
0047     void (*msiq_free)(struct pci_pbm_info *pbm);
0048     int (*msiq_build_irq)(struct pci_pbm_info *pbm, unsigned long msiqid,
0049                   unsigned long devino);
0050 };
0051
0052 void sparc64_pbm_msi_init(struct pci_pbm_info *pbm,
0053               const struct sparc64_msiq_ops *ops);
0054
0055 struct sparc64_msiq_cookie {
0056     struct pci_pbm_info *pbm;
0057     unsigned long msiqid;
0058 };
0059 #endif
0060
0061 struct pci_pbm_info {
0062     struct pci_pbm_info     *next;
0063     struct pci_pbm_info     *sibling;
0064     int             index;
0065
0066     /* Physical address base of controller registers. */
0067     unsigned long           controller_regs;
0068
0069     /* Physical address base of PBM registers. */
0070     unsigned long           pbm_regs;
0071
0072     /* Physical address of DMA sync register, if any.  */
0073     unsigned long           sync_reg;
0074
0075     /* Opaque 32-bit system bus Port ID. */
0076     u32             portid;
0077
0078     /* Opaque 32-bit handle used for hypervisor calls.  */
0079     u32             devhandle;
0080
0081     /* Chipset version information. */
0082     int             chip_type;
0083 #define PBM_CHIP_TYPE_SABRE     1
0084 #define PBM_CHIP_TYPE_PSYCHO        2
0085 #define PBM_CHIP_TYPE_SCHIZO        3
0086 #define PBM_CHIP_TYPE_SCHIZO_PLUS   4
0087 #define PBM_CHIP_TYPE_TOMATILLO     5
0088     int             chip_version;
0089     int             chip_revision;
0090
0091     /* Name used for top-level resources. */
0092     const char          *name;
0093
0094     /* OBP specific information. */
0095     struct platform_device      *op;
0096     u64             ino_bitmap;
0097
0098     /* PBM I/O and Memory space resources. */
0099     struct resource         io_space;
0100     struct resource         mem_space;
0101     struct resource         mem64_space;
0102     struct resource         busn;
0103     /* offset */
0104     resource_size_t         io_offset;
0105     resource_size_t         mem_offset;
0106     resource_size_t         mem64_offset;
0107
0108     /* Base of PCI Config space, can be per-PBM or shared. */
0109     unsigned long           config_space;
0110
0111     /* This will be 12 on PCI-E controllers, 8 elsewhere.  */
0112     unsigned long           config_space_reg_bits;
0113
0114     unsigned long           pci_afsr;
0115     unsigned long           pci_afar;
0116     unsigned long           pci_csr;
0117
0118     /* State of 66MHz capabilities on this PBM. */
0119     int             is_66mhz_capable;
0120     int             all_devs_66mhz;
0121
0122 #ifdef CONFIG_PCI_MSI
0123     /* MSI info.  */
0124     u32             msiq_num;
0125     u32             msiq_ent_count;
0126     u32             msiq_first;
0127     u32             msiq_first_devino;
0128     u32             msiq_rotor;
0129     struct sparc64_msiq_cookie  *msiq_irq_cookies;
0130     u32             msi_num;
0131     u32             msi_first;
0132     u32             msi_data_mask;
0133     u32             msix_data_width;
0134     u64             msi32_start;
0135     u64             msi64_start;
0136     u32             msi32_len;
0137     u32             msi64_len;
0138     void                *msi_queues;
0139     unsigned long           *msi_bitmap;
0140     unsigned int            *msi_irq_table;
0141     int (*setup_msi_irq)(unsigned int *irq_p, struct pci_dev *pdev,
0142                  struct msi_desc *entry);
0143     void (*teardown_msi_irq)(unsigned int irq, struct pci_dev *pdev);
0144     const struct sparc64_msiq_ops   *msi_ops;
0145 #endif /* !(CONFIG_PCI_MSI) */
0146
0147     /* This PBM's streaming buffer. */
0148     struct strbuf           stc;
0149
0150     /* IOMMU state, potentially shared by both PBM segments. */
0151     struct iommu            *iommu;
0152
0153     /* Now things for the actual PCI bus probes. */
0154     unsigned int            pci_first_busno;
0155     unsigned int            pci_last_busno;
0156     struct pci_bus          *pci_bus;
0157     struct pci_ops          *pci_ops;
0158
0159     int             numa_node;
0160 };
0161
0162 extern struct pci_pbm_info *pci_pbm_root;
0163
0164 extern int pci_num_pbms;
0165
0166 /* PCI bus scanning and fixup support. */
0167 void pci_get_pbm_props(struct pci_pbm_info *pbm);
0168 struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
0169                  struct device *parent);
0170 void pci_determine_mem_io_space(struct pci_pbm_info *pbm);
0171
0172 /* Error reporting support. */
0173 void pci_scan_for_target_abort(struct pci_pbm_info *, struct pci_bus *);
0174 void pci_scan_for_master_abort(struct pci_pbm_info *, struct pci_bus *);
0175 void pci_scan_for_parity_error(struct pci_pbm_info *, struct pci_bus *);
0176
0177 /* Configuration space access. */
0178 void pci_config_read8(u8 *addr, u8 *ret);
0179 void pci_config_read16(u16 *addr, u16 *ret);
0180 void pci_config_read32(u32 *addr, u32 *ret);
0181 void pci_config_write8(u8 *addr, u8 val);
0182 void pci_config_write16(u16 *addr, u16 val);
0183 void pci_config_write32(u32 *addr, u32 val);
0184
0185 extern struct pci_ops sun4u_pci_ops;
0186 extern struct pci_ops sun4v_pci_ops;
0187
0188 extern volatile int pci_poke_in_progress;
0189 extern volatile int pci_poke_cpu;
0190 extern volatile int pci_poke_faulted;
0191
0192 #endif /* !(PCI_IMPL_H) */