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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* pci_common.c: PCI controller common support.
0003  *
0004  * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
0005  */
0006 
0007 #include <linux/string.h>
0008 #include <linux/slab.h>
0009 #include <linux/pci.h>
0010 #include <linux/device.h>
0011 #include <linux/of_device.h>
0012 
0013 #include <asm/prom.h>
0014 #include <asm/oplib.h>
0015 
0016 #include "pci_impl.h"
0017 #include "pci_sun4v.h"
0018 
0019 static int config_out_of_range(struct pci_pbm_info *pbm,
0020                    unsigned long bus,
0021                    unsigned long devfn,
0022                    unsigned long reg)
0023 {
0024     if (bus < pbm->pci_first_busno ||
0025         bus > pbm->pci_last_busno)
0026         return 1;
0027     return 0;
0028 }
0029 
0030 static void *sun4u_config_mkaddr(struct pci_pbm_info *pbm,
0031                  unsigned long bus,
0032                  unsigned long devfn,
0033                  unsigned long reg)
0034 {
0035     unsigned long rbits = pbm->config_space_reg_bits;
0036 
0037     if (config_out_of_range(pbm, bus, devfn, reg))
0038         return NULL;
0039 
0040     reg = (reg & ((1 << rbits) - 1));
0041     devfn <<= rbits;
0042     bus <<= rbits + 8;
0043 
0044     return (void *) (pbm->config_space | bus | devfn | reg);
0045 }
0046 
0047 /* At least on Sabre, it is necessary to access all PCI host controller
0048  * registers at their natural size, otherwise zeros are returned.
0049  * Strange but true, and I see no language in the UltraSPARC-IIi
0050  * programmer's manual that mentions this even indirectly.
0051  */
0052 static int sun4u_read_pci_cfg_host(struct pci_pbm_info *pbm,
0053                    unsigned char bus, unsigned int devfn,
0054                    int where, int size, u32 *value)
0055 {
0056     u32 tmp32, *addr;
0057     u16 tmp16;
0058     u8 tmp8;
0059 
0060     addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
0061     if (!addr)
0062         return PCIBIOS_SUCCESSFUL;
0063 
0064     switch (size) {
0065     case 1:
0066         if (where < 8) {
0067             unsigned long align = (unsigned long) addr;
0068 
0069             align &= ~1;
0070             pci_config_read16((u16 *)align, &tmp16);
0071             if (where & 1)
0072                 *value = tmp16 >> 8;
0073             else
0074                 *value = tmp16 & 0xff;
0075         } else {
0076             pci_config_read8((u8 *)addr, &tmp8);
0077             *value = (u32) tmp8;
0078         }
0079         break;
0080 
0081     case 2:
0082         if (where < 8) {
0083             pci_config_read16((u16 *)addr, &tmp16);
0084             *value = (u32) tmp16;
0085         } else {
0086             pci_config_read8((u8 *)addr, &tmp8);
0087             *value = (u32) tmp8;
0088             pci_config_read8(((u8 *)addr) + 1, &tmp8);
0089             *value |= ((u32) tmp8) << 8;
0090         }
0091         break;
0092 
0093     case 4:
0094         tmp32 = 0xffffffff;
0095         sun4u_read_pci_cfg_host(pbm, bus, devfn,
0096                     where, 2, &tmp32);
0097         *value = tmp32;
0098 
0099         tmp32 = 0xffffffff;
0100         sun4u_read_pci_cfg_host(pbm, bus, devfn,
0101                     where + 2, 2, &tmp32);
0102         *value |= tmp32 << 16;
0103         break;
0104     }
0105     return PCIBIOS_SUCCESSFUL;
0106 }
0107 
0108 static int sun4u_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
0109                   int where, int size, u32 *value)
0110 {
0111     struct pci_pbm_info *pbm = bus_dev->sysdata;
0112     unsigned char bus = bus_dev->number;
0113     u32 *addr;
0114     u16 tmp16;
0115     u8 tmp8;
0116 
0117     switch (size) {
0118     case 1:
0119         *value = 0xff;
0120         break;
0121     case 2:
0122         *value = 0xffff;
0123         break;
0124     case 4:
0125         *value = 0xffffffff;
0126         break;
0127     }
0128 
0129     if (!bus_dev->number && !PCI_SLOT(devfn))
0130         return sun4u_read_pci_cfg_host(pbm, bus, devfn, where,
0131                            size, value);
0132 
0133     addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
0134     if (!addr)
0135         return PCIBIOS_SUCCESSFUL;
0136 
0137     switch (size) {
0138     case 1:
0139         pci_config_read8((u8 *)addr, &tmp8);
0140         *value = (u32) tmp8;
0141         break;
0142 
0143     case 2:
0144         if (where & 0x01) {
0145             printk("pci_read_config_word: misaligned reg [%x]\n",
0146                    where);
0147             return PCIBIOS_SUCCESSFUL;
0148         }
0149         pci_config_read16((u16 *)addr, &tmp16);
0150         *value = (u32) tmp16;
0151         break;
0152 
0153     case 4:
0154         if (where & 0x03) {
0155             printk("pci_read_config_dword: misaligned reg [%x]\n",
0156                    where);
0157             return PCIBIOS_SUCCESSFUL;
0158         }
0159         pci_config_read32(addr, value);
0160         break;
0161     }
0162     return PCIBIOS_SUCCESSFUL;
0163 }
0164 
0165 static int sun4u_write_pci_cfg_host(struct pci_pbm_info *pbm,
0166                     unsigned char bus, unsigned int devfn,
0167                     int where, int size, u32 value)
0168 {
0169     u32 *addr;
0170 
0171     addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
0172     if (!addr)
0173         return PCIBIOS_SUCCESSFUL;
0174 
0175     switch (size) {
0176     case 1:
0177         if (where < 8) {
0178             unsigned long align = (unsigned long) addr;
0179             u16 tmp16;
0180 
0181             align &= ~1;
0182             pci_config_read16((u16 *)align, &tmp16);
0183             if (where & 1) {
0184                 tmp16 &= 0x00ff;
0185                 tmp16 |= value << 8;
0186             } else {
0187                 tmp16 &= 0xff00;
0188                 tmp16 |= value;
0189             }
0190             pci_config_write16((u16 *)align, tmp16);
0191         } else
0192             pci_config_write8((u8 *)addr, value);
0193         break;
0194     case 2:
0195         if (where < 8) {
0196             pci_config_write16((u16 *)addr, value);
0197         } else {
0198             pci_config_write8((u8 *)addr, value & 0xff);
0199             pci_config_write8(((u8 *)addr) + 1, value >> 8);
0200         }
0201         break;
0202     case 4:
0203         sun4u_write_pci_cfg_host(pbm, bus, devfn,
0204                      where, 2, value & 0xffff);
0205         sun4u_write_pci_cfg_host(pbm, bus, devfn,
0206                      where + 2, 2, value >> 16);
0207         break;
0208     }
0209     return PCIBIOS_SUCCESSFUL;
0210 }
0211 
0212 static int sun4u_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
0213                    int where, int size, u32 value)
0214 {
0215     struct pci_pbm_info *pbm = bus_dev->sysdata;
0216     unsigned char bus = bus_dev->number;
0217     u32 *addr;
0218 
0219     if (!bus_dev->number && !PCI_SLOT(devfn))
0220         return sun4u_write_pci_cfg_host(pbm, bus, devfn, where,
0221                         size, value);
0222 
0223     addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
0224     if (!addr)
0225         return PCIBIOS_SUCCESSFUL;
0226 
0227     switch (size) {
0228     case 1:
0229         pci_config_write8((u8 *)addr, value);
0230         break;
0231 
0232     case 2:
0233         if (where & 0x01) {
0234             printk("pci_write_config_word: misaligned reg [%x]\n",
0235                    where);
0236             return PCIBIOS_SUCCESSFUL;
0237         }
0238         pci_config_write16((u16 *)addr, value);
0239         break;
0240 
0241     case 4:
0242         if (where & 0x03) {
0243             printk("pci_write_config_dword: misaligned reg [%x]\n",
0244                    where);
0245             return PCIBIOS_SUCCESSFUL;
0246         }
0247         pci_config_write32(addr, value);
0248     }
0249     return PCIBIOS_SUCCESSFUL;
0250 }
0251 
0252 struct pci_ops sun4u_pci_ops = {
0253     .read =     sun4u_read_pci_cfg,
0254     .write =    sun4u_write_pci_cfg,
0255 };
0256 
0257 static int sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
0258                   int where, int size, u32 *value)
0259 {
0260     struct pci_pbm_info *pbm = bus_dev->sysdata;
0261     u32 devhandle = pbm->devhandle;
0262     unsigned int bus = bus_dev->number;
0263     unsigned int device = PCI_SLOT(devfn);
0264     unsigned int func = PCI_FUNC(devfn);
0265     unsigned long ret;
0266 
0267     if (config_out_of_range(pbm, bus, devfn, where)) {
0268         ret = ~0UL;
0269     } else {
0270         ret = pci_sun4v_config_get(devhandle,
0271                 HV_PCI_DEVICE_BUILD(bus, device, func),
0272                 where, size);
0273     }
0274     switch (size) {
0275     case 1:
0276         *value = ret & 0xff;
0277         break;
0278     case 2:
0279         *value = ret & 0xffff;
0280         break;
0281     case 4:
0282         *value = ret & 0xffffffff;
0283         break;
0284     }
0285 
0286 
0287     return PCIBIOS_SUCCESSFUL;
0288 }
0289 
0290 static int sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
0291                    int where, int size, u32 value)
0292 {
0293     struct pci_pbm_info *pbm = bus_dev->sysdata;
0294     u32 devhandle = pbm->devhandle;
0295     unsigned int bus = bus_dev->number;
0296     unsigned int device = PCI_SLOT(devfn);
0297     unsigned int func = PCI_FUNC(devfn);
0298 
0299     if (config_out_of_range(pbm, bus, devfn, where)) {
0300         /* Do nothing. */
0301     } else {
0302         /* We don't check for hypervisor errors here, but perhaps
0303          * we should and influence our return value depending upon
0304          * what kind of error is thrown.
0305          */
0306         pci_sun4v_config_put(devhandle,
0307                      HV_PCI_DEVICE_BUILD(bus, device, func),
0308                      where, size, value);
0309     }
0310     return PCIBIOS_SUCCESSFUL;
0311 }
0312 
0313 struct pci_ops sun4v_pci_ops = {
0314     .read =     sun4v_read_pci_cfg,
0315     .write =    sun4v_write_pci_cfg,
0316 };
0317 
0318 void pci_get_pbm_props(struct pci_pbm_info *pbm)
0319 {
0320     const u32 *val = of_get_property(pbm->op->dev.of_node, "bus-range", NULL);
0321 
0322     pbm->pci_first_busno = val[0];
0323     pbm->pci_last_busno = val[1];
0324 
0325     val = of_get_property(pbm->op->dev.of_node, "ino-bitmap", NULL);
0326     if (val) {
0327         pbm->ino_bitmap = (((u64)val[1] << 32UL) |
0328                    ((u64)val[0] <<  0UL));
0329     }
0330 }
0331 
0332 static void pci_register_iommu_region(struct pci_pbm_info *pbm)
0333 {
0334     const u32 *vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma",
0335                       NULL);
0336 
0337     if (vdma) {
0338         struct resource *rp = kzalloc(sizeof(*rp), GFP_KERNEL);
0339 
0340         if (!rp) {
0341             pr_info("%s: Cannot allocate IOMMU resource.\n",
0342                 pbm->name);
0343             return;
0344         }
0345         rp->name = "IOMMU";
0346         rp->start = pbm->mem_space.start + (unsigned long) vdma[0];
0347         rp->end = rp->start + (unsigned long) vdma[1] - 1UL;
0348         rp->flags = IORESOURCE_BUSY;
0349         if (request_resource(&pbm->mem_space, rp)) {
0350             pr_info("%s: Unable to request IOMMU resource.\n",
0351                 pbm->name);
0352             kfree(rp);
0353         }
0354     }
0355 }
0356 
0357 void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
0358 {
0359     const struct linux_prom_pci_ranges *pbm_ranges;
0360     int i, saw_mem, saw_io;
0361     int num_pbm_ranges;
0362 
0363     /* Corresponding generic code in of_pci_get_host_bridge_resources() */
0364 
0365     saw_mem = saw_io = 0;
0366     pbm_ranges = of_get_property(pbm->op->dev.of_node, "ranges", &i);
0367     if (!pbm_ranges) {
0368         prom_printf("PCI: Fatal error, missing PBM ranges property "
0369                 " for %s\n",
0370                 pbm->name);
0371         prom_halt();
0372     }
0373 
0374     num_pbm_ranges = i / sizeof(*pbm_ranges);
0375     memset(&pbm->mem64_space, 0, sizeof(struct resource));
0376 
0377     for (i = 0; i < num_pbm_ranges; i++) {
0378         const struct linux_prom_pci_ranges *pr = &pbm_ranges[i];
0379         unsigned long a, size, region_a;
0380         u32 parent_phys_hi, parent_phys_lo;
0381         u32 child_phys_mid, child_phys_lo;
0382         u32 size_hi, size_lo;
0383         int type;
0384 
0385         parent_phys_hi = pr->parent_phys_hi;
0386         parent_phys_lo = pr->parent_phys_lo;
0387         child_phys_mid = pr->child_phys_mid;
0388         child_phys_lo = pr->child_phys_lo;
0389         if (tlb_type == hypervisor)
0390             parent_phys_hi &= 0x0fffffff;
0391 
0392         size_hi = pr->size_hi;
0393         size_lo = pr->size_lo;
0394 
0395         type = (pr->child_phys_hi >> 24) & 0x3;
0396         a = (((unsigned long)parent_phys_hi << 32UL) |
0397              ((unsigned long)parent_phys_lo  <<  0UL));
0398         region_a = (((unsigned long)child_phys_mid << 32UL) |
0399              ((unsigned long)child_phys_lo  <<  0UL));
0400         size = (((unsigned long)size_hi << 32UL) |
0401             ((unsigned long)size_lo  <<  0UL));
0402 
0403         switch (type) {
0404         case 0:
0405             /* PCI config space, 16MB */
0406             pbm->config_space = a;
0407             break;
0408 
0409         case 1:
0410             /* 16-bit IO space, 16MB */
0411             pbm->io_space.start = a;
0412             pbm->io_space.end = a + size - 1UL;
0413             pbm->io_space.flags = IORESOURCE_IO;
0414             pbm->io_offset = a - region_a;
0415             saw_io = 1;
0416             break;
0417 
0418         case 2:
0419             /* 32-bit MEM space, 2GB */
0420             pbm->mem_space.start = a;
0421             pbm->mem_space.end = a + size - 1UL;
0422             pbm->mem_space.flags = IORESOURCE_MEM;
0423             pbm->mem_offset = a - region_a;
0424             saw_mem = 1;
0425             break;
0426 
0427         case 3:
0428             /* 64-bit MEM handling */
0429             pbm->mem64_space.start = a;
0430             pbm->mem64_space.end = a + size - 1UL;
0431             pbm->mem64_space.flags = IORESOURCE_MEM;
0432             pbm->mem64_offset = a - region_a;
0433             saw_mem = 1;
0434             break;
0435 
0436         default:
0437             break;
0438         }
0439     }
0440 
0441     if (!saw_io || !saw_mem) {
0442         prom_printf("%s: Fatal error, missing %s PBM range.\n",
0443                 pbm->name,
0444                 (!saw_io ? "IO" : "MEM"));
0445         prom_halt();
0446     }
0447 
0448     if (pbm->io_space.flags)
0449         printk("%s: PCI IO %pR offset %llx\n",
0450                pbm->name, &pbm->io_space, pbm->io_offset);
0451     if (pbm->mem_space.flags)
0452         printk("%s: PCI MEM %pR offset %llx\n",
0453                pbm->name, &pbm->mem_space, pbm->mem_offset);
0454     if (pbm->mem64_space.flags && pbm->mem_space.flags) {
0455         if (pbm->mem64_space.start <= pbm->mem_space.end)
0456             pbm->mem64_space.start = pbm->mem_space.end + 1;
0457         if (pbm->mem64_space.start > pbm->mem64_space.end)
0458             pbm->mem64_space.flags = 0;
0459     }
0460 
0461     if (pbm->mem64_space.flags)
0462         printk("%s: PCI MEM64 %pR offset %llx\n",
0463                pbm->name, &pbm->mem64_space, pbm->mem64_offset);
0464 
0465     pbm->io_space.name = pbm->mem_space.name = pbm->name;
0466     pbm->mem64_space.name = pbm->name;
0467 
0468     request_resource(&ioport_resource, &pbm->io_space);
0469     request_resource(&iomem_resource, &pbm->mem_space);
0470     if (pbm->mem64_space.flags)
0471         request_resource(&iomem_resource, &pbm->mem64_space);
0472 
0473     pci_register_iommu_region(pbm);
0474 }
0475 
0476 /* Generic helper routines for PCI error reporting. */
0477 void pci_scan_for_target_abort(struct pci_pbm_info *pbm,
0478                    struct pci_bus *pbus)
0479 {
0480     struct pci_dev *pdev;
0481     struct pci_bus *bus;
0482 
0483     list_for_each_entry(pdev, &pbus->devices, bus_list) {
0484         u16 status, error_bits;
0485 
0486         pci_read_config_word(pdev, PCI_STATUS, &status);
0487         error_bits =
0488             (status & (PCI_STATUS_SIG_TARGET_ABORT |
0489                    PCI_STATUS_REC_TARGET_ABORT));
0490         if (error_bits) {
0491             pci_write_config_word(pdev, PCI_STATUS, error_bits);
0492             pci_info(pdev, "%s: Device saw Target Abort [%016x]\n",
0493                  pbm->name, status);
0494         }
0495     }
0496 
0497     list_for_each_entry(bus, &pbus->children, node)
0498         pci_scan_for_target_abort(pbm, bus);
0499 }
0500 
0501 void pci_scan_for_master_abort(struct pci_pbm_info *pbm,
0502                    struct pci_bus *pbus)
0503 {
0504     struct pci_dev *pdev;
0505     struct pci_bus *bus;
0506 
0507     list_for_each_entry(pdev, &pbus->devices, bus_list) {
0508         u16 status, error_bits;
0509 
0510         pci_read_config_word(pdev, PCI_STATUS, &status);
0511         error_bits =
0512             (status & (PCI_STATUS_REC_MASTER_ABORT));
0513         if (error_bits) {
0514             pci_write_config_word(pdev, PCI_STATUS, error_bits);
0515             pci_info(pdev, "%s: Device received Master Abort "
0516                  "[%016x]\n", pbm->name, status);
0517         }
0518     }
0519 
0520     list_for_each_entry(bus, &pbus->children, node)
0521         pci_scan_for_master_abort(pbm, bus);
0522 }
0523 
0524 void pci_scan_for_parity_error(struct pci_pbm_info *pbm,
0525                    struct pci_bus *pbus)
0526 {
0527     struct pci_dev *pdev;
0528     struct pci_bus *bus;
0529 
0530     list_for_each_entry(pdev, &pbus->devices, bus_list) {
0531         u16 status, error_bits;
0532 
0533         pci_read_config_word(pdev, PCI_STATUS, &status);
0534         error_bits =
0535             (status & (PCI_STATUS_PARITY |
0536                    PCI_STATUS_DETECTED_PARITY));
0537         if (error_bits) {
0538             pci_write_config_word(pdev, PCI_STATUS, error_bits);
0539             pci_info(pdev, "%s: Device saw Parity Error [%016x]\n",
0540                  pbm->name, status);
0541         }
0542     }
0543 
0544     list_for_each_entry(bus, &pbus->children, node)
0545         pci_scan_for_parity_error(pbm, bus);
0546 }
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