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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* pci.c: UltraSparc PCI controller support.
0003  *
0004  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
0005  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
0006  * Copyright (C) 1999 Jakub Jelinek   (jj@ultra.linux.cz)
0007  *
0008  * OF tree based PCI bus probing taken from the PowerPC port
0009  * with minor modifications, see there for credits.
0010  */
0011 
0012 #include <linux/export.h>
0013 #include <linux/kernel.h>
0014 #include <linux/string.h>
0015 #include <linux/sched.h>
0016 #include <linux/capability.h>
0017 #include <linux/errno.h>
0018 #include <linux/pci.h>
0019 #include <linux/msi.h>
0020 #include <linux/irq.h>
0021 #include <linux/init.h>
0022 #include <linux/of.h>
0023 #include <linux/of_device.h>
0024 #include <linux/pgtable.h>
0025 
0026 #include <linux/uaccess.h>
0027 #include <asm/irq.h>
0028 #include <asm/prom.h>
0029 #include <asm/apb.h>
0030 
0031 #include "pci_impl.h"
0032 #include "kernel.h"
0033 
0034 /* List of all PCI controllers found in the system. */
0035 struct pci_pbm_info *pci_pbm_root = NULL;
0036 
0037 /* Each PBM found gets a unique index. */
0038 int pci_num_pbms = 0;
0039 
0040 volatile int pci_poke_in_progress;
0041 volatile int pci_poke_cpu = -1;
0042 volatile int pci_poke_faulted;
0043 
0044 static DEFINE_SPINLOCK(pci_poke_lock);
0045 
0046 void pci_config_read8(u8 *addr, u8 *ret)
0047 {
0048     unsigned long flags;
0049     u8 byte;
0050 
0051     spin_lock_irqsave(&pci_poke_lock, flags);
0052     pci_poke_cpu = smp_processor_id();
0053     pci_poke_in_progress = 1;
0054     pci_poke_faulted = 0;
0055     __asm__ __volatile__("membar #Sync\n\t"
0056                  "lduba [%1] %2, %0\n\t"
0057                  "membar #Sync"
0058                  : "=r" (byte)
0059                  : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
0060                  : "memory");
0061     pci_poke_in_progress = 0;
0062     pci_poke_cpu = -1;
0063     if (!pci_poke_faulted)
0064         *ret = byte;
0065     spin_unlock_irqrestore(&pci_poke_lock, flags);
0066 }
0067 
0068 void pci_config_read16(u16 *addr, u16 *ret)
0069 {
0070     unsigned long flags;
0071     u16 word;
0072 
0073     spin_lock_irqsave(&pci_poke_lock, flags);
0074     pci_poke_cpu = smp_processor_id();
0075     pci_poke_in_progress = 1;
0076     pci_poke_faulted = 0;
0077     __asm__ __volatile__("membar #Sync\n\t"
0078                  "lduha [%1] %2, %0\n\t"
0079                  "membar #Sync"
0080                  : "=r" (word)
0081                  : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
0082                  : "memory");
0083     pci_poke_in_progress = 0;
0084     pci_poke_cpu = -1;
0085     if (!pci_poke_faulted)
0086         *ret = word;
0087     spin_unlock_irqrestore(&pci_poke_lock, flags);
0088 }
0089 
0090 void pci_config_read32(u32 *addr, u32 *ret)
0091 {
0092     unsigned long flags;
0093     u32 dword;
0094 
0095     spin_lock_irqsave(&pci_poke_lock, flags);
0096     pci_poke_cpu = smp_processor_id();
0097     pci_poke_in_progress = 1;
0098     pci_poke_faulted = 0;
0099     __asm__ __volatile__("membar #Sync\n\t"
0100                  "lduwa [%1] %2, %0\n\t"
0101                  "membar #Sync"
0102                  : "=r" (dword)
0103                  : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
0104                  : "memory");
0105     pci_poke_in_progress = 0;
0106     pci_poke_cpu = -1;
0107     if (!pci_poke_faulted)
0108         *ret = dword;
0109     spin_unlock_irqrestore(&pci_poke_lock, flags);
0110 }
0111 
0112 void pci_config_write8(u8 *addr, u8 val)
0113 {
0114     unsigned long flags;
0115 
0116     spin_lock_irqsave(&pci_poke_lock, flags);
0117     pci_poke_cpu = smp_processor_id();
0118     pci_poke_in_progress = 1;
0119     pci_poke_faulted = 0;
0120     __asm__ __volatile__("membar #Sync\n\t"
0121                  "stba %0, [%1] %2\n\t"
0122                  "membar #Sync"
0123                  : /* no outputs */
0124                  : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
0125                  : "memory");
0126     pci_poke_in_progress = 0;
0127     pci_poke_cpu = -1;
0128     spin_unlock_irqrestore(&pci_poke_lock, flags);
0129 }
0130 
0131 void pci_config_write16(u16 *addr, u16 val)
0132 {
0133     unsigned long flags;
0134 
0135     spin_lock_irqsave(&pci_poke_lock, flags);
0136     pci_poke_cpu = smp_processor_id();
0137     pci_poke_in_progress = 1;
0138     pci_poke_faulted = 0;
0139     __asm__ __volatile__("membar #Sync\n\t"
0140                  "stha %0, [%1] %2\n\t"
0141                  "membar #Sync"
0142                  : /* no outputs */
0143                  : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
0144                  : "memory");
0145     pci_poke_in_progress = 0;
0146     pci_poke_cpu = -1;
0147     spin_unlock_irqrestore(&pci_poke_lock, flags);
0148 }
0149 
0150 void pci_config_write32(u32 *addr, u32 val)
0151 {
0152     unsigned long flags;
0153 
0154     spin_lock_irqsave(&pci_poke_lock, flags);
0155     pci_poke_cpu = smp_processor_id();
0156     pci_poke_in_progress = 1;
0157     pci_poke_faulted = 0;
0158     __asm__ __volatile__("membar #Sync\n\t"
0159                  "stwa %0, [%1] %2\n\t"
0160                  "membar #Sync"
0161                  : /* no outputs */
0162                  : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
0163                  : "memory");
0164     pci_poke_in_progress = 0;
0165     pci_poke_cpu = -1;
0166     spin_unlock_irqrestore(&pci_poke_lock, flags);
0167 }
0168 
0169 static int ofpci_verbose;
0170 
0171 static int __init ofpci_debug(char *str)
0172 {
0173     int val = 0;
0174 
0175     get_option(&str, &val);
0176     if (val)
0177         ofpci_verbose = 1;
0178     return 1;
0179 }
0180 
0181 __setup("ofpci_debug=", ofpci_debug);
0182 
0183 static unsigned long pci_parse_of_flags(u32 addr0)
0184 {
0185     unsigned long flags = 0;
0186 
0187     if (addr0 & 0x02000000) {
0188         flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
0189         flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
0190         if (addr0 & 0x01000000)
0191             flags |= IORESOURCE_MEM_64
0192                  | PCI_BASE_ADDRESS_MEM_TYPE_64;
0193         if (addr0 & 0x40000000)
0194             flags |= IORESOURCE_PREFETCH
0195                  | PCI_BASE_ADDRESS_MEM_PREFETCH;
0196     } else if (addr0 & 0x01000000)
0197         flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
0198     return flags;
0199 }
0200 
0201 /* The of_device layer has translated all of the assigned-address properties
0202  * into physical address resources, we only have to figure out the register
0203  * mapping.
0204  */
0205 static void pci_parse_of_addrs(struct platform_device *op,
0206                    struct device_node *node,
0207                    struct pci_dev *dev)
0208 {
0209     struct resource *op_res;
0210     const u32 *addrs;
0211     int proplen;
0212 
0213     addrs = of_get_property(node, "assigned-addresses", &proplen);
0214     if (!addrs)
0215         return;
0216     if (ofpci_verbose)
0217         pci_info(dev, "    parse addresses (%d bytes) @ %p\n",
0218              proplen, addrs);
0219     op_res = &op->resource[0];
0220     for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
0221         struct resource *res;
0222         unsigned long flags;
0223         int i;
0224 
0225         flags = pci_parse_of_flags(addrs[0]);
0226         if (!flags)
0227             continue;
0228         i = addrs[0] & 0xff;
0229         if (ofpci_verbose)
0230             pci_info(dev, "  start: %llx, end: %llx, i: %x\n",
0231                  op_res->start, op_res->end, i);
0232 
0233         if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
0234             res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
0235         } else if (i == dev->rom_base_reg) {
0236             res = &dev->resource[PCI_ROM_RESOURCE];
0237             flags |= IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
0238         } else {
0239             pci_err(dev, "bad cfg reg num 0x%x\n", i);
0240             continue;
0241         }
0242         res->start = op_res->start;
0243         res->end = op_res->end;
0244         res->flags = flags;
0245         res->name = pci_name(dev);
0246 
0247         pci_info(dev, "reg 0x%x: %pR\n", i, res);
0248     }
0249 }
0250 
0251 static void pci_init_dev_archdata(struct dev_archdata *sd, void *iommu,
0252                   void *stc, void *host_controller,
0253                   struct platform_device  *op,
0254                   int numa_node)
0255 {
0256     sd->iommu = iommu;
0257     sd->stc = stc;
0258     sd->host_controller = host_controller;
0259     sd->op = op;
0260     sd->numa_node = numa_node;
0261 }
0262 
0263 static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
0264                      struct device_node *node,
0265                      struct pci_bus *bus, int devfn)
0266 {
0267     struct dev_archdata *sd;
0268     struct platform_device *op;
0269     struct pci_dev *dev;
0270     u32 class;
0271 
0272     dev = pci_alloc_dev(bus);
0273     if (!dev)
0274         return NULL;
0275 
0276     op = of_find_device_by_node(node);
0277     sd = &dev->dev.archdata;
0278     pci_init_dev_archdata(sd, pbm->iommu, &pbm->stc, pbm, op,
0279                   pbm->numa_node);
0280     sd = &op->dev.archdata;
0281     sd->iommu = pbm->iommu;
0282     sd->stc = &pbm->stc;
0283     sd->numa_node = pbm->numa_node;
0284 
0285     if (of_node_name_eq(node, "ebus"))
0286         of_propagate_archdata(op);
0287 
0288     if (ofpci_verbose)
0289         pci_info(bus,"    create device, devfn: %x, type: %s\n",
0290              devfn, of_node_get_device_type(node));
0291 
0292     dev->sysdata = node;
0293     dev->dev.parent = bus->bridge;
0294     dev->dev.bus = &pci_bus_type;
0295     dev->dev.of_node = of_node_get(node);
0296     dev->devfn = devfn;
0297     dev->multifunction = 0;     /* maybe a lie? */
0298     set_pcie_port_type(dev);
0299 
0300     pci_dev_assign_slot(dev);
0301     dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
0302     dev->device = of_getintprop_default(node, "device-id", 0xffff);
0303     dev->subsystem_vendor =
0304         of_getintprop_default(node, "subsystem-vendor-id", 0);
0305     dev->subsystem_device =
0306         of_getintprop_default(node, "subsystem-id", 0);
0307 
0308     dev->cfg_size = pci_cfg_space_size(dev);
0309 
0310     /* We can't actually use the firmware value, we have
0311      * to read what is in the register right now.  One
0312      * reason is that in the case of IDE interfaces the
0313      * firmware can sample the value before the the IDE
0314      * interface is programmed into native mode.
0315      */
0316     pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
0317     dev->class = class >> 8;
0318     dev->revision = class & 0xff;
0319 
0320     dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
0321         dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
0322 
0323     /* I have seen IDE devices which will not respond to
0324      * the bmdma simplex check reads if bus mastering is
0325      * disabled.
0326      */
0327     if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
0328         pci_set_master(dev);
0329 
0330     dev->current_state = PCI_UNKNOWN;   /* unknown power state */
0331     dev->error_state = pci_channel_io_normal;
0332     dev->dma_mask = 0xffffffff;
0333 
0334     if (of_node_name_eq(node, "pci")) {
0335         /* a PCI-PCI bridge */
0336         dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
0337         dev->rom_base_reg = PCI_ROM_ADDRESS1;
0338     } else if (of_node_is_type(node, "cardbus")) {
0339         dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
0340     } else {
0341         dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
0342         dev->rom_base_reg = PCI_ROM_ADDRESS;
0343 
0344         dev->irq = sd->op->archdata.irqs[0];
0345         if (dev->irq == 0xffffffff)
0346             dev->irq = PCI_IRQ_NONE;
0347     }
0348 
0349     pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
0350          dev->vendor, dev->device, dev->hdr_type, dev->class);
0351 
0352     pci_parse_of_addrs(sd->op, node, dev);
0353 
0354     if (ofpci_verbose)
0355         pci_info(dev, "    adding to system ...\n");
0356 
0357     pci_device_add(dev, bus);
0358 
0359     return dev;
0360 }
0361 
0362 static void apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
0363 {
0364     u32 idx, first, last;
0365 
0366     first = 8;
0367     last = 0;
0368     for (idx = 0; idx < 8; idx++) {
0369         if ((map & (1 << idx)) != 0) {
0370             if (first > idx)
0371                 first = idx;
0372             if (last < idx)
0373                 last = idx;
0374         }
0375     }
0376 
0377     *first_p = first;
0378     *last_p = last;
0379 }
0380 
0381 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
0382  * a proper 'ranges' property.
0383  */
0384 static void apb_fake_ranges(struct pci_dev *dev,
0385                 struct pci_bus *bus,
0386                 struct pci_pbm_info *pbm)
0387 {
0388     struct pci_bus_region region;
0389     struct resource *res;
0390     u32 first, last;
0391     u8 map;
0392 
0393     pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
0394     apb_calc_first_last(map, &first, &last);
0395     res = bus->resource[0];
0396     res->flags = IORESOURCE_IO;
0397     region.start = (first << 21);
0398     region.end = (last << 21) + ((1 << 21) - 1);
0399     pcibios_bus_to_resource(dev->bus, res, &region);
0400 
0401     pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
0402     apb_calc_first_last(map, &first, &last);
0403     res = bus->resource[1];
0404     res->flags = IORESOURCE_MEM;
0405     region.start = (first << 29);
0406     region.end = (last << 29) + ((1 << 29) - 1);
0407     pcibios_bus_to_resource(dev->bus, res, &region);
0408 }
0409 
0410 static void pci_of_scan_bus(struct pci_pbm_info *pbm,
0411                 struct device_node *node,
0412                 struct pci_bus *bus);
0413 
0414 #define GET_64BIT(prop, i)  ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
0415 
0416 static void of_scan_pci_bridge(struct pci_pbm_info *pbm,
0417                    struct device_node *node,
0418                    struct pci_dev *dev)
0419 {
0420     struct pci_bus *bus;
0421     const u32 *busrange, *ranges;
0422     int len, i, simba;
0423     struct pci_bus_region region;
0424     struct resource *res;
0425     unsigned int flags;
0426     u64 size;
0427 
0428     if (ofpci_verbose)
0429         pci_info(dev, "of_scan_pci_bridge(%pOF)\n", node);
0430 
0431     /* parse bus-range property */
0432     busrange = of_get_property(node, "bus-range", &len);
0433     if (busrange == NULL || len != 8) {
0434         pci_info(dev, "Can't get bus-range for PCI-PCI bridge %pOF\n",
0435                node);
0436         return;
0437     }
0438 
0439     if (ofpci_verbose)
0440         pci_info(dev, "    Bridge bus range [%u --> %u]\n",
0441              busrange[0], busrange[1]);
0442 
0443     ranges = of_get_property(node, "ranges", &len);
0444     simba = 0;
0445     if (ranges == NULL) {
0446         const char *model = of_get_property(node, "model", NULL);
0447         if (model && !strcmp(model, "SUNW,simba"))
0448             simba = 1;
0449     }
0450 
0451     bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
0452     if (!bus) {
0453         pci_err(dev, "Failed to create pci bus for %pOF\n",
0454             node);
0455         return;
0456     }
0457 
0458     bus->primary = dev->bus->number;
0459     pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
0460     bus->bridge_ctl = 0;
0461 
0462     if (ofpci_verbose)
0463         pci_info(dev, "    Bridge ranges[%p] simba[%d]\n",
0464              ranges, simba);
0465 
0466     /* parse ranges property, or cook one up by hand for Simba */
0467     /* PCI #address-cells == 3 and #size-cells == 2 always */
0468     res = &dev->resource[PCI_BRIDGE_RESOURCES];
0469     for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
0470         res->flags = 0;
0471         bus->resource[i] = res;
0472         ++res;
0473     }
0474     if (simba) {
0475         apb_fake_ranges(dev, bus, pbm);
0476         goto after_ranges;
0477     } else if (ranges == NULL) {
0478         pci_read_bridge_bases(bus);
0479         goto after_ranges;
0480     }
0481     i = 1;
0482     for (; len >= 32; len -= 32, ranges += 8) {
0483         u64 start;
0484 
0485         if (ofpci_verbose)
0486             pci_info(dev, "    RAW Range[%08x:%08x:%08x:%08x:%08x:%08x:"
0487                  "%08x:%08x]\n",
0488                  ranges[0], ranges[1], ranges[2], ranges[3],
0489                  ranges[4], ranges[5], ranges[6], ranges[7]);
0490 
0491         flags = pci_parse_of_flags(ranges[0]);
0492         size = GET_64BIT(ranges, 6);
0493         if (flags == 0 || size == 0)
0494             continue;
0495 
0496         /* On PCI-Express systems, PCI bridges that have no devices downstream
0497          * have a bogus size value where the first 32-bit cell is 0xffffffff.
0498          * This results in a bogus range where start + size overflows.
0499          *
0500          * Just skip these otherwise the kernel will complain when the resource
0501          * tries to be claimed.
0502          */
0503         if (size >> 32 == 0xffffffff)
0504             continue;
0505 
0506         if (flags & IORESOURCE_IO) {
0507             res = bus->resource[0];
0508             if (res->flags) {
0509                 pci_err(dev, "ignoring extra I/O range"
0510                     " for bridge %pOF\n", node);
0511                 continue;
0512             }
0513         } else {
0514             if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
0515                 pci_err(dev, "too many memory ranges"
0516                     " for bridge %pOF\n", node);
0517                 continue;
0518             }
0519             res = bus->resource[i];
0520             ++i;
0521         }
0522 
0523         res->flags = flags;
0524         region.start = start = GET_64BIT(ranges, 1);
0525         region.end = region.start + size - 1;
0526 
0527         if (ofpci_verbose)
0528             pci_info(dev, "      Using flags[%08x] start[%016llx] size[%016llx]\n",
0529                  flags, start, size);
0530 
0531         pcibios_bus_to_resource(dev->bus, res, &region);
0532     }
0533 after_ranges:
0534     sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
0535         bus->number);
0536     if (ofpci_verbose)
0537         pci_info(dev, "    bus name: %s\n", bus->name);
0538 
0539     pci_of_scan_bus(pbm, node, bus);
0540 }
0541 
0542 static void pci_of_scan_bus(struct pci_pbm_info *pbm,
0543                 struct device_node *node,
0544                 struct pci_bus *bus)
0545 {
0546     struct device_node *child;
0547     const u32 *reg;
0548     int reglen, devfn, prev_devfn;
0549     struct pci_dev *dev;
0550 
0551     if (ofpci_verbose)
0552         pci_info(bus, "scan_bus[%pOF] bus no %d\n",
0553              node, bus->number);
0554 
0555     prev_devfn = -1;
0556     for_each_child_of_node(node, child) {
0557         if (ofpci_verbose)
0558             pci_info(bus, "  * %pOF\n", child);
0559         reg = of_get_property(child, "reg", &reglen);
0560         if (reg == NULL || reglen < 20)
0561             continue;
0562 
0563         devfn = (reg[0] >> 8) & 0xff;
0564 
0565         /* This is a workaround for some device trees
0566          * which list PCI devices twice.  On the V100
0567          * for example, device number 3 is listed twice.
0568          * Once as "pm" and once again as "lomp".
0569          */
0570         if (devfn == prev_devfn)
0571             continue;
0572         prev_devfn = devfn;
0573 
0574         /* create a new pci_dev for this device */
0575         dev = of_create_pci_dev(pbm, child, bus, devfn);
0576         if (!dev)
0577             continue;
0578         if (ofpci_verbose)
0579             pci_info(dev, "dev header type: %x\n", dev->hdr_type);
0580 
0581         if (pci_is_bridge(dev))
0582             of_scan_pci_bridge(pbm, child, dev);
0583     }
0584 }
0585 
0586 static ssize_t
0587 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
0588 {
0589     struct pci_dev *pdev;
0590     struct device_node *dp;
0591 
0592     pdev = to_pci_dev(dev);
0593     dp = pdev->dev.of_node;
0594 
0595     return scnprintf(buf, PAGE_SIZE, "%pOF\n", dp);
0596 }
0597 
0598 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
0599 
0600 static void pci_bus_register_of_sysfs(struct pci_bus *bus)
0601 {
0602     struct pci_dev *dev;
0603     struct pci_bus *child_bus;
0604     int err;
0605 
0606     list_for_each_entry(dev, &bus->devices, bus_list) {
0607         /* we don't really care if we can create this file or
0608          * not, but we need to assign the result of the call
0609          * or the world will fall under alien invasion and
0610          * everybody will be frozen on a spaceship ready to be
0611          * eaten on alpha centauri by some green and jelly
0612          * humanoid.
0613          */
0614         err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
0615         (void) err;
0616     }
0617     list_for_each_entry(child_bus, &bus->children, node)
0618         pci_bus_register_of_sysfs(child_bus);
0619 }
0620 
0621 static void pci_claim_legacy_resources(struct pci_dev *dev)
0622 {
0623     struct pci_bus_region region;
0624     struct resource *p, *root, *conflict;
0625 
0626     if ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
0627         return;
0628 
0629     p = kzalloc(sizeof(*p), GFP_KERNEL);
0630     if (!p)
0631         return;
0632 
0633     p->name = "Video RAM area";
0634     p->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
0635 
0636     region.start = 0xa0000UL;
0637     region.end = region.start + 0x1ffffUL;
0638     pcibios_bus_to_resource(dev->bus, p, &region);
0639 
0640     root = pci_find_parent_resource(dev, p);
0641     if (!root) {
0642         pci_info(dev, "can't claim VGA legacy %pR: no compatible bridge window\n", p);
0643         goto err;
0644     }
0645 
0646     conflict = request_resource_conflict(root, p);
0647     if (conflict) {
0648         pci_info(dev, "can't claim VGA legacy %pR: address conflict with %s %pR\n",
0649              p, conflict->name, conflict);
0650         goto err;
0651     }
0652 
0653     pci_info(dev, "VGA legacy framebuffer %pR\n", p);
0654     return;
0655 
0656 err:
0657     kfree(p);
0658 }
0659 
0660 static void pci_claim_bus_resources(struct pci_bus *bus)
0661 {
0662     struct pci_bus *child_bus;
0663     struct pci_dev *dev;
0664 
0665     list_for_each_entry(dev, &bus->devices, bus_list) {
0666         int i;
0667 
0668         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
0669             struct resource *r = &dev->resource[i];
0670 
0671             if (r->parent || !r->start || !r->flags)
0672                 continue;
0673 
0674             if (ofpci_verbose)
0675                 pci_info(dev, "Claiming Resource %d: %pR\n",
0676                      i, r);
0677 
0678             pci_claim_resource(dev, i);
0679         }
0680 
0681         pci_claim_legacy_resources(dev);
0682     }
0683 
0684     list_for_each_entry(child_bus, &bus->children, node)
0685         pci_claim_bus_resources(child_bus);
0686 }
0687 
0688 struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
0689                  struct device *parent)
0690 {
0691     LIST_HEAD(resources);
0692     struct device_node *node = pbm->op->dev.of_node;
0693     struct pci_bus *bus;
0694 
0695     printk("PCI: Scanning PBM %pOF\n", node);
0696 
0697     pci_add_resource_offset(&resources, &pbm->io_space,
0698                 pbm->io_offset);
0699     pci_add_resource_offset(&resources, &pbm->mem_space,
0700                 pbm->mem_offset);
0701     if (pbm->mem64_space.flags)
0702         pci_add_resource_offset(&resources, &pbm->mem64_space,
0703                     pbm->mem64_offset);
0704     pbm->busn.start = pbm->pci_first_busno;
0705     pbm->busn.end   = pbm->pci_last_busno;
0706     pbm->busn.flags = IORESOURCE_BUS;
0707     pci_add_resource(&resources, &pbm->busn);
0708     bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
0709                   pbm, &resources);
0710     if (!bus) {
0711         printk(KERN_ERR "Failed to create bus for %pOF\n", node);
0712         pci_free_resource_list(&resources);
0713         return NULL;
0714     }
0715 
0716     pci_of_scan_bus(pbm, node, bus);
0717     pci_bus_register_of_sysfs(bus);
0718 
0719     pci_claim_bus_resources(bus);
0720 
0721     pci_bus_add_devices(bus);
0722     return bus;
0723 }
0724 
0725 int pcibios_enable_device(struct pci_dev *dev, int mask)
0726 {
0727     u16 cmd, oldcmd;
0728     int i;
0729 
0730     pci_read_config_word(dev, PCI_COMMAND, &cmd);
0731     oldcmd = cmd;
0732 
0733     for (i = 0; i < PCI_NUM_RESOURCES; i++) {
0734         struct resource *res = &dev->resource[i];
0735 
0736         /* Only set up the requested stuff */
0737         if (!(mask & (1<<i)))
0738             continue;
0739 
0740         if (res->flags & IORESOURCE_IO)
0741             cmd |= PCI_COMMAND_IO;
0742         if (res->flags & IORESOURCE_MEM)
0743             cmd |= PCI_COMMAND_MEMORY;
0744     }
0745 
0746     if (cmd != oldcmd) {
0747         pci_info(dev, "enabling device (%04x -> %04x)\n", oldcmd, cmd);
0748         pci_write_config_word(dev, PCI_COMMAND, cmd);
0749     }
0750     return 0;
0751 }
0752 
0753 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
0754 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
0755 {
0756     struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
0757     resource_size_t ioaddr = pci_resource_start(pdev, bar);
0758 
0759     if (!pbm)
0760         return -EINVAL;
0761 
0762     vma->vm_pgoff += (ioaddr + pbm->io_space.start) >> PAGE_SHIFT;
0763 
0764     return 0;
0765 }
0766 
0767 #ifdef CONFIG_NUMA
0768 int pcibus_to_node(struct pci_bus *pbus)
0769 {
0770     struct pci_pbm_info *pbm = pbus->sysdata;
0771 
0772     return pbm->numa_node;
0773 }
0774 EXPORT_SYMBOL(pcibus_to_node);
0775 #endif
0776 
0777 /* Return the domain number for this pci bus */
0778 
0779 int pci_domain_nr(struct pci_bus *pbus)
0780 {
0781     struct pci_pbm_info *pbm = pbus->sysdata;
0782     int ret;
0783 
0784     if (!pbm) {
0785         ret = -ENXIO;
0786     } else {
0787         ret = pbm->index;
0788     }
0789 
0790     return ret;
0791 }
0792 EXPORT_SYMBOL(pci_domain_nr);
0793 
0794 #ifdef CONFIG_PCI_MSI
0795 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
0796 {
0797     struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
0798     unsigned int irq;
0799 
0800     if (!pbm->setup_msi_irq)
0801         return -EINVAL;
0802 
0803     return pbm->setup_msi_irq(&irq, pdev, desc);
0804 }
0805 
0806 void arch_teardown_msi_irq(unsigned int irq)
0807 {
0808     struct msi_desc *entry = irq_get_msi_desc(irq);
0809     struct pci_dev *pdev = msi_desc_to_pci_dev(entry);
0810     struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
0811 
0812     if (pbm->teardown_msi_irq)
0813         pbm->teardown_msi_irq(irq, pdev);
0814 }
0815 #endif /* !(CONFIG_PCI_MSI) */
0816 
0817 /* ALI sound chips generate 31-bits of DMA, a special register
0818  * determines what bit 31 is emitted as.
0819  */
0820 int ali_sound_dma_hack(struct device *dev, u64 device_mask)
0821 {
0822     struct iommu *iommu = dev->archdata.iommu;
0823     struct pci_dev *ali_isa_bridge;
0824     u8 val;
0825 
0826     if (!dev_is_pci(dev))
0827         return 0;
0828 
0829     if (to_pci_dev(dev)->vendor != PCI_VENDOR_ID_AL ||
0830         to_pci_dev(dev)->device != PCI_DEVICE_ID_AL_M5451 ||
0831         device_mask != 0x7fffffff)
0832         return 0;
0833 
0834     ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
0835                      PCI_DEVICE_ID_AL_M1533,
0836                      NULL);
0837 
0838     pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
0839     if (iommu->dma_addr_mask & 0x80000000)
0840         val |= 0x01;
0841     else
0842         val &= ~0x01;
0843     pci_write_config_byte(ali_isa_bridge, 0x7e, val);
0844     pci_dev_put(ali_isa_bridge);
0845     return 1;
0846 }
0847 
0848 void pci_resource_to_user(const struct pci_dev *pdev, int bar,
0849               const struct resource *rp, resource_size_t *start,
0850               resource_size_t *end)
0851 {
0852     struct pci_bus_region region;
0853 
0854     /*
0855      * "User" addresses are shown in /sys/devices/pci.../.../resource
0856      * and /proc/bus/pci/devices and used as mmap offsets for
0857      * /proc/bus/pci/BB/DD.F files (see proc_bus_pci_mmap()).
0858      *
0859      * On sparc, these are PCI bus addresses, i.e., raw BAR values.
0860      */
0861     pcibios_resource_to_bus(pdev->bus, &region, (struct resource *) rp);
0862     *start = region.start;
0863     *end = region.end;
0864 }
0865 
0866 void pcibios_set_master(struct pci_dev *dev)
0867 {
0868     /* No special bus mastering setup handling */
0869 }
0870 
0871 #ifdef CONFIG_PCI_IOV
0872 int pcibios_device_add(struct pci_dev *dev)
0873 {
0874     struct pci_dev *pdev;
0875 
0876     /* Add sriov arch specific initialization here.
0877      * Copy dev_archdata from PF to VF
0878      */
0879     if (dev->is_virtfn) {
0880         struct dev_archdata *psd;
0881 
0882         pdev = dev->physfn;
0883         psd = &pdev->dev.archdata;
0884         pci_init_dev_archdata(&dev->dev.archdata, psd->iommu,
0885                       psd->stc, psd->host_controller, NULL,
0886                       psd->numa_node);
0887     }
0888     return 0;
0889 }
0890 #endif /* CONFIG_PCI_IOV */
0891 
0892 static int __init pcibios_init(void)
0893 {
0894     pci_dfl_cache_line_size = 64 >> 2;
0895     return 0;
0896 }
0897 subsys_initcall(pcibios_init);
0898 
0899 #ifdef CONFIG_SYSFS
0900 
0901 #define SLOT_NAME_SIZE  11  /* Max decimal digits + null in u32 */
0902 
0903 static void pcie_bus_slot_names(struct pci_bus *pbus)
0904 {
0905     struct pci_dev *pdev;
0906     struct pci_bus *bus;
0907 
0908     list_for_each_entry(pdev, &pbus->devices, bus_list) {
0909         char name[SLOT_NAME_SIZE];
0910         struct pci_slot *pci_slot;
0911         const u32 *slot_num;
0912         int len;
0913 
0914         slot_num = of_get_property(pdev->dev.of_node,
0915                        "physical-slot#", &len);
0916 
0917         if (slot_num == NULL || len != 4)
0918             continue;
0919 
0920         snprintf(name, sizeof(name), "%u", slot_num[0]);
0921         pci_slot = pci_create_slot(pbus, slot_num[0], name, NULL);
0922 
0923         if (IS_ERR(pci_slot))
0924             pr_err("PCI: pci_create_slot returned %ld.\n",
0925                    PTR_ERR(pci_slot));
0926     }
0927 
0928     list_for_each_entry(bus, &pbus->children, node)
0929         pcie_bus_slot_names(bus);
0930 }
0931 
0932 static void pci_bus_slot_names(struct device_node *node, struct pci_bus *bus)
0933 {
0934     const struct pci_slot_names {
0935         u32 slot_mask;
0936         char    names[0];
0937     } *prop;
0938     const char *sp;
0939     int len, i;
0940     u32 mask;
0941 
0942     prop = of_get_property(node, "slot-names", &len);
0943     if (!prop)
0944         return;
0945 
0946     mask = prop->slot_mask;
0947     sp = prop->names;
0948 
0949     if (ofpci_verbose)
0950         pci_info(bus, "Making slots for [%pOF] mask[0x%02x]\n",
0951              node, mask);
0952 
0953     i = 0;
0954     while (mask) {
0955         struct pci_slot *pci_slot;
0956         u32 this_bit = 1 << i;
0957 
0958         if (!(mask & this_bit)) {
0959             i++;
0960             continue;
0961         }
0962 
0963         if (ofpci_verbose)
0964             pci_info(bus, "Making slot [%s]\n", sp);
0965 
0966         pci_slot = pci_create_slot(bus, i, sp, NULL);
0967         if (IS_ERR(pci_slot))
0968             pci_err(bus, "pci_create_slot returned %ld\n",
0969                 PTR_ERR(pci_slot));
0970 
0971         sp += strlen(sp) + 1;
0972         mask &= ~this_bit;
0973         i++;
0974     }
0975 }
0976 
0977 static int __init of_pci_slot_init(void)
0978 {
0979     struct pci_bus *pbus = NULL;
0980 
0981     while ((pbus = pci_find_next_bus(pbus)) != NULL) {
0982         struct device_node *node;
0983         struct pci_dev *pdev;
0984 
0985         pdev = list_first_entry(&pbus->devices, struct pci_dev,
0986                     bus_list);
0987 
0988         if (pdev && pci_is_pcie(pdev)) {
0989             pcie_bus_slot_names(pbus);
0990         } else {
0991 
0992             if (pbus->self) {
0993 
0994                 /* PCI->PCI bridge */
0995                 node = pbus->self->dev.of_node;
0996 
0997             } else {
0998                 struct pci_pbm_info *pbm = pbus->sysdata;
0999 
1000                 /* Host PCI controller */
1001                 node = pbm->op->dev.of_node;
1002             }
1003 
1004             pci_bus_slot_names(node, pbus);
1005         }
1006     }
1007 
1008     return 0;
1009 }
1010 device_initcall(of_pci_slot_init);
1011 #endif
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