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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * leon_pci_grpci2.c: GRPCI2 Host PCI driver
0004  *
0005  * Copyright (C) 2011 Aeroflex Gaisler AB, Daniel Hellstrom
0006  *
0007  */
0008 
0009 #include <linux/of_device.h>
0010 #include <linux/kernel.h>
0011 #include <linux/pci.h>
0012 #include <linux/slab.h>
0013 #include <linux/delay.h>
0014 #include <linux/export.h>
0015 #include <asm/io.h>
0016 #include <asm/leon.h>
0017 #include <asm/vaddrs.h>
0018 #include <asm/sections.h>
0019 #include <asm/leon_pci.h>
0020 
0021 #include "irq.h"
0022 
0023 struct grpci2_barcfg {
0024     unsigned long pciadr;   /* PCI Space Address */
0025     unsigned long ahbadr;   /* PCI Base address mapped to this AHB addr */
0026 };
0027 
0028 /* Device Node Configuration options:
0029  *  - barcfgs    : Custom Configuration of Host's 6 target BARs
0030  *  - irq_mask   : Limit which PCI interrupts are enabled
0031  *  - do_reset   : Force PCI Reset on startup
0032  *
0033  * barcfgs
0034  * =======
0035  *
0036  * Optional custom Target BAR configuration (see struct grpci2_barcfg). All
0037  * addresses are physical. Array always contains 6 elements (len=2*4*6 bytes)
0038  *
0039  * -1 means not configured (let host driver do default setup).
0040  *
0041  * [i*2+0] = PCI Address of BAR[i] on target interface
0042  * [i*2+1] = Accessing PCI address of BAR[i] result in this AMBA address
0043  *
0044  *
0045  * irq_mask
0046  * ========
0047  *
0048  * Limit which PCI interrupts are enabled. 0=Disable, 1=Enable. By default
0049  * all are enabled. Use this when PCI interrupt pins are floating on PCB.
0050  * int, len=4.
0051  *  bit0 = PCI INTA#
0052  *  bit1 = PCI INTB#
0053  *  bit2 = PCI INTC#
0054  *  bit3 = PCI INTD#
0055  *
0056  *
0057  * reset
0058  * =====
0059  *
0060  * Force PCI reset on startup. int, len=4
0061  */
0062 
0063 /* Enable Debugging Configuration Space Access */
0064 #undef GRPCI2_DEBUG_CFGACCESS
0065 
0066 /*
0067  * GRPCI2 APB Register MAP
0068  */
0069 struct grpci2_regs {
0070     unsigned int ctrl;      /* 0x00 Control */
0071     unsigned int sts_cap;       /* 0x04 Status / Capabilities */
0072     int res1;           /* 0x08 */
0073     unsigned int io_map;        /* 0x0C I/O Map address */
0074     unsigned int dma_ctrl;      /* 0x10 DMA */
0075     unsigned int dma_bdbase;    /* 0x14 DMA */
0076     int res2[2];            /* 0x18 */
0077     unsigned int bars[6];       /* 0x20 read-only PCI BARs */
0078     int res3[2];            /* 0x38 */
0079     unsigned int ahbmst_map[16];    /* 0x40 AHB->PCI Map per AHB Master */
0080 
0081     /* PCI Trace Buffer Registers (OPTIONAL) */
0082     unsigned int t_ctrl;        /* 0x80 */
0083     unsigned int t_cnt;     /* 0x84 */
0084     unsigned int t_adpat;       /* 0x88 */
0085     unsigned int t_admask;      /* 0x8C */
0086     unsigned int t_sigpat;      /* 0x90 */
0087     unsigned int t_sigmask;     /* 0x94 */
0088     unsigned int t_adstate;     /* 0x98 */
0089     unsigned int t_sigstate;    /* 0x9C */
0090 };
0091 
0092 #define REGLOAD(a)  (be32_to_cpu(__raw_readl(&(a))))
0093 #define REGSTORE(a, v)  (__raw_writel(cpu_to_be32(v), &(a)))
0094 
0095 #define CTRL_BUS_BIT 16
0096 
0097 #define CTRL_RESET (1<<31)
0098 #define CTRL_SI (1<<27)
0099 #define CTRL_PE (1<<26)
0100 #define CTRL_EI (1<<25)
0101 #define CTRL_ER (1<<24)
0102 #define CTRL_BUS (0xff<<CTRL_BUS_BIT)
0103 #define CTRL_HOSTINT 0xf
0104 
0105 #define STS_HOST_BIT    31
0106 #define STS_MST_BIT 30
0107 #define STS_TAR_BIT 29
0108 #define STS_DMA_BIT 28
0109 #define STS_DI_BIT  27
0110 #define STS_HI_BIT  26
0111 #define STS_IRQMODE_BIT 24
0112 #define STS_TRACE_BIT   23
0113 #define STS_CFGERRVALID_BIT 20
0114 #define STS_CFGERR_BIT  19
0115 #define STS_INTTYPE_BIT 12
0116 #define STS_INTSTS_BIT  8
0117 #define STS_FDEPTH_BIT  2
0118 #define STS_FNUM_BIT    0
0119 
0120 #define STS_HOST    (1<<STS_HOST_BIT)
0121 #define STS_MST     (1<<STS_MST_BIT)
0122 #define STS_TAR     (1<<STS_TAR_BIT)
0123 #define STS_DMA     (1<<STS_DMA_BIT)
0124 #define STS_DI      (1<<STS_DI_BIT)
0125 #define STS_HI      (1<<STS_HI_BIT)
0126 #define STS_IRQMODE (0x3<<STS_IRQMODE_BIT)
0127 #define STS_TRACE   (1<<STS_TRACE_BIT)
0128 #define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT)
0129 #define STS_CFGERR  (1<<STS_CFGERR_BIT)
0130 #define STS_INTTYPE (0x3f<<STS_INTTYPE_BIT)
0131 #define STS_INTSTS  (0xf<<STS_INTSTS_BIT)
0132 #define STS_FDEPTH  (0x7<<STS_FDEPTH_BIT)
0133 #define STS_FNUM    (0x3<<STS_FNUM_BIT)
0134 
0135 #define STS_ISYSERR (1<<17)
0136 #define STS_IDMA    (1<<16)
0137 #define STS_IDMAERR (1<<15)
0138 #define STS_IMSTABRT    (1<<14)
0139 #define STS_ITGTABRT    (1<<13)
0140 #define STS_IPARERR (1<<12)
0141 
0142 #define STS_ERR_IRQ (STS_ISYSERR | STS_IMSTABRT | STS_ITGTABRT | STS_IPARERR)
0143 
0144 struct grpci2_bd_chan {
0145     unsigned int ctrl;  /* 0x00 DMA Control */
0146     unsigned int nchan; /* 0x04 Next DMA Channel Address */
0147     unsigned int nbd;   /* 0x08 Next Data Descriptor in chan */
0148     unsigned int res;   /* 0x0C Reserved */
0149 };
0150 
0151 #define BD_CHAN_EN      0x80000000
0152 #define BD_CHAN_TYPE        0x00300000
0153 #define BD_CHAN_BDCNT       0x0000ffff
0154 #define BD_CHAN_EN_BIT      31
0155 #define BD_CHAN_TYPE_BIT    20
0156 #define BD_CHAN_BDCNT_BIT   0
0157 
0158 struct grpci2_bd_data {
0159     unsigned int ctrl;  /* 0x00 DMA Data Control */
0160     unsigned int pci_adr;   /* 0x04 PCI Start Address */
0161     unsigned int ahb_adr;   /* 0x08 AHB Start address */
0162     unsigned int next;  /* 0x0C Next Data Descriptor in chan */
0163 };
0164 
0165 #define BD_DATA_EN      0x80000000
0166 #define BD_DATA_IE      0x40000000
0167 #define BD_DATA_DR      0x20000000
0168 #define BD_DATA_TYPE        0x00300000
0169 #define BD_DATA_ER      0x00080000
0170 #define BD_DATA_LEN     0x0000ffff
0171 #define BD_DATA_EN_BIT      31
0172 #define BD_DATA_IE_BIT      30
0173 #define BD_DATA_DR_BIT      29
0174 #define BD_DATA_TYPE_BIT    20
0175 #define BD_DATA_ER_BIT      19
0176 #define BD_DATA_LEN_BIT     0
0177 
0178 /* GRPCI2 Capability */
0179 struct grpci2_cap_first {
0180     unsigned int ctrl;
0181     unsigned int pci2ahb_map[6];
0182     unsigned int ext2ahb_map;
0183     unsigned int io_map;
0184     unsigned int pcibar_size[6];
0185 };
0186 #define CAP9_CTRL_OFS 0
0187 #define CAP9_BAR_OFS 0x4
0188 #define CAP9_IOMAP_OFS 0x20
0189 #define CAP9_BARSIZE_OFS 0x24
0190 
0191 #define TGT 256
0192 
0193 struct grpci2_priv {
0194     struct leon_pci_info    info; /* must be on top of this structure */
0195     struct grpci2_regs __iomem *regs;
0196     char            irq;
0197     char            irq_mode; /* IRQ Mode from CAPSTS REG */
0198     char            bt_enabled;
0199     char            do_reset;
0200     char            irq_mask;
0201     u32         pciid; /* PCI ID of Host */
0202     unsigned char       irq_map[4];
0203 
0204     /* Virtual IRQ numbers */
0205     unsigned int        virq_err;
0206     unsigned int        virq_dma;
0207 
0208     /* AHB PCI Windows */
0209     unsigned long       pci_area;   /* MEMORY */
0210     unsigned long       pci_area_end;
0211     unsigned long       pci_io;     /* I/O */
0212     unsigned long       pci_conf;   /* CONFIGURATION */
0213     unsigned long       pci_conf_end;
0214     unsigned long       pci_io_va;
0215 
0216     struct grpci2_barcfg    tgtbars[6];
0217 };
0218 
0219 static DEFINE_SPINLOCK(grpci2_dev_lock);
0220 static struct grpci2_priv *grpci2priv;
0221 
0222 static int grpci2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
0223 {
0224     struct grpci2_priv *priv = dev->bus->sysdata;
0225     int irq_group;
0226 
0227     /* Use default IRQ decoding on PCI BUS0 according slot numbering */
0228     irq_group = slot & 0x3;
0229     pin = ((pin - 1) + irq_group) & 0x3;
0230 
0231     return priv->irq_map[pin];
0232 }
0233 
0234 static int grpci2_cfg_r32(struct grpci2_priv *priv, unsigned int bus,
0235                 unsigned int devfn, int where, u32 *val)
0236 {
0237     unsigned int *pci_conf;
0238     unsigned long flags;
0239     u32 tmp;
0240 
0241     if (where & 0x3)
0242         return -EINVAL;
0243 
0244     if (bus == 0) {
0245         devfn += (0x8 * 6); /* start at AD16=Device0 */
0246     } else if (bus == TGT) {
0247         bus = 0;
0248         devfn = 0; /* special case: bridge controller itself */
0249     }
0250 
0251     /* Select bus */
0252     spin_lock_irqsave(&grpci2_dev_lock, flags);
0253     REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |
0254                    (bus << 16));
0255     spin_unlock_irqrestore(&grpci2_dev_lock, flags);
0256 
0257     /* clear old status */
0258     REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));
0259 
0260     pci_conf = (unsigned int *) (priv->pci_conf |
0261                         (devfn << 8) | (where & 0xfc));
0262     tmp = LEON3_BYPASS_LOAD_PA(pci_conf);
0263 
0264     /* Wait until GRPCI2 signals that CFG access is done, it should be
0265      * done instantaneously unless a DMA operation is ongoing...
0266      */
0267     while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0)
0268         ;
0269 
0270     if (REGLOAD(priv->regs->sts_cap) & STS_CFGERR) {
0271         *val = 0xffffffff;
0272     } else {
0273         /* Bus always little endian (unaffected by byte-swapping) */
0274         *val = swab32(tmp);
0275     }
0276 
0277     return 0;
0278 }
0279 
0280 static int grpci2_cfg_r16(struct grpci2_priv *priv, unsigned int bus,
0281                 unsigned int devfn, int where, u32 *val)
0282 {
0283     u32 v;
0284     int ret;
0285 
0286     if (where & 0x1)
0287         return -EINVAL;
0288     ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
0289     *val = 0xffff & (v >> (8 * (where & 0x3)));
0290     return ret;
0291 }
0292 
0293 static int grpci2_cfg_r8(struct grpci2_priv *priv, unsigned int bus,
0294                 unsigned int devfn, int where, u32 *val)
0295 {
0296     u32 v;
0297     int ret;
0298 
0299     ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
0300     *val = 0xff & (v >> (8 * (where & 3)));
0301 
0302     return ret;
0303 }
0304 
0305 static int grpci2_cfg_w32(struct grpci2_priv *priv, unsigned int bus,
0306                 unsigned int devfn, int where, u32 val)
0307 {
0308     unsigned int *pci_conf;
0309     unsigned long flags;
0310 
0311     if (where & 0x3)
0312         return -EINVAL;
0313 
0314     if (bus == 0) {
0315         devfn += (0x8 * 6); /* start at AD16=Device0 */
0316     } else if (bus == TGT) {
0317         bus = 0;
0318         devfn = 0; /* special case: bridge controller itself */
0319     }
0320 
0321     /* Select bus */
0322     spin_lock_irqsave(&grpci2_dev_lock, flags);
0323     REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |
0324                    (bus << 16));
0325     spin_unlock_irqrestore(&grpci2_dev_lock, flags);
0326 
0327     /* clear old status */
0328     REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));
0329 
0330     pci_conf = (unsigned int *) (priv->pci_conf |
0331                         (devfn << 8) | (where & 0xfc));
0332     LEON3_BYPASS_STORE_PA(pci_conf, swab32(val));
0333 
0334     /* Wait until GRPCI2 signals that CFG access is done, it should be
0335      * done instantaneously unless a DMA operation is ongoing...
0336      */
0337     while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0)
0338         ;
0339 
0340     return 0;
0341 }
0342 
0343 static int grpci2_cfg_w16(struct grpci2_priv *priv, unsigned int bus,
0344                 unsigned int devfn, int where, u32 val)
0345 {
0346     int ret;
0347     u32 v;
0348 
0349     if (where & 0x1)
0350         return -EINVAL;
0351     ret = grpci2_cfg_r32(priv, bus, devfn, where&~3, &v);
0352     if (ret)
0353         return ret;
0354     v = (v & ~(0xffff << (8 * (where & 0x3)))) |
0355         ((0xffff & val) << (8 * (where & 0x3)));
0356     return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v);
0357 }
0358 
0359 static int grpci2_cfg_w8(struct grpci2_priv *priv, unsigned int bus,
0360                 unsigned int devfn, int where, u32 val)
0361 {
0362     int ret;
0363     u32 v;
0364 
0365     ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
0366     if (ret != 0)
0367         return ret;
0368     v = (v & ~(0xff << (8 * (where & 0x3)))) |
0369         ((0xff & val) << (8 * (where & 0x3)));
0370     return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v);
0371 }
0372 
0373 /* Read from Configuration Space. When entering here the PCI layer has taken
0374  * the pci_lock spinlock and IRQ is off.
0375  */
0376 static int grpci2_read_config(struct pci_bus *bus, unsigned int devfn,
0377                   int where, int size, u32 *val)
0378 {
0379     struct grpci2_priv *priv = grpci2priv;
0380     unsigned int busno = bus->number;
0381     int ret;
0382 
0383     if (PCI_SLOT(devfn) > 15 || busno > 255) {
0384         *val = ~0;
0385         return 0;
0386     }
0387 
0388     switch (size) {
0389     case 1:
0390         ret = grpci2_cfg_r8(priv, busno, devfn, where, val);
0391         break;
0392     case 2:
0393         ret = grpci2_cfg_r16(priv, busno, devfn, where, val);
0394         break;
0395     case 4:
0396         ret = grpci2_cfg_r32(priv, busno, devfn, where, val);
0397         break;
0398     default:
0399         ret = -EINVAL;
0400         break;
0401     }
0402 
0403 #ifdef GRPCI2_DEBUG_CFGACCESS
0404     printk(KERN_INFO "grpci2_read_config: [%02x:%02x:%x] ofs=%d val=%x "
0405         "size=%d\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where,
0406         *val, size);
0407 #endif
0408 
0409     return ret;
0410 }
0411 
0412 /* Write to Configuration Space. When entering here the PCI layer has taken
0413  * the pci_lock spinlock and IRQ is off.
0414  */
0415 static int grpci2_write_config(struct pci_bus *bus, unsigned int devfn,
0416                    int where, int size, u32 val)
0417 {
0418     struct grpci2_priv *priv = grpci2priv;
0419     unsigned int busno = bus->number;
0420 
0421     if (PCI_SLOT(devfn) > 15 || busno > 255)
0422         return 0;
0423 
0424 #ifdef GRPCI2_DEBUG_CFGACCESS
0425     printk(KERN_INFO "grpci2_write_config: [%02x:%02x:%x] ofs=%d size=%d "
0426         "val=%x\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn),
0427         where, size, val);
0428 #endif
0429 
0430     switch (size) {
0431     default:
0432         return -EINVAL;
0433     case 1:
0434         return grpci2_cfg_w8(priv, busno, devfn, where, val);
0435     case 2:
0436         return grpci2_cfg_w16(priv, busno, devfn, where, val);
0437     case 4:
0438         return grpci2_cfg_w32(priv, busno, devfn, where, val);
0439     }
0440 }
0441 
0442 static struct pci_ops grpci2_ops = {
0443     .read =     grpci2_read_config,
0444     .write =    grpci2_write_config,
0445 };
0446 
0447 /* GENIRQ IRQ chip implementation for GRPCI2 irqmode=0..2. In configuration
0448  * 3 where all PCI Interrupts has a separate IRQ on the system IRQ controller
0449  * this is not needed and the standard IRQ controller can be used.
0450  */
0451 
0452 static void grpci2_mask_irq(struct irq_data *data)
0453 {
0454     unsigned long flags;
0455     unsigned int irqidx;
0456     struct grpci2_priv *priv = grpci2priv;
0457 
0458     irqidx = (unsigned int)data->chip_data - 1;
0459     if (irqidx > 3) /* only mask PCI interrupts here */
0460         return;
0461 
0462     spin_lock_irqsave(&grpci2_dev_lock, flags);
0463     REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) & ~(1 << irqidx));
0464     spin_unlock_irqrestore(&grpci2_dev_lock, flags);
0465 }
0466 
0467 static void grpci2_unmask_irq(struct irq_data *data)
0468 {
0469     unsigned long flags;
0470     unsigned int irqidx;
0471     struct grpci2_priv *priv = grpci2priv;
0472 
0473     irqidx = (unsigned int)data->chip_data - 1;
0474     if (irqidx > 3) /* only unmask PCI interrupts here */
0475         return;
0476 
0477     spin_lock_irqsave(&grpci2_dev_lock, flags);
0478     REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) | (1 << irqidx));
0479     spin_unlock_irqrestore(&grpci2_dev_lock, flags);
0480 }
0481 
0482 static unsigned int grpci2_startup_irq(struct irq_data *data)
0483 {
0484     grpci2_unmask_irq(data);
0485     return 0;
0486 }
0487 
0488 static void grpci2_shutdown_irq(struct irq_data *data)
0489 {
0490     grpci2_mask_irq(data);
0491 }
0492 
0493 static struct irq_chip grpci2_irq = {
0494     .name       = "grpci2",
0495     .irq_startup    = grpci2_startup_irq,
0496     .irq_shutdown   = grpci2_shutdown_irq,
0497     .irq_mask   = grpci2_mask_irq,
0498     .irq_unmask = grpci2_unmask_irq,
0499 };
0500 
0501 /* Handle one or multiple IRQs from the PCI core */
0502 static void grpci2_pci_flow_irq(struct irq_desc *desc)
0503 {
0504     struct grpci2_priv *priv = grpci2priv;
0505     int i, ack = 0;
0506     unsigned int ctrl, sts_cap, pci_ints;
0507 
0508     ctrl = REGLOAD(priv->regs->ctrl);
0509     sts_cap = REGLOAD(priv->regs->sts_cap);
0510 
0511     /* Error Interrupt? */
0512     if (sts_cap & STS_ERR_IRQ) {
0513         generic_handle_irq(priv->virq_err);
0514         ack = 1;
0515     }
0516 
0517     /* PCI Interrupt? */
0518     pci_ints = ((~sts_cap) >> STS_INTSTS_BIT) & ctrl & CTRL_HOSTINT;
0519     if (pci_ints) {
0520         /* Call respective PCI Interrupt handler */
0521         for (i = 0; i < 4; i++) {
0522             if (pci_ints & (1 << i))
0523                 generic_handle_irq(priv->irq_map[i]);
0524         }
0525         ack = 1;
0526     }
0527 
0528     /*
0529      * Decode DMA Interrupt only when shared with Err and PCI INTX#, when
0530      * the DMA is a unique IRQ the DMA interrupts doesn't end up here, they
0531      * goes directly to DMA ISR.
0532      */
0533     if ((priv->irq_mode == 0) && (sts_cap & (STS_IDMA | STS_IDMAERR))) {
0534         generic_handle_irq(priv->virq_dma);
0535         ack = 1;
0536     }
0537 
0538     /*
0539      * Call "first level" IRQ chip end-of-irq handler. It will ACK LEON IRQ
0540      * Controller, this must be done after IRQ sources have been handled to
0541      * avoid double IRQ generation
0542      */
0543     if (ack)
0544         desc->irq_data.chip->irq_eoi(&desc->irq_data);
0545 }
0546 
0547 /* Create a virtual IRQ */
0548 static unsigned int grpci2_build_device_irq(unsigned int irq)
0549 {
0550     unsigned int virq = 0, pil;
0551 
0552     pil = 1 << 8;
0553     virq = irq_alloc(irq, pil);
0554     if (virq == 0)
0555         goto out;
0556 
0557     irq_set_chip_and_handler_name(virq, &grpci2_irq, handle_simple_irq,
0558                       "pcilvl");
0559     irq_set_chip_data(virq, (void *)irq);
0560 
0561 out:
0562     return virq;
0563 }
0564 
0565 static void grpci2_hw_init(struct grpci2_priv *priv)
0566 {
0567     u32 ahbadr, pciadr, bar_sz, capptr, io_map, data;
0568     struct grpci2_regs __iomem *regs = priv->regs;
0569     int i;
0570     struct grpci2_barcfg *barcfg = priv->tgtbars;
0571 
0572     /* Reset any earlier setup */
0573     if (priv->do_reset) {
0574         printk(KERN_INFO "GRPCI2: Resetting PCI bus\n");
0575         REGSTORE(regs->ctrl, CTRL_RESET);
0576         ssleep(1); /* Wait for boards to settle */
0577     }
0578     REGSTORE(regs->ctrl, 0);
0579     REGSTORE(regs->sts_cap, ~0); /* Clear Status */
0580     REGSTORE(regs->dma_ctrl, 0);
0581     REGSTORE(regs->dma_bdbase, 0);
0582 
0583     /* Translate I/O accesses to 0, I/O Space always @ PCI low 64Kbytes */
0584     REGSTORE(regs->io_map, REGLOAD(regs->io_map) & 0x0000ffff);
0585 
0586     /* set 1:1 mapping between AHB -> PCI memory space, for all Masters
0587      * Each AHB master has it's own mapping registers. Max 16 AHB masters.
0588      */
0589     for (i = 0; i < 16; i++)
0590         REGSTORE(regs->ahbmst_map[i], priv->pci_area);
0591 
0592     /* Get the GRPCI2 Host PCI ID */
0593     grpci2_cfg_r32(priv, TGT, 0, PCI_VENDOR_ID, &priv->pciid);
0594 
0595     /* Get address to first (always defined) capability structure */
0596     grpci2_cfg_r8(priv, TGT, 0, PCI_CAPABILITY_LIST, &capptr);
0597 
0598     /* Enable/Disable Byte twisting */
0599     grpci2_cfg_r32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, &io_map);
0600     io_map = (io_map & ~0x1) | (priv->bt_enabled ? 1 : 0);
0601     grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, io_map);
0602 
0603     /* Setup the Host's PCI Target BARs for other peripherals to access,
0604      * and do DMA to the host's memory. The target BARs can be sized and
0605      * enabled individually.
0606      *
0607      * User may set custom target BARs, but default is:
0608      * The first BARs is used to map kernel low (DMA is part of normal
0609      * region on sparc which is SRMMU_MAXMEM big) main memory 1:1 to the
0610      * PCI bus, the other BARs are disabled. We assume that the first BAR
0611      * is always available.
0612      */
0613     for (i = 0; i < 6; i++) {
0614         if (barcfg[i].pciadr != ~0 && barcfg[i].ahbadr != ~0) {
0615             /* Target BARs must have the proper alignment */
0616             ahbadr = barcfg[i].ahbadr;
0617             pciadr = barcfg[i].pciadr;
0618             bar_sz = ((pciadr - 1) & ~pciadr) + 1;
0619         } else {
0620             if (i == 0) {
0621                 /* Map main memory */
0622                 bar_sz = 0xf0000008; /* 256MB prefetchable */
0623                 ahbadr = 0xf0000000 & (u32)__pa(PAGE_ALIGN(
0624                     (unsigned long) &_end));
0625                 pciadr = ahbadr;
0626             } else {
0627                 bar_sz = 0;
0628                 ahbadr = 0;
0629                 pciadr = 0;
0630             }
0631         }
0632         grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BARSIZE_OFS+i*4,
0633                 bar_sz);
0634         grpci2_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0+i*4, pciadr);
0635         grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BAR_OFS+i*4, ahbadr);
0636         printk(KERN_INFO "        TGT BAR[%d]: 0x%08x (PCI)-> 0x%08x\n",
0637             i, pciadr, ahbadr);
0638     }
0639 
0640     /* set as bus master and enable pci memory responses */
0641     grpci2_cfg_r32(priv, TGT, 0, PCI_COMMAND, &data);
0642     data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
0643     grpci2_cfg_w32(priv, TGT, 0, PCI_COMMAND, data);
0644 
0645     /* Enable Error respone (CPU-TRAP) on illegal memory access. */
0646     REGSTORE(regs->ctrl, CTRL_ER | CTRL_PE);
0647 }
0648 
0649 static irqreturn_t grpci2_jump_interrupt(int irq, void *arg)
0650 {
0651     printk(KERN_ERR "GRPCI2: Jump IRQ happened\n");
0652     return IRQ_NONE;
0653 }
0654 
0655 /* Handle GRPCI2 Error Interrupt */
0656 static irqreturn_t grpci2_err_interrupt(int irq, void *arg)
0657 {
0658     struct grpci2_priv *priv = arg;
0659     struct grpci2_regs __iomem *regs = priv->regs;
0660     unsigned int status;
0661 
0662     status = REGLOAD(regs->sts_cap);
0663     if ((status & STS_ERR_IRQ) == 0)
0664         return IRQ_NONE;
0665 
0666     if (status & STS_IPARERR)
0667         printk(KERN_ERR "GRPCI2: Parity Error\n");
0668 
0669     if (status & STS_ITGTABRT)
0670         printk(KERN_ERR "GRPCI2: Target Abort\n");
0671 
0672     if (status & STS_IMSTABRT)
0673         printk(KERN_ERR "GRPCI2: Master Abort\n");
0674 
0675     if (status & STS_ISYSERR)
0676         printk(KERN_ERR "GRPCI2: System Error\n");
0677 
0678     /* Clear handled INT TYPE IRQs */
0679     REGSTORE(regs->sts_cap, status & STS_ERR_IRQ);
0680 
0681     return IRQ_HANDLED;
0682 }
0683 
0684 static int grpci2_of_probe(struct platform_device *ofdev)
0685 {
0686     struct grpci2_regs __iomem *regs;
0687     struct grpci2_priv *priv;
0688     int err, i, len;
0689     const int *tmp;
0690     unsigned int capability;
0691 
0692     if (grpci2priv) {
0693         printk(KERN_ERR "GRPCI2: only one GRPCI2 core supported\n");
0694         return -ENODEV;
0695     }
0696 
0697     if (ofdev->num_resources < 3) {
0698         printk(KERN_ERR "GRPCI2: not enough APB/AHB resources\n");
0699         return -EIO;
0700     }
0701 
0702     /* Find Device Address */
0703     regs = of_ioremap(&ofdev->resource[0], 0,
0704               resource_size(&ofdev->resource[0]),
0705               "grlib-grpci2 regs");
0706     if (regs == NULL) {
0707         printk(KERN_ERR "GRPCI2: ioremap failed\n");
0708         return -EIO;
0709     }
0710 
0711     /*
0712      * Check that we're in Host Slot and that we can act as a Host Bridge
0713      * and not only as target.
0714      */
0715     capability = REGLOAD(regs->sts_cap);
0716     if ((capability & STS_HOST) || !(capability & STS_MST)) {
0717         printk(KERN_INFO "GRPCI2: not in host system slot\n");
0718         err = -EIO;
0719         goto err1;
0720     }
0721 
0722     priv = grpci2priv = kzalloc(sizeof(struct grpci2_priv), GFP_KERNEL);
0723     if (grpci2priv == NULL) {
0724         err = -ENOMEM;
0725         goto err1;
0726     }
0727     priv->regs = regs;
0728     priv->irq = ofdev->archdata.irqs[0]; /* BASE IRQ */
0729     priv->irq_mode = (capability & STS_IRQMODE) >> STS_IRQMODE_BIT;
0730 
0731     printk(KERN_INFO "GRPCI2: host found at %p, irq%d\n", regs, priv->irq);
0732 
0733     /* Byte twisting should be made configurable from kernel command line */
0734     priv->bt_enabled = 1;
0735 
0736     /* Let user do custom Target BAR assignment */
0737     tmp = of_get_property(ofdev->dev.of_node, "barcfg", &len);
0738     if (tmp && (len == 2*4*6))
0739         memcpy(priv->tgtbars, tmp, 2*4*6);
0740     else
0741         memset(priv->tgtbars, -1, 2*4*6);
0742 
0743     /* Limit IRQ unmasking in irq_mode 2 and 3 */
0744     tmp = of_get_property(ofdev->dev.of_node, "irq_mask", &len);
0745     if (tmp && (len == 4))
0746         priv->do_reset = *tmp;
0747     else
0748         priv->irq_mask = 0xf;
0749 
0750     /* Optional PCI reset. Force PCI reset on startup */
0751     tmp = of_get_property(ofdev->dev.of_node, "reset", &len);
0752     if (tmp && (len == 4))
0753         priv->do_reset = *tmp;
0754     else
0755         priv->do_reset = 0;
0756 
0757     /* Find PCI Memory, I/O and Configuration Space Windows */
0758     priv->pci_area = ofdev->resource[1].start;
0759     priv->pci_area_end = ofdev->resource[1].end+1;
0760     priv->pci_io = ofdev->resource[2].start;
0761     priv->pci_conf = ofdev->resource[2].start + 0x10000;
0762     priv->pci_conf_end = priv->pci_conf + 0x10000;
0763     priv->pci_io_va = (unsigned long)ioremap(priv->pci_io, 0x10000);
0764     if (!priv->pci_io_va) {
0765         err = -EIO;
0766         goto err2;
0767     }
0768 
0769     printk(KERN_INFO
0770         "GRPCI2: MEMORY SPACE [0x%08lx - 0x%08lx]\n"
0771         "        I/O    SPACE [0x%08lx - 0x%08lx]\n"
0772         "        CONFIG SPACE [0x%08lx - 0x%08lx]\n",
0773         priv->pci_area, priv->pci_area_end-1,
0774         priv->pci_io, priv->pci_conf-1,
0775         priv->pci_conf, priv->pci_conf_end-1);
0776 
0777     /*
0778      * I/O Space resources in I/O Window mapped into Virtual Adr Space
0779      * We never use low 4KB because some devices seem have problems using
0780      * address 0.
0781      */
0782     memset(&priv->info.io_space, 0, sizeof(struct resource));
0783     priv->info.io_space.name = "GRPCI2 PCI I/O Space";
0784     priv->info.io_space.start = priv->pci_io_va + 0x1000;
0785     priv->info.io_space.end = priv->pci_io_va + 0x10000 - 1;
0786     priv->info.io_space.flags = IORESOURCE_IO;
0787 
0788     /*
0789      * GRPCI2 has no prefetchable memory, map everything as
0790      * non-prefetchable memory
0791      */
0792     memset(&priv->info.mem_space, 0, sizeof(struct resource));
0793     priv->info.mem_space.name = "GRPCI2 PCI MEM Space";
0794     priv->info.mem_space.start = priv->pci_area;
0795     priv->info.mem_space.end = priv->pci_area_end - 1;
0796     priv->info.mem_space.flags = IORESOURCE_MEM;
0797 
0798     if (request_resource(&iomem_resource, &priv->info.mem_space) < 0)
0799         goto err3;
0800     if (request_resource(&ioport_resource, &priv->info.io_space) < 0)
0801         goto err4;
0802 
0803     /* setup maximum supported PCI buses */
0804     priv->info.busn.name = "GRPCI2 busn";
0805     priv->info.busn.start = 0;
0806     priv->info.busn.end = 255;
0807 
0808     grpci2_hw_init(priv);
0809 
0810     /*
0811      * Get PCI Interrupt to System IRQ mapping and setup IRQ handling
0812      * Error IRQ always on PCI INTA.
0813      */
0814     if (priv->irq_mode < 2) {
0815         /* All PCI interrupts are shared using the same system IRQ */
0816         leon_update_virq_handling(priv->irq, grpci2_pci_flow_irq,
0817                      "pcilvl", 0);
0818 
0819         priv->irq_map[0] = grpci2_build_device_irq(1);
0820         priv->irq_map[1] = grpci2_build_device_irq(2);
0821         priv->irq_map[2] = grpci2_build_device_irq(3);
0822         priv->irq_map[3] = grpci2_build_device_irq(4);
0823 
0824         priv->virq_err = grpci2_build_device_irq(5);
0825         if (priv->irq_mode & 1)
0826             priv->virq_dma = ofdev->archdata.irqs[1];
0827         else
0828             priv->virq_dma = grpci2_build_device_irq(6);
0829 
0830         /* Enable IRQs on LEON IRQ controller */
0831         err = request_irq(priv->irq, grpci2_jump_interrupt, 0,
0832                     "GRPCI2_JUMP", priv);
0833         if (err)
0834             printk(KERN_ERR "GRPCI2: ERR IRQ request failed\n");
0835     } else {
0836         /* All PCI interrupts have an unique IRQ interrupt */
0837         for (i = 0; i < 4; i++) {
0838             /* Make LEON IRQ layer handle level IRQ by acking */
0839             leon_update_virq_handling(ofdev->archdata.irqs[i],
0840                          handle_fasteoi_irq, "pcilvl",
0841                          1);
0842             priv->irq_map[i] = ofdev->archdata.irqs[i];
0843         }
0844         priv->virq_err = priv->irq_map[0];
0845         if (priv->irq_mode & 1)
0846             priv->virq_dma = ofdev->archdata.irqs[4];
0847         else
0848             priv->virq_dma = priv->irq_map[0];
0849 
0850         /* Unmask all PCI interrupts, request_irq will not do that */
0851         REGSTORE(regs->ctrl, REGLOAD(regs->ctrl)|(priv->irq_mask&0xf));
0852     }
0853 
0854     /* Setup IRQ handler for non-configuration space access errors */
0855     err = request_irq(priv->virq_err, grpci2_err_interrupt, IRQF_SHARED,
0856                 "GRPCI2_ERR", priv);
0857     if (err) {
0858         printk(KERN_DEBUG "GRPCI2: ERR VIRQ request failed: %d\n", err);
0859         goto err5;
0860     }
0861 
0862     /*
0863      * Enable Error Interrupts. PCI interrupts are unmasked once request_irq
0864      * is called by the PCI Device drivers
0865      */
0866     REGSTORE(regs->ctrl, REGLOAD(regs->ctrl) | CTRL_EI | CTRL_SI);
0867 
0868     /* Init common layer and scan buses */
0869     priv->info.ops = &grpci2_ops;
0870     priv->info.map_irq = grpci2_map_irq;
0871     leon_pci_init(ofdev, &priv->info);
0872 
0873     return 0;
0874 
0875 err5:
0876     release_resource(&priv->info.io_space);
0877 err4:
0878     release_resource(&priv->info.mem_space);
0879 err3:
0880     err = -ENOMEM;
0881     iounmap((void __iomem *)priv->pci_io_va);
0882 err2:
0883     kfree(priv);
0884 err1:
0885     of_iounmap(&ofdev->resource[0], regs,
0886         resource_size(&ofdev->resource[0]));
0887     return err;
0888 }
0889 
0890 static const struct of_device_id grpci2_of_match[] __initconst = {
0891     {
0892      .name = "GAISLER_GRPCI2",
0893      },
0894     {
0895      .name = "01_07c",
0896      },
0897     {},
0898 };
0899 
0900 static struct platform_driver grpci2_of_driver = {
0901     .driver = {
0902         .name = "grpci2",
0903         .of_match_table = grpci2_of_match,
0904     },
0905     .probe = grpci2_of_probe,
0906 };
0907 
0908 static int __init grpci2_init(void)
0909 {
0910     return platform_driver_register(&grpci2_of_driver);
0911 }
0912 
0913 subsys_initcall(grpci2_init);
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