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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * leon_pci_grpci1.c: GRPCI1 Host PCI driver
0004  *
0005  * Copyright (C) 2013 Aeroflex Gaisler AB
0006  *
0007  * This GRPCI1 driver does not support PCI interrupts taken from
0008  * GPIO pins. Interrupt generation at PCI parity and system error
0009  * detection is by default turned off since some GRPCI1 cores does
0010  * not support detection. It can be turned on from the bootloader
0011  * using the all_pci_errors property.
0012  *
0013  * Contributors: Daniel Hellstrom <daniel@gaisler.com>
0014  */
0015 
0016 #include <linux/of_device.h>
0017 #include <linux/export.h>
0018 #include <linux/kernel.h>
0019 #include <linux/of_irq.h>
0020 #include <linux/delay.h>
0021 #include <linux/pci.h>
0022 
0023 #include <asm/leon_pci.h>
0024 #include <asm/sections.h>
0025 #include <asm/vaddrs.h>
0026 #include <asm/leon.h>
0027 #include <asm/io.h>
0028 
0029 #include "irq.h"
0030 
0031 /* Enable/Disable Debugging Configuration Space Access */
0032 #undef GRPCI1_DEBUG_CFGACCESS
0033 
0034 /*
0035  * GRPCI1 APB Register MAP
0036  */
0037 struct grpci1_regs {
0038     unsigned int cfg_stat;      /* 0x00 Configuration / Status */
0039     unsigned int bar0;      /* 0x04 BAR0 (RO) */
0040     unsigned int page0;     /* 0x08 PAGE0 (RO) */
0041     unsigned int bar1;      /* 0x0C BAR1 (RO) */
0042     unsigned int page1;     /* 0x10 PAGE1 */
0043     unsigned int iomap;     /* 0x14 IO Map */
0044     unsigned int stat_cmd;      /* 0x18 PCI Status & Command (RO) */
0045     unsigned int irq;       /* 0x1C Interrupt register */
0046 };
0047 
0048 #define REGLOAD(a)  (be32_to_cpu(__raw_readl(&(a))))
0049 #define REGSTORE(a, v)  (__raw_writel(cpu_to_be32(v), &(a)))
0050 
0051 #define PAGE0_BTEN_BIT    0
0052 #define PAGE0_BTEN        (1 << PAGE0_BTEN_BIT)
0053 
0054 #define CFGSTAT_HOST_BIT  13
0055 #define CFGSTAT_CTO_BIT   8
0056 #define CFGSTAT_HOST      (1 << CFGSTAT_HOST_BIT)
0057 #define CFGSTAT_CTO       (1 << CFGSTAT_CTO_BIT)
0058 
0059 #define IRQ_DPE (1 << 9)
0060 #define IRQ_SSE (1 << 8)
0061 #define IRQ_RMA (1 << 7)
0062 #define IRQ_RTA (1 << 6)
0063 #define IRQ_STA (1 << 5)
0064 #define IRQ_DPED (1 << 4)
0065 #define IRQ_INTD (1 << 3)
0066 #define IRQ_INTC (1 << 2)
0067 #define IRQ_INTB (1 << 1)
0068 #define IRQ_INTA (1 << 0)
0069 #define IRQ_DEF_ERRORS (IRQ_RMA | IRQ_RTA | IRQ_STA)
0070 #define IRQ_ALL_ERRORS (IRQ_DPED | IRQ_DEF_ERRORS | IRQ_SSE | IRQ_DPE)
0071 #define IRQ_INTX (IRQ_INTA | IRQ_INTB | IRQ_INTC | IRQ_INTD)
0072 #define IRQ_MASK_BIT 16
0073 
0074 #define DEF_PCI_ERRORS (PCI_STATUS_SIG_TARGET_ABORT | \
0075             PCI_STATUS_REC_TARGET_ABORT | \
0076             PCI_STATUS_REC_MASTER_ABORT)
0077 #define ALL_PCI_ERRORS (PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY | \
0078             PCI_STATUS_SIG_SYSTEM_ERROR | DEF_PCI_ERRORS)
0079 
0080 #define TGT 256
0081 
0082 struct grpci1_priv {
0083     struct leon_pci_info    info; /* must be on top of this structure */
0084     struct grpci1_regs __iomem *regs;       /* GRPCI register map */
0085     struct device       *dev;
0086     int         pci_err_mask;   /* STATUS register error mask */
0087     int         irq;        /* LEON irqctrl GRPCI IRQ */
0088     unsigned char       irq_map[4]; /* GRPCI nexus PCI INTX# IRQs */
0089     unsigned int        irq_err;    /* GRPCI nexus Virt Error IRQ */
0090 
0091     /* AHB PCI Windows */
0092     unsigned long       pci_area;   /* MEMORY */
0093     unsigned long       pci_area_end;
0094     unsigned long       pci_io;     /* I/O */
0095     unsigned long       pci_conf;   /* CONFIGURATION */
0096     unsigned long       pci_conf_end;
0097     unsigned long       pci_io_va;
0098 };
0099 
0100 static struct grpci1_priv *grpci1priv;
0101 
0102 static int grpci1_cfg_w32(struct grpci1_priv *priv, unsigned int bus,
0103                 unsigned int devfn, int where, u32 val);
0104 
0105 static int grpci1_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
0106 {
0107     struct grpci1_priv *priv = dev->bus->sysdata;
0108     int irq_group;
0109 
0110     /* Use default IRQ decoding on PCI BUS0 according slot numbering */
0111     irq_group = slot & 0x3;
0112     pin = ((pin - 1) + irq_group) & 0x3;
0113 
0114     return priv->irq_map[pin];
0115 }
0116 
0117 static int grpci1_cfg_r32(struct grpci1_priv *priv, unsigned int bus,
0118                 unsigned int devfn, int where, u32 *val)
0119 {
0120     u32 *pci_conf, tmp, cfg;
0121 
0122     if (where & 0x3)
0123         return -EINVAL;
0124 
0125     if (bus == 0) {
0126         devfn += (0x8 * 6); /* start at AD16=Device0 */
0127     } else if (bus == TGT) {
0128         bus = 0;
0129         devfn = 0; /* special case: bridge controller itself */
0130     }
0131 
0132     /* Select bus */
0133     cfg = REGLOAD(priv->regs->cfg_stat);
0134     REGSTORE(priv->regs->cfg_stat, (cfg & ~(0xf << 23)) | (bus << 23));
0135 
0136     /* do read access */
0137     pci_conf = (u32 *) (priv->pci_conf | (devfn << 8) | (where & 0xfc));
0138     tmp = LEON3_BYPASS_LOAD_PA(pci_conf);
0139 
0140     /* check if master abort was received */
0141     if (REGLOAD(priv->regs->cfg_stat) & CFGSTAT_CTO) {
0142         *val = 0xffffffff;
0143         /* Clear Master abort bit in PCI cfg space (is set) */
0144         tmp = REGLOAD(priv->regs->stat_cmd);
0145         grpci1_cfg_w32(priv, TGT, 0, PCI_COMMAND, tmp);
0146     } else {
0147         /* Bus always little endian (unaffected by byte-swapping) */
0148         *val = swab32(tmp);
0149     }
0150 
0151     return 0;
0152 }
0153 
0154 static int grpci1_cfg_r16(struct grpci1_priv *priv, unsigned int bus,
0155                 unsigned int devfn, int where, u32 *val)
0156 {
0157     u32 v;
0158     int ret;
0159 
0160     if (where & 0x1)
0161         return -EINVAL;
0162     ret = grpci1_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
0163     *val = 0xffff & (v >> (8 * (where & 0x3)));
0164     return ret;
0165 }
0166 
0167 static int grpci1_cfg_r8(struct grpci1_priv *priv, unsigned int bus,
0168                 unsigned int devfn, int where, u32 *val)
0169 {
0170     u32 v;
0171     int ret;
0172 
0173     ret = grpci1_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
0174     *val = 0xff & (v >> (8 * (where & 3)));
0175 
0176     return ret;
0177 }
0178 
0179 static int grpci1_cfg_w32(struct grpci1_priv *priv, unsigned int bus,
0180                 unsigned int devfn, int where, u32 val)
0181 {
0182     unsigned int *pci_conf;
0183     u32 cfg;
0184 
0185     if (where & 0x3)
0186         return -EINVAL;
0187 
0188     if (bus == 0) {
0189         devfn += (0x8 * 6); /* start at AD16=Device0 */
0190     } else if (bus == TGT) {
0191         bus = 0;
0192         devfn = 0; /* special case: bridge controller itself */
0193     }
0194 
0195     /* Select bus */
0196     cfg = REGLOAD(priv->regs->cfg_stat);
0197     REGSTORE(priv->regs->cfg_stat, (cfg & ~(0xf << 23)) | (bus << 23));
0198 
0199     pci_conf = (unsigned int *) (priv->pci_conf |
0200                         (devfn << 8) | (where & 0xfc));
0201     LEON3_BYPASS_STORE_PA(pci_conf, swab32(val));
0202 
0203     return 0;
0204 }
0205 
0206 static int grpci1_cfg_w16(struct grpci1_priv *priv, unsigned int bus,
0207                 unsigned int devfn, int where, u32 val)
0208 {
0209     int ret;
0210     u32 v;
0211 
0212     if (where & 0x1)
0213         return -EINVAL;
0214     ret = grpci1_cfg_r32(priv, bus, devfn, where&~3, &v);
0215     if (ret)
0216         return ret;
0217     v = (v & ~(0xffff << (8 * (where & 0x3)))) |
0218         ((0xffff & val) << (8 * (where & 0x3)));
0219     return grpci1_cfg_w32(priv, bus, devfn, where & ~0x3, v);
0220 }
0221 
0222 static int grpci1_cfg_w8(struct grpci1_priv *priv, unsigned int bus,
0223                 unsigned int devfn, int where, u32 val)
0224 {
0225     int ret;
0226     u32 v;
0227 
0228     ret = grpci1_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
0229     if (ret != 0)
0230         return ret;
0231     v = (v & ~(0xff << (8 * (where & 0x3)))) |
0232         ((0xff & val) << (8 * (where & 0x3)));
0233     return grpci1_cfg_w32(priv, bus, devfn, where & ~0x3, v);
0234 }
0235 
0236 /* Read from Configuration Space. When entering here the PCI layer has taken
0237  * the pci_lock spinlock and IRQ is off.
0238  */
0239 static int grpci1_read_config(struct pci_bus *bus, unsigned int devfn,
0240                   int where, int size, u32 *val)
0241 {
0242     struct grpci1_priv *priv = grpci1priv;
0243     unsigned int busno = bus->number;
0244     int ret;
0245 
0246     if (PCI_SLOT(devfn) > 15 || busno > 15) {
0247         *val = ~0;
0248         return 0;
0249     }
0250 
0251     switch (size) {
0252     case 1:
0253         ret = grpci1_cfg_r8(priv, busno, devfn, where, val);
0254         break;
0255     case 2:
0256         ret = grpci1_cfg_r16(priv, busno, devfn, where, val);
0257         break;
0258     case 4:
0259         ret = grpci1_cfg_r32(priv, busno, devfn, where, val);
0260         break;
0261     default:
0262         ret = -EINVAL;
0263         break;
0264     }
0265 
0266 #ifdef GRPCI1_DEBUG_CFGACCESS
0267     printk(KERN_INFO
0268         "grpci1_read_config: [%02x:%02x:%x] ofs=%d val=%x size=%d\n",
0269         busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where, *val, size);
0270 #endif
0271 
0272     return ret;
0273 }
0274 
0275 /* Write to Configuration Space. When entering here the PCI layer has taken
0276  * the pci_lock spinlock and IRQ is off.
0277  */
0278 static int grpci1_write_config(struct pci_bus *bus, unsigned int devfn,
0279                    int where, int size, u32 val)
0280 {
0281     struct grpci1_priv *priv = grpci1priv;
0282     unsigned int busno = bus->number;
0283 
0284     if (PCI_SLOT(devfn) > 15 || busno > 15)
0285         return 0;
0286 
0287 #ifdef GRPCI1_DEBUG_CFGACCESS
0288     printk(KERN_INFO
0289         "grpci1_write_config: [%02x:%02x:%x] ofs=%d size=%d val=%x\n",
0290         busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val);
0291 #endif
0292 
0293     switch (size) {
0294     default:
0295         return -EINVAL;
0296     case 1:
0297         return grpci1_cfg_w8(priv, busno, devfn, where, val);
0298     case 2:
0299         return grpci1_cfg_w16(priv, busno, devfn, where, val);
0300     case 4:
0301         return grpci1_cfg_w32(priv, busno, devfn, where, val);
0302     }
0303 }
0304 
0305 static struct pci_ops grpci1_ops = {
0306     .read =     grpci1_read_config,
0307     .write =    grpci1_write_config,
0308 };
0309 
0310 /* GENIRQ IRQ chip implementation for grpci1 irqmode=0..2. In configuration
0311  * 3 where all PCI Interrupts has a separate IRQ on the system IRQ controller
0312  * this is not needed and the standard IRQ controller can be used.
0313  */
0314 
0315 static void grpci1_mask_irq(struct irq_data *data)
0316 {
0317     u32 irqidx;
0318     struct grpci1_priv *priv = grpci1priv;
0319 
0320     irqidx = (u32)data->chip_data - 1;
0321     if (irqidx > 3) /* only mask PCI interrupts here */
0322         return;
0323     irqidx += IRQ_MASK_BIT;
0324 
0325     REGSTORE(priv->regs->irq, REGLOAD(priv->regs->irq) & ~(1 << irqidx));
0326 }
0327 
0328 static void grpci1_unmask_irq(struct irq_data *data)
0329 {
0330     u32 irqidx;
0331     struct grpci1_priv *priv = grpci1priv;
0332 
0333     irqidx = (u32)data->chip_data - 1;
0334     if (irqidx > 3) /* only unmask PCI interrupts here */
0335         return;
0336     irqidx += IRQ_MASK_BIT;
0337 
0338     REGSTORE(priv->regs->irq, REGLOAD(priv->regs->irq) | (1 << irqidx));
0339 }
0340 
0341 static unsigned int grpci1_startup_irq(struct irq_data *data)
0342 {
0343     grpci1_unmask_irq(data);
0344     return 0;
0345 }
0346 
0347 static void grpci1_shutdown_irq(struct irq_data *data)
0348 {
0349     grpci1_mask_irq(data);
0350 }
0351 
0352 static struct irq_chip grpci1_irq = {
0353     .name       = "grpci1",
0354     .irq_startup    = grpci1_startup_irq,
0355     .irq_shutdown   = grpci1_shutdown_irq,
0356     .irq_mask   = grpci1_mask_irq,
0357     .irq_unmask = grpci1_unmask_irq,
0358 };
0359 
0360 /* Handle one or multiple IRQs from the PCI core */
0361 static void grpci1_pci_flow_irq(struct irq_desc *desc)
0362 {
0363     struct grpci1_priv *priv = grpci1priv;
0364     int i, ack = 0;
0365     unsigned int irqreg;
0366 
0367     irqreg = REGLOAD(priv->regs->irq);
0368     irqreg = (irqreg >> IRQ_MASK_BIT) & irqreg;
0369 
0370     /* Error Interrupt? */
0371     if (irqreg & IRQ_ALL_ERRORS) {
0372         generic_handle_irq(priv->irq_err);
0373         ack = 1;
0374     }
0375 
0376     /* PCI Interrupt? */
0377     if (irqreg & IRQ_INTX) {
0378         /* Call respective PCI Interrupt handler */
0379         for (i = 0; i < 4; i++) {
0380             if (irqreg & (1 << i))
0381                 generic_handle_irq(priv->irq_map[i]);
0382         }
0383         ack = 1;
0384     }
0385 
0386     /*
0387      * Call "first level" IRQ chip end-of-irq handler. It will ACK LEON IRQ
0388      * Controller, this must be done after IRQ sources have been handled to
0389      * avoid double IRQ generation
0390      */
0391     if (ack)
0392         desc->irq_data.chip->irq_eoi(&desc->irq_data);
0393 }
0394 
0395 /* Create a virtual IRQ */
0396 static unsigned int grpci1_build_device_irq(unsigned int irq)
0397 {
0398     unsigned int virq = 0, pil;
0399 
0400     pil = 1 << 8;
0401     virq = irq_alloc(irq, pil);
0402     if (virq == 0)
0403         goto out;
0404 
0405     irq_set_chip_and_handler_name(virq, &grpci1_irq, handle_simple_irq,
0406                       "pcilvl");
0407     irq_set_chip_data(virq, (void *)irq);
0408 
0409 out:
0410     return virq;
0411 }
0412 
0413 /*
0414  * Initialize mappings AMBA<->PCI, clear IRQ state, setup PCI interface
0415  *
0416  * Target BARs:
0417  *  BAR0: unused in this implementation
0418  *  BAR1: peripheral DMA to host's memory (size at least 256MByte)
0419  *  BAR2..BAR5: not implemented in hardware
0420  */
0421 static void grpci1_hw_init(struct grpci1_priv *priv)
0422 {
0423     u32 ahbadr, bar_sz, data, pciadr;
0424     struct grpci1_regs __iomem *regs = priv->regs;
0425 
0426     /* set 1:1 mapping between AHB -> PCI memory space */
0427     REGSTORE(regs->cfg_stat, priv->pci_area & 0xf0000000);
0428 
0429     /* map PCI accesses to target BAR1 to Linux kernel memory 1:1 */
0430     ahbadr = 0xf0000000 & (u32)__pa(PAGE_ALIGN((unsigned long) &_end));
0431     REGSTORE(regs->page1, ahbadr);
0432 
0433     /* translate I/O accesses to 0, I/O Space always @ PCI low 64Kbytes */
0434     REGSTORE(regs->iomap, REGLOAD(regs->iomap) & 0x0000ffff);
0435 
0436     /* disable and clear pending interrupts */
0437     REGSTORE(regs->irq, 0);
0438 
0439     /* Setup BAR0 outside access range so that it does not conflict with
0440      * peripheral DMA. There is no need to set up the PAGE0 register.
0441      */
0442     grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
0443     grpci1_cfg_r32(priv, TGT, 0, PCI_BASE_ADDRESS_0, &bar_sz);
0444     bar_sz = ~bar_sz + 1;
0445     pciadr = priv->pci_area - bar_sz;
0446     grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0, pciadr);
0447 
0448     /*
0449      * Setup the Host's PCI Target BAR1 for other peripherals to access,
0450      * and do DMA to the host's memory.
0451      */
0452     grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_1, ahbadr);
0453 
0454     /*
0455      * Setup Latency Timer and cache line size. Default cache line
0456      * size will result in poor performance (256 word fetches), 0xff
0457      * will set it according to the max size of the PCI FIFO.
0458      */
0459     grpci1_cfg_w8(priv, TGT, 0, PCI_CACHE_LINE_SIZE, 0xff);
0460     grpci1_cfg_w8(priv, TGT, 0, PCI_LATENCY_TIMER, 0x40);
0461 
0462     /* set as bus master, enable pci memory responses, clear status bits */
0463     grpci1_cfg_r32(priv, TGT, 0, PCI_COMMAND, &data);
0464     data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
0465     grpci1_cfg_w32(priv, TGT, 0, PCI_COMMAND, data);
0466 }
0467 
0468 static irqreturn_t grpci1_jump_interrupt(int irq, void *arg)
0469 {
0470     struct grpci1_priv *priv = arg;
0471     dev_err(priv->dev, "Jump IRQ happened\n");
0472     return IRQ_NONE;
0473 }
0474 
0475 /* Handle GRPCI1 Error Interrupt */
0476 static irqreturn_t grpci1_err_interrupt(int irq, void *arg)
0477 {
0478     struct grpci1_priv *priv = arg;
0479     u32 status;
0480 
0481     grpci1_cfg_r16(priv, TGT, 0, PCI_STATUS, &status);
0482     status &= priv->pci_err_mask;
0483 
0484     if (status == 0)
0485         return IRQ_NONE;
0486 
0487     if (status & PCI_STATUS_PARITY)
0488         dev_err(priv->dev, "Data Parity Error\n");
0489 
0490     if (status & PCI_STATUS_SIG_TARGET_ABORT)
0491         dev_err(priv->dev, "Signalled Target Abort\n");
0492 
0493     if (status & PCI_STATUS_REC_TARGET_ABORT)
0494         dev_err(priv->dev, "Received Target Abort\n");
0495 
0496     if (status & PCI_STATUS_REC_MASTER_ABORT)
0497         dev_err(priv->dev, "Received Master Abort\n");
0498 
0499     if (status & PCI_STATUS_SIG_SYSTEM_ERROR)
0500         dev_err(priv->dev, "Signalled System Error\n");
0501 
0502     if (status & PCI_STATUS_DETECTED_PARITY)
0503         dev_err(priv->dev, "Parity Error\n");
0504 
0505     /* Clear handled INT TYPE IRQs */
0506     grpci1_cfg_w16(priv, TGT, 0, PCI_STATUS, status);
0507 
0508     return IRQ_HANDLED;
0509 }
0510 
0511 static int grpci1_of_probe(struct platform_device *ofdev)
0512 {
0513     struct grpci1_regs __iomem *regs;
0514     struct grpci1_priv *priv;
0515     int err, len;
0516     const int *tmp;
0517     u32 cfg, size, err_mask;
0518     struct resource *res;
0519 
0520     if (grpci1priv) {
0521         dev_err(&ofdev->dev, "only one GRPCI1 supported\n");
0522         return -ENODEV;
0523     }
0524 
0525     if (ofdev->num_resources < 3) {
0526         dev_err(&ofdev->dev, "not enough APB/AHB resources\n");
0527         return -EIO;
0528     }
0529 
0530     priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL);
0531     if (!priv) {
0532         dev_err(&ofdev->dev, "memory allocation failed\n");
0533         return -ENOMEM;
0534     }
0535     platform_set_drvdata(ofdev, priv);
0536     priv->dev = &ofdev->dev;
0537 
0538     /* find device register base address */
0539     res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
0540     regs = devm_ioremap_resource(&ofdev->dev, res);
0541     if (IS_ERR(regs))
0542         return PTR_ERR(regs);
0543 
0544     /*
0545      * check that we're in Host Slot and that we can act as a Host Bridge
0546      * and not only as target/peripheral.
0547      */
0548     cfg = REGLOAD(regs->cfg_stat);
0549     if ((cfg & CFGSTAT_HOST) == 0) {
0550         dev_err(&ofdev->dev, "not in host system slot\n");
0551         return -EIO;
0552     }
0553 
0554     /* check that BAR1 support 256 MByte so that we can map kernel space */
0555     REGSTORE(regs->page1, 0xffffffff);
0556     size = ~REGLOAD(regs->page1) + 1;
0557     if (size < 0x10000000) {
0558         dev_err(&ofdev->dev, "BAR1 must be at least 256MByte\n");
0559         return -EIO;
0560     }
0561 
0562     /* hardware must support little-endian PCI (byte-twisting) */
0563     if ((REGLOAD(regs->page0) & PAGE0_BTEN) == 0) {
0564         dev_err(&ofdev->dev, "byte-twisting is required\n");
0565         return -EIO;
0566     }
0567 
0568     priv->regs = regs;
0569     priv->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
0570     dev_info(&ofdev->dev, "host found at 0x%p, irq%d\n", regs, priv->irq);
0571 
0572     /* Find PCI Memory, I/O and Configuration Space Windows */
0573     priv->pci_area = ofdev->resource[1].start;
0574     priv->pci_area_end = ofdev->resource[1].end+1;
0575     priv->pci_io = ofdev->resource[2].start;
0576     priv->pci_conf = ofdev->resource[2].start + 0x10000;
0577     priv->pci_conf_end = priv->pci_conf + 0x10000;
0578     priv->pci_io_va = (unsigned long)ioremap(priv->pci_io, 0x10000);
0579     if (!priv->pci_io_va) {
0580         dev_err(&ofdev->dev, "unable to map PCI I/O area\n");
0581         return -EIO;
0582     }
0583 
0584     printk(KERN_INFO
0585         "GRPCI1: MEMORY SPACE [0x%08lx - 0x%08lx]\n"
0586         "        I/O    SPACE [0x%08lx - 0x%08lx]\n"
0587         "        CONFIG SPACE [0x%08lx - 0x%08lx]\n",
0588         priv->pci_area, priv->pci_area_end-1,
0589         priv->pci_io, priv->pci_conf-1,
0590         priv->pci_conf, priv->pci_conf_end-1);
0591 
0592     /*
0593      * I/O Space resources in I/O Window mapped into Virtual Adr Space
0594      * We never use low 4KB because some devices seem have problems using
0595      * address 0.
0596      */
0597     priv->info.io_space.name = "GRPCI1 PCI I/O Space";
0598     priv->info.io_space.start = priv->pci_io_va + 0x1000;
0599     priv->info.io_space.end = priv->pci_io_va + 0x10000 - 1;
0600     priv->info.io_space.flags = IORESOURCE_IO;
0601 
0602     /*
0603      * grpci1 has no prefetchable memory, map everything as
0604      * non-prefetchable memory
0605      */
0606     priv->info.mem_space.name = "GRPCI1 PCI MEM Space";
0607     priv->info.mem_space.start = priv->pci_area;
0608     priv->info.mem_space.end = priv->pci_area_end - 1;
0609     priv->info.mem_space.flags = IORESOURCE_MEM;
0610 
0611     if (request_resource(&iomem_resource, &priv->info.mem_space) < 0) {
0612         dev_err(&ofdev->dev, "unable to request PCI memory area\n");
0613         err = -ENOMEM;
0614         goto err1;
0615     }
0616 
0617     if (request_resource(&ioport_resource, &priv->info.io_space) < 0) {
0618         dev_err(&ofdev->dev, "unable to request PCI I/O area\n");
0619         err = -ENOMEM;
0620         goto err2;
0621     }
0622 
0623     /* setup maximum supported PCI buses */
0624     priv->info.busn.name = "GRPCI1 busn";
0625     priv->info.busn.start = 0;
0626     priv->info.busn.end = 15;
0627 
0628     grpci1priv = priv;
0629 
0630     /* Initialize hardware */
0631     grpci1_hw_init(priv);
0632 
0633     /*
0634      * Get PCI Interrupt to System IRQ mapping and setup IRQ handling
0635      * Error IRQ. All PCI and PCI-Error interrupts are shared using the
0636      * same system IRQ.
0637      */
0638     leon_update_virq_handling(priv->irq, grpci1_pci_flow_irq, "pcilvl", 0);
0639 
0640     priv->irq_map[0] = grpci1_build_device_irq(1);
0641     priv->irq_map[1] = grpci1_build_device_irq(2);
0642     priv->irq_map[2] = grpci1_build_device_irq(3);
0643     priv->irq_map[3] = grpci1_build_device_irq(4);
0644     priv->irq_err = grpci1_build_device_irq(5);
0645 
0646     printk(KERN_INFO "        PCI INTA..D#: IRQ%d, IRQ%d, IRQ%d, IRQ%d\n",
0647         priv->irq_map[0], priv->irq_map[1], priv->irq_map[2],
0648         priv->irq_map[3]);
0649 
0650     /* Enable IRQs on LEON IRQ controller */
0651     err = devm_request_irq(&ofdev->dev, priv->irq, grpci1_jump_interrupt, 0,
0652                 "GRPCI1_JUMP", priv);
0653     if (err) {
0654         dev_err(&ofdev->dev, "ERR IRQ request failed: %d\n", err);
0655         goto err3;
0656     }
0657 
0658     /* Setup IRQ handler for access errors */
0659     err = devm_request_irq(&ofdev->dev, priv->irq_err,
0660                 grpci1_err_interrupt, IRQF_SHARED, "GRPCI1_ERR",
0661                 priv);
0662     if (err) {
0663         dev_err(&ofdev->dev, "ERR VIRQ request failed: %d\n", err);
0664         goto err3;
0665     }
0666 
0667     tmp = of_get_property(ofdev->dev.of_node, "all_pci_errors", &len);
0668     if (tmp && (len == 4)) {
0669         priv->pci_err_mask = ALL_PCI_ERRORS;
0670         err_mask = IRQ_ALL_ERRORS << IRQ_MASK_BIT;
0671     } else {
0672         priv->pci_err_mask = DEF_PCI_ERRORS;
0673         err_mask = IRQ_DEF_ERRORS << IRQ_MASK_BIT;
0674     }
0675 
0676     /*
0677      * Enable Error Interrupts. PCI interrupts are unmasked once request_irq
0678      * is called by the PCI Device drivers
0679      */
0680     REGSTORE(regs->irq, err_mask);
0681 
0682     /* Init common layer and scan buses */
0683     priv->info.ops = &grpci1_ops;
0684     priv->info.map_irq = grpci1_map_irq;
0685     leon_pci_init(ofdev, &priv->info);
0686 
0687     return 0;
0688 
0689 err3:
0690     release_resource(&priv->info.io_space);
0691 err2:
0692     release_resource(&priv->info.mem_space);
0693 err1:
0694     iounmap((void __iomem *)priv->pci_io_va);
0695     grpci1priv = NULL;
0696     return err;
0697 }
0698 
0699 static const struct of_device_id grpci1_of_match[] __initconst = {
0700     {
0701      .name = "GAISLER_PCIFBRG",
0702      },
0703     {
0704      .name = "01_014",
0705      },
0706     {},
0707 };
0708 
0709 static struct platform_driver grpci1_of_driver = {
0710     .driver = {
0711         .name = "grpci1",
0712         .of_match_table = grpci1_of_match,
0713     },
0714     .probe = grpci1_of_probe,
0715 };
0716 
0717 static int __init grpci1_init(void)
0718 {
0719     return platform_driver_register(&grpci1_of_driver);
0720 }
0721 
0722 subsys_initcall(grpci1_init);
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