sparc/kernel/ivec.S

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002     /* The registers for cross calls will be:
0003      *
0004      * DATA 0: [low 32-bits]  Address of function to call, jmp to this
0005      *         [high 32-bits] MMU Context Argument 0, place in %g5
0006      * DATA 1: Address Argument 1, place in %g1
0007      * DATA 2: Address Argument 2, place in %g7
0008      *
0009      * With this method we can do most of the cross-call tlb/cache
0010      * flushing very quickly.
0011      */
0012     .align      32
0013     .globl      do_ivec
0014     .type       do_ivec,#function
0015 do_ivec:
0016     mov     0x40, %g3
0017     ldxa        [%g3 + %g0] ASI_INTR_R, %g3
0018     sethi       %hi(KERNBASE), %g4
0019     cmp     %g3, %g4
0020     bgeu,pn     %xcc, do_ivec_xcall
0021      srlx       %g3, 32, %g5
0022     stxa        %g0, [%g0] ASI_INTR_RECEIVE
0023     membar      #Sync
0024
0025     sethi       %hi(ivector_table_pa), %g2
0026     ldx     [%g2 + %lo(ivector_table_pa)], %g2
0027     sllx        %g3, 4, %g3
0028     add     %g2, %g3, %g3
0029
0030     TRAP_LOAD_IRQ_WORK_PA(%g6, %g1)
0031
0032     ldx     [%g6], %g5
0033     stxa        %g5, [%g3] ASI_PHYS_USE_EC
0034     stx     %g3, [%g6]
0035     wr      %g0, 1 << PIL_DEVICE_IRQ, %set_softint
0036     retry
0037 do_ivec_xcall:
0038     mov     0x50, %g1
0039     ldxa        [%g1 + %g0] ASI_INTR_R, %g1
0040     srl     %g3, 0, %g3
0041
0042     mov     0x60, %g7
0043     ldxa        [%g7 + %g0] ASI_INTR_R, %g7
0044     stxa        %g0, [%g0] ASI_INTR_RECEIVE
0045     membar      #Sync
0046     ba,pt       %xcc, 1f
0047      nop
0048
0049     .align      32
0050 1:  jmpl        %g3, %g0
0051      nop
0052     .size       do_ivec,.-do_ivec