sparc/kernel/hvtramp.S

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* hvtramp.S: Hypervisor start-cpu trampoline code.
0003  *
0004  * Copyright (C) 2007, 2008 David S. Miller <davem@davemloft.net>
0005  */
0006
0007
0008 #include <asm/thread_info.h>
0009 #include <asm/hypervisor.h>
0010 #include <asm/scratchpad.h>
0011 #include <asm/spitfire.h>
0012 #include <asm/hvtramp.h>
0013 #include <asm/pstate.h>
0014 #include <asm/ptrace.h>
0015 #include <asm/head.h>
0016 #include <asm/asi.h>
0017 #include <asm/pil.h>
0018
0019     .align      8
0020     .globl      hv_cpu_startup, hv_cpu_startup_end
0021
0022     /* This code executes directly out of the hypervisor
0023      * with physical addressing (va==pa).  %o0 contains
0024      * our client argument which for Linux points to
0025      * a descriptor data structure which defines the
0026      * MMU entries we need to load up.
0027      *
0028      * After we set things up we enable the MMU and call
0029      * into the kernel.
0030      *
0031      * First setup basic privileged cpu state.
0032      */
0033 hv_cpu_startup:
0034     SET_GL(0)
0035     wrpr        %g0, PIL_NORMAL_MAX, %pil
0036     wrpr        %g0, 0, %canrestore
0037     wrpr        %g0, 0, %otherwin
0038     wrpr        %g0, 6, %cansave
0039     wrpr        %g0, 6, %cleanwin
0040     wrpr        %g0, 0, %cwp
0041     wrpr        %g0, 0, %wstate
0042     wrpr        %g0, 0, %tl
0043
0044     sethi       %hi(sparc64_ttable_tl0), %g1
0045     wrpr        %g1, %tba
0046
0047     mov     %o0, %l0
0048
0049     lduw        [%l0 + HVTRAMP_DESCR_CPU], %g1
0050     mov     SCRATCHPAD_CPUID, %g2
0051     stxa        %g1, [%g2] ASI_SCRATCHPAD
0052
0053     ldx     [%l0 + HVTRAMP_DESCR_FAULT_INFO_VA], %g2
0054     stxa        %g2, [%g0] ASI_SCRATCHPAD
0055
0056     mov     0, %l1
0057     lduw        [%l0 + HVTRAMP_DESCR_NUM_MAPPINGS], %l2
0058     add     %l0, HVTRAMP_DESCR_MAPS, %l3
0059
0060 1:  ldx     [%l3 + HVTRAMP_MAPPING_VADDR], %o0
0061     clr     %o1
0062     ldx     [%l3 + HVTRAMP_MAPPING_TTE], %o2
0063     mov     HV_MMU_IMMU | HV_MMU_DMMU, %o3
0064     mov     HV_FAST_MMU_MAP_PERM_ADDR, %o5
0065     ta      HV_FAST_TRAP
0066
0067     brnz,pn     %o0, 80f
0068      nop
0069
0070     add     %l1, 1, %l1
0071     cmp     %l1, %l2
0072     blt,a,pt    %xcc, 1b
0073      add        %l3, HVTRAMP_MAPPING_SIZE, %l3
0074
0075     ldx     [%l0 + HVTRAMP_DESCR_FAULT_INFO_PA], %o0
0076     mov     HV_FAST_MMU_FAULT_AREA_CONF, %o5
0077     ta      HV_FAST_TRAP
0078
0079     brnz,pn     %o0, 80f
0080      nop
0081
0082     wrpr        %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
0083
0084     ldx     [%l0 + HVTRAMP_DESCR_THREAD_REG], %l6
0085
0086     mov     1, %o0
0087     set     1f, %o1
0088     mov     HV_FAST_MMU_ENABLE, %o5
0089     ta      HV_FAST_TRAP
0090
0091     ba,pt       %xcc, 80f
0092      nop
0093
0094 1:
0095     wr      %g0, 0, %fprs
0096     wr      %g0, ASI_P, %asi
0097
0098     mov     PRIMARY_CONTEXT, %g7
0099     stxa        %g0, [%g7] ASI_MMU
0100     membar      #Sync
0101
0102     mov     SECONDARY_CONTEXT, %g7
0103     stxa        %g0, [%g7] ASI_MMU
0104     membar      #Sync
0105
0106     mov     %l6, %g6
0107     ldx     [%g6 + TI_TASK], %g4
0108
0109     mov     1, %g5
0110     sllx        %g5, THREAD_SHIFT, %g5
0111     sub     %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
0112     add     %g6, %g5, %sp
0113
0114     call        init_irqwork_curcpu
0115      nop
0116     call        hard_smp_processor_id
0117      nop
0118
0119     call        sun4v_register_mondo_queues
0120      nop
0121
0122     call        init_cur_cpu_trap
0123      mov        %g6, %o0
0124
0125     wrpr        %g0, (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE), %pstate
0126
0127     call        smp_callin
0128      nop
0129
0130     call        cpu_panic
0131      nop
0132
0133 80: ba,pt       %xcc, 80b
0134      nop
0135
0136     .align      8
0137 hv_cpu_startup_end: