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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002     /* These get patched into the trap table at boot time
0003      * once we know we have a cheetah processor.
0004      */
0005     .globl      cheetah_fecc_trap_vector
0006     .type       cheetah_fecc_trap_vector,#function
0007 cheetah_fecc_trap_vector:
0008     membar      #Sync
0009     ldxa        [%g0] ASI_DCU_CONTROL_REG, %g1
0010     andn        %g1, DCU_DC | DCU_IC, %g1
0011     stxa        %g1, [%g0] ASI_DCU_CONTROL_REG
0012     membar      #Sync
0013     sethi       %hi(cheetah_fast_ecc), %g2
0014     jmpl        %g2 + %lo(cheetah_fast_ecc), %g0
0015      mov        0, %g1
0016     .size       cheetah_fecc_trap_vector,.-cheetah_fecc_trap_vector
0017 
0018     .globl      cheetah_fecc_trap_vector_tl1
0019     .type       cheetah_fecc_trap_vector_tl1,#function
0020 cheetah_fecc_trap_vector_tl1:
0021     membar      #Sync
0022     ldxa        [%g0] ASI_DCU_CONTROL_REG, %g1
0023     andn        %g1, DCU_DC | DCU_IC, %g1
0024     stxa        %g1, [%g0] ASI_DCU_CONTROL_REG
0025     membar      #Sync
0026     sethi       %hi(cheetah_fast_ecc), %g2
0027     jmpl        %g2 + %lo(cheetah_fast_ecc), %g0
0028      mov        1, %g1
0029     .size       cheetah_fecc_trap_vector_tl1,.-cheetah_fecc_trap_vector_tl1
0030 
0031     .globl  cheetah_cee_trap_vector
0032     .type   cheetah_cee_trap_vector,#function
0033 cheetah_cee_trap_vector:
0034     membar      #Sync
0035     ldxa        [%g0] ASI_DCU_CONTROL_REG, %g1
0036     andn        %g1, DCU_IC, %g1
0037     stxa        %g1, [%g0] ASI_DCU_CONTROL_REG
0038     membar      #Sync
0039     sethi       %hi(cheetah_cee), %g2
0040     jmpl        %g2 + %lo(cheetah_cee), %g0
0041      mov        0, %g1
0042     .size       cheetah_cee_trap_vector,.-cheetah_cee_trap_vector
0043 
0044     .globl      cheetah_cee_trap_vector_tl1
0045     .type       cheetah_cee_trap_vector_tl1,#function
0046 cheetah_cee_trap_vector_tl1:
0047     membar      #Sync
0048     ldxa        [%g0] ASI_DCU_CONTROL_REG, %g1
0049     andn        %g1, DCU_IC, %g1
0050     stxa        %g1, [%g0] ASI_DCU_CONTROL_REG
0051     membar      #Sync
0052     sethi       %hi(cheetah_cee), %g2
0053     jmpl        %g2 + %lo(cheetah_cee), %g0
0054      mov        1, %g1
0055     .size       cheetah_cee_trap_vector_tl1,.-cheetah_cee_trap_vector_tl1
0056 
0057     .globl  cheetah_deferred_trap_vector
0058     .type   cheetah_deferred_trap_vector,#function
0059 cheetah_deferred_trap_vector:
0060     membar      #Sync
0061     ldxa        [%g0] ASI_DCU_CONTROL_REG, %g1;
0062     andn        %g1, DCU_DC | DCU_IC, %g1;
0063     stxa        %g1, [%g0] ASI_DCU_CONTROL_REG;
0064     membar      #Sync;
0065     sethi       %hi(cheetah_deferred_trap), %g2
0066     jmpl        %g2 + %lo(cheetah_deferred_trap), %g0
0067      mov        0, %g1
0068     .size       cheetah_deferred_trap_vector,.-cheetah_deferred_trap_vector
0069 
0070     .globl      cheetah_deferred_trap_vector_tl1
0071     .type       cheetah_deferred_trap_vector_tl1,#function
0072 cheetah_deferred_trap_vector_tl1:
0073     membar      #Sync;
0074     ldxa        [%g0] ASI_DCU_CONTROL_REG, %g1;
0075     andn        %g1, DCU_DC | DCU_IC, %g1;
0076     stxa        %g1, [%g0] ASI_DCU_CONTROL_REG;
0077     membar      #Sync;
0078     sethi       %hi(cheetah_deferred_trap), %g2
0079     jmpl        %g2 + %lo(cheetah_deferred_trap), %g0
0080      mov        1, %g1
0081     .size       cheetah_deferred_trap_vector_tl1,.-cheetah_deferred_trap_vector_tl1
0082 
0083     /* Cheetah+ specific traps. These are for the new I/D cache parity
0084      * error traps.  The first argument to cheetah_plus_parity_handler
0085      * is encoded as follows:
0086      *
0087      * Bit0:    0=dcache,1=icache
0088      * Bit1:    0=recoverable,1=unrecoverable
0089      */
0090     .globl      cheetah_plus_dcpe_trap_vector
0091     .type       cheetah_plus_dcpe_trap_vector,#function
0092 cheetah_plus_dcpe_trap_vector:
0093     membar      #Sync
0094     sethi       %hi(do_cheetah_plus_data_parity), %g7
0095     jmpl        %g7 + %lo(do_cheetah_plus_data_parity), %g0
0096      nop
0097     nop
0098     nop
0099     nop
0100     nop
0101     .size       cheetah_plus_dcpe_trap_vector,.-cheetah_plus_dcpe_trap_vector
0102 
0103     .type       do_cheetah_plus_data_parity,#function
0104 do_cheetah_plus_data_parity:
0105     rdpr        %pil, %g2
0106     wrpr        %g0, PIL_NORMAL_MAX, %pil
0107     ba,pt       %xcc, etrap_irq
0108      rd     %pc, %g7
0109 #ifdef CONFIG_TRACE_IRQFLAGS
0110     call        trace_hardirqs_off
0111      nop
0112 #endif
0113     mov     0x0, %o0
0114     call        cheetah_plus_parity_error
0115      add        %sp, PTREGS_OFF, %o1
0116     ba,a,pt     %xcc, rtrap_irq
0117     .size       do_cheetah_plus_data_parity,.-do_cheetah_plus_data_parity
0118 
0119     .globl      cheetah_plus_dcpe_trap_vector_tl1
0120     .type       cheetah_plus_dcpe_trap_vector_tl1,#function
0121 cheetah_plus_dcpe_trap_vector_tl1:
0122     membar      #Sync
0123     wrpr        PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
0124     sethi       %hi(do_dcpe_tl1), %g3
0125     jmpl        %g3 + %lo(do_dcpe_tl1), %g0
0126      nop
0127     nop
0128     nop
0129     nop
0130     .size       cheetah_plus_dcpe_trap_vector_tl1,.-cheetah_plus_dcpe_trap_vector_tl1
0131 
0132     .globl      cheetah_plus_icpe_trap_vector
0133     .type       cheetah_plus_icpe_trap_vector,#function
0134 cheetah_plus_icpe_trap_vector:
0135     membar      #Sync
0136     sethi       %hi(do_cheetah_plus_insn_parity), %g7
0137     jmpl        %g7 + %lo(do_cheetah_plus_insn_parity), %g0
0138      nop
0139     nop
0140     nop
0141     nop
0142     nop
0143     .size       cheetah_plus_icpe_trap_vector,.-cheetah_plus_icpe_trap_vector
0144 
0145     .type       do_cheetah_plus_insn_parity,#function
0146 do_cheetah_plus_insn_parity:
0147     rdpr        %pil, %g2
0148     wrpr        %g0, PIL_NORMAL_MAX, %pil
0149     ba,pt       %xcc, etrap_irq
0150      rd     %pc, %g7
0151 #ifdef CONFIG_TRACE_IRQFLAGS
0152     call        trace_hardirqs_off
0153      nop
0154 #endif
0155     mov     0x1, %o0
0156     call        cheetah_plus_parity_error
0157      add        %sp, PTREGS_OFF, %o1
0158     ba,a,pt     %xcc, rtrap_irq
0159     .size       do_cheetah_plus_insn_parity,.-do_cheetah_plus_insn_parity
0160 
0161     .globl      cheetah_plus_icpe_trap_vector_tl1
0162     .type       cheetah_plus_icpe_trap_vector_tl1,#function
0163 cheetah_plus_icpe_trap_vector_tl1:
0164     membar      #Sync
0165     wrpr        PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
0166     sethi       %hi(do_icpe_tl1), %g3
0167     jmpl        %g3 + %lo(do_icpe_tl1), %g0
0168      nop
0169     nop
0170     nop
0171     nop
0172     .size       cheetah_plus_icpe_trap_vector_tl1,.-cheetah_plus_icpe_trap_vector_tl1
0173 
0174     /* If we take one of these traps when tl >= 1, then we
0175      * jump to interrupt globals.  If some trap level above us
0176      * was also using interrupt globals, we cannot recover.
0177      * We may use all interrupt global registers except %g6.
0178      */
0179     .globl      do_dcpe_tl1
0180     .type       do_dcpe_tl1,#function
0181 do_dcpe_tl1:
0182     rdpr        %tl, %g1        ! Save original trap level
0183     mov     1, %g2          ! Setup TSTATE checking loop
0184     sethi       %hi(TSTATE_IG), %g3 ! TSTATE mask bit
0185 1:  wrpr        %g2, %tl        ! Set trap level to check
0186     rdpr        %tstate, %g4        ! Read TSTATE for this level
0187     andcc       %g4, %g3, %g0       ! Interrupt globals in use?
0188     bne,a,pn    %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable
0189      wrpr       %g1, %tl        ! Restore original trap level
0190     add     %g2, 1, %g2     ! Next trap level
0191     cmp     %g2, %g1        ! Hit them all yet?
0192     ble,pt      %icc, 1b        ! Not yet
0193      nop
0194     wrpr        %g1, %tl        ! Restore original trap level
0195 do_dcpe_tl1_nonfatal:   /* Ok we may use interrupt globals safely. */
0196     sethi       %hi(dcache_parity_tl1_occurred), %g2
0197     lduw        [%g2 + %lo(dcache_parity_tl1_occurred)], %g1
0198     add     %g1, 1, %g1
0199     stw     %g1, [%g2 + %lo(dcache_parity_tl1_occurred)]
0200     /* Reset D-cache parity */
0201     sethi       %hi(1 << 16), %g1   ! D-cache size
0202     mov     (1 << 5), %g2       ! D-cache line size
0203     sub     %g1, %g2, %g1       ! Move down 1 cacheline
0204 1:  srl     %g1, 14, %g3        ! Compute UTAG
0205     membar      #Sync
0206     stxa        %g3, [%g1] ASI_DCACHE_UTAG
0207     membar      #Sync
0208     sub     %g2, 8, %g3     ! 64-bit data word within line
0209 2:  membar      #Sync
0210     stxa        %g0, [%g1 + %g3] ASI_DCACHE_DATA
0211     membar      #Sync
0212     subcc       %g3, 8, %g3     ! Next 64-bit data word
0213     bge,pt      %icc, 2b
0214      nop
0215     subcc       %g1, %g2, %g1       ! Next cacheline
0216     bge,pt      %icc, 1b
0217      nop
0218     ba,a,pt     %xcc, dcpe_icpe_tl1_common
0219 
0220 do_dcpe_tl1_fatal:
0221     sethi       %hi(1f), %g7
0222     ba,pt       %xcc, etraptl1
0223 1:  or      %g7, %lo(1b), %g7
0224     mov     0x2, %o0
0225     call        cheetah_plus_parity_error
0226      add        %sp, PTREGS_OFF, %o1
0227     ba,a,pt     %xcc, rtrap
0228     .size       do_dcpe_tl1,.-do_dcpe_tl1
0229 
0230     .globl      do_icpe_tl1
0231     .type       do_icpe_tl1,#function
0232 do_icpe_tl1:
0233     rdpr        %tl, %g1        ! Save original trap level
0234     mov     1, %g2          ! Setup TSTATE checking loop
0235     sethi       %hi(TSTATE_IG), %g3 ! TSTATE mask bit
0236 1:  wrpr        %g2, %tl        ! Set trap level to check
0237     rdpr        %tstate, %g4        ! Read TSTATE for this level
0238     andcc       %g4, %g3, %g0       ! Interrupt globals in use?
0239     bne,a,pn    %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable
0240      wrpr       %g1, %tl        ! Restore original trap level
0241     add     %g2, 1, %g2     ! Next trap level
0242     cmp     %g2, %g1        ! Hit them all yet?
0243     ble,pt      %icc, 1b        ! Not yet
0244      nop
0245     wrpr        %g1, %tl        ! Restore original trap level
0246 do_icpe_tl1_nonfatal:   /* Ok we may use interrupt globals safely. */
0247     sethi       %hi(icache_parity_tl1_occurred), %g2
0248     lduw        [%g2 + %lo(icache_parity_tl1_occurred)], %g1
0249     add     %g1, 1, %g1
0250     stw     %g1, [%g2 + %lo(icache_parity_tl1_occurred)]
0251     /* Flush I-cache */
0252     sethi       %hi(1 << 15), %g1   ! I-cache size
0253     mov     (1 << 5), %g2       ! I-cache line size
0254     sub     %g1, %g2, %g1
0255 1:  or      %g1, (2 << 3), %g3
0256     stxa        %g0, [%g3] ASI_IC_TAG
0257     membar      #Sync
0258     subcc       %g1, %g2, %g1
0259     bge,pt      %icc, 1b
0260      nop
0261     ba,a,pt     %xcc, dcpe_icpe_tl1_common
0262 
0263 do_icpe_tl1_fatal:
0264     sethi       %hi(1f), %g7
0265     ba,pt       %xcc, etraptl1
0266 1:  or      %g7, %lo(1b), %g7
0267     mov     0x3, %o0
0268     call        cheetah_plus_parity_error
0269      add        %sp, PTREGS_OFF, %o1
0270     ba,a,pt     %xcc, rtrap
0271     .size       do_icpe_tl1,.-do_icpe_tl1
0272     
0273     .type       dcpe_icpe_tl1_common,#function
0274 dcpe_icpe_tl1_common:
0275     /* Flush D-cache, re-enable D/I caches in DCU and finally
0276      * retry the trapping instruction.
0277      */
0278     sethi       %hi(1 << 16), %g1   ! D-cache size
0279     mov     (1 << 5), %g2       ! D-cache line size
0280     sub     %g1, %g2, %g1
0281 1:  stxa        %g0, [%g1] ASI_DCACHE_TAG
0282     membar      #Sync
0283     subcc       %g1, %g2, %g1
0284     bge,pt      %icc, 1b
0285      nop
0286     ldxa        [%g0] ASI_DCU_CONTROL_REG, %g1
0287     or      %g1, (DCU_DC | DCU_IC), %g1
0288     stxa        %g1, [%g0] ASI_DCU_CONTROL_REG
0289     membar      #Sync
0290     retry
0291     .size       dcpe_icpe_tl1_common,.-dcpe_icpe_tl1_common
0292 
0293     /* Capture I/D/E-cache state into per-cpu error scoreboard.
0294      *
0295      * %g1:     (TL>=0) ? 1 : 0
0296      * %g2:     scratch
0297      * %g3:     scratch
0298      * %g4:     AFSR
0299      * %g5:     AFAR
0300      * %g6:     unused, will have current thread ptr after etrap
0301      * %g7:     scratch
0302      */
0303     .type       __cheetah_log_error,#function
0304 __cheetah_log_error:
0305     /* Put "TL1" software bit into AFSR. */
0306     and     %g1, 0x1, %g1
0307     sllx        %g1, 63, %g2
0308     or      %g4, %g2, %g4
0309 
0310     /* Get log entry pointer for this cpu at this trap level. */
0311     BRANCH_IF_JALAPENO(g2,g3,50f)
0312     ldxa        [%g0] ASI_SAFARI_CONFIG, %g2
0313     srlx        %g2, 17, %g2
0314     ba,pt       %xcc, 60f
0315      and        %g2, 0x3ff, %g2
0316 
0317 50: ldxa        [%g0] ASI_JBUS_CONFIG, %g2
0318     srlx        %g2, 17, %g2
0319     and     %g2, 0x1f, %g2
0320 
0321 60: sllx        %g2, 9, %g2
0322     sethi       %hi(cheetah_error_log), %g3
0323     ldx     [%g3 + %lo(cheetah_error_log)], %g3
0324     brz,pn      %g3, 80f
0325      nop
0326 
0327     add     %g3, %g2, %g3
0328     sllx        %g1, 8, %g1
0329     add     %g3, %g1, %g1
0330 
0331     /* %g1 holds pointer to the top of the logging scoreboard */
0332     ldx     [%g1 + 0x0], %g7
0333     cmp     %g7, -1
0334     bne,pn      %xcc, 80f
0335      nop
0336 
0337     stx     %g4, [%g1 + 0x0]
0338     stx     %g5, [%g1 + 0x8]
0339     add     %g1, 0x10, %g1
0340 
0341     /* %g1 now points to D-cache logging area */
0342     set     0x3ff8, %g2 /* DC_addr mask     */
0343     and     %g5, %g2, %g2   /* DC_addr bits of AFAR */
0344     srlx        %g5, 12, %g3
0345     or      %g3, 1, %g3 /* PHYS tag + valid */
0346 
0347 10: ldxa        [%g2] ASI_DCACHE_TAG, %g7
0348     cmp     %g3, %g7    /* TAG match?       */
0349     bne,pt      %xcc, 13f
0350      nop
0351 
0352     /* Yep, what we want, capture state. */
0353     stx     %g2, [%g1 + 0x20]
0354     stx     %g7, [%g1 + 0x28]
0355 
0356     /* A membar Sync is required before and after utag access. */
0357     membar      #Sync
0358     ldxa        [%g2] ASI_DCACHE_UTAG, %g7
0359     membar      #Sync
0360     stx     %g7, [%g1 + 0x30]
0361     ldxa        [%g2] ASI_DCACHE_SNOOP_TAG, %g7
0362     stx     %g7, [%g1 + 0x38]
0363     clr     %g3
0364 
0365 12: ldxa        [%g2 + %g3] ASI_DCACHE_DATA, %g7
0366     stx     %g7, [%g1]
0367     add     %g3, (1 << 5), %g3
0368     cmp     %g3, (4 << 5)
0369     bl,pt       %xcc, 12b
0370      add        %g1, 0x8, %g1
0371 
0372     ba,pt       %xcc, 20f
0373      add        %g1, 0x20, %g1
0374 
0375 13: sethi       %hi(1 << 14), %g7
0376     add     %g2, %g7, %g2
0377     srlx        %g2, 14, %g7
0378     cmp     %g7, 4
0379     bl,pt       %xcc, 10b
0380      nop
0381 
0382     add     %g1, 0x40, %g1
0383 
0384     /* %g1 now points to I-cache logging area */
0385 20: set     0x1fe0, %g2 /* IC_addr mask     */
0386     and     %g5, %g2, %g2   /* IC_addr bits of AFAR */
0387     sllx        %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */
0388     srlx        %g5, (13 - 8), %g3 /* Make PTAG */
0389     andn        %g3, 0xff, %g3  /* Mask off undefined bits */
0390 
0391 21: ldxa        [%g2] ASI_IC_TAG, %g7
0392     andn        %g7, 0xff, %g7
0393     cmp     %g3, %g7
0394     bne,pt      %xcc, 23f
0395      nop
0396 
0397     /* Yep, what we want, capture state. */
0398     stx     %g2, [%g1 + 0x40]
0399     stx     %g7, [%g1 + 0x48]
0400     add     %g2, (1 << 3), %g2
0401     ldxa        [%g2] ASI_IC_TAG, %g7
0402     add     %g2, (1 << 3), %g2
0403     stx     %g7, [%g1 + 0x50]
0404     ldxa        [%g2] ASI_IC_TAG, %g7
0405     add     %g2, (1 << 3), %g2
0406     stx     %g7, [%g1 + 0x60]
0407     ldxa        [%g2] ASI_IC_TAG, %g7
0408     stx     %g7, [%g1 + 0x68]
0409     sub     %g2, (3 << 3), %g2
0410     ldxa        [%g2] ASI_IC_STAG, %g7
0411     stx     %g7, [%g1 + 0x58]
0412     clr     %g3
0413     srlx        %g2, 2, %g2
0414 
0415 22: ldxa        [%g2 + %g3] ASI_IC_INSTR, %g7
0416     stx     %g7, [%g1]
0417     add     %g3, (1 << 3), %g3
0418     cmp     %g3, (8 << 3)
0419     bl,pt       %xcc, 22b
0420      add        %g1, 0x8, %g1
0421 
0422     ba,pt       %xcc, 30f
0423      add        %g1, 0x30, %g1
0424 
0425 23: sethi       %hi(1 << 14), %g7
0426     add     %g2, %g7, %g2
0427     srlx        %g2, 14, %g7
0428     cmp     %g7, 4
0429     bl,pt       %xcc, 21b
0430      nop
0431 
0432     add     %g1, 0x70, %g1
0433 
0434     /* %g1 now points to E-cache logging area */
0435 30: andn        %g5, (32 - 1), %g2
0436     stx     %g2, [%g1 + 0x20]
0437     ldxa        [%g2] ASI_EC_TAG_DATA, %g7
0438     stx     %g7, [%g1 + 0x28]
0439     ldxa        [%g2] ASI_EC_R, %g0
0440     clr     %g3
0441 
0442 31: ldxa        [%g3] ASI_EC_DATA, %g7
0443     stx     %g7, [%g1 + %g3]
0444     add     %g3, 0x8, %g3
0445     cmp     %g3, 0x20
0446 
0447     bl,pt       %xcc, 31b
0448      nop
0449 80:
0450     rdpr        %tt, %g2
0451     cmp     %g2, 0x70
0452     be      c_fast_ecc
0453      cmp        %g2, 0x63
0454     be      c_cee
0455      nop
0456     ba,a,pt     %xcc, c_deferred
0457     .size       __cheetah_log_error,.-__cheetah_log_error
0458 
0459     /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
0460      * in the trap table.  That code has done a memory barrier
0461      * and has disabled both the I-cache and D-cache in the DCU
0462      * control register.  The I-cache is disabled so that we may
0463      * capture the corrupted cache line, and the D-cache is disabled
0464      * because corrupt data may have been placed there and we don't
0465      * want to reference it.
0466      *
0467      * %g1 is one if this trap occurred at %tl >= 1.
0468      *
0469      * Next, we turn off error reporting so that we don't recurse.
0470      */
0471     .globl      cheetah_fast_ecc
0472     .type       cheetah_fast_ecc,#function
0473 cheetah_fast_ecc:
0474     ldxa        [%g0] ASI_ESTATE_ERROR_EN, %g2
0475     andn        %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
0476     stxa        %g2, [%g0] ASI_ESTATE_ERROR_EN
0477     membar      #Sync
0478 
0479     /* Fetch and clear AFSR/AFAR */
0480     ldxa        [%g0] ASI_AFSR, %g4
0481     ldxa        [%g0] ASI_AFAR, %g5
0482     stxa        %g4, [%g0] ASI_AFSR
0483     membar      #Sync
0484 
0485     ba,pt       %xcc, __cheetah_log_error
0486      nop
0487     .size       cheetah_fast_ecc,.-cheetah_fast_ecc
0488 
0489     .type       c_fast_ecc,#function
0490 c_fast_ecc:
0491     rdpr        %pil, %g2
0492     wrpr        %g0, PIL_NORMAL_MAX, %pil
0493     ba,pt       %xcc, etrap_irq
0494      rd     %pc, %g7
0495 #ifdef CONFIG_TRACE_IRQFLAGS
0496     call        trace_hardirqs_off
0497      nop
0498 #endif
0499     mov     %l4, %o1
0500     mov     %l5, %o2
0501     call        cheetah_fecc_handler
0502      add        %sp, PTREGS_OFF, %o0
0503     ba,a,pt     %xcc, rtrap_irq
0504     .size       c_fast_ecc,.-c_fast_ecc
0505 
0506     /* Our caller has disabled I-cache and performed membar Sync. */
0507     .globl      cheetah_cee
0508     .type       cheetah_cee,#function
0509 cheetah_cee:
0510     ldxa        [%g0] ASI_ESTATE_ERROR_EN, %g2
0511     andn        %g2, ESTATE_ERROR_CEEN, %g2
0512     stxa        %g2, [%g0] ASI_ESTATE_ERROR_EN
0513     membar      #Sync
0514 
0515     /* Fetch and clear AFSR/AFAR */
0516     ldxa        [%g0] ASI_AFSR, %g4
0517     ldxa        [%g0] ASI_AFAR, %g5
0518     stxa        %g4, [%g0] ASI_AFSR
0519     membar      #Sync
0520 
0521     ba,pt       %xcc, __cheetah_log_error
0522      nop
0523     .size       cheetah_cee,.-cheetah_cee
0524 
0525     .type       c_cee,#function
0526 c_cee:
0527     rdpr        %pil, %g2
0528     wrpr        %g0, PIL_NORMAL_MAX, %pil
0529     ba,pt       %xcc, etrap_irq
0530      rd     %pc, %g7
0531 #ifdef CONFIG_TRACE_IRQFLAGS
0532     call        trace_hardirqs_off
0533      nop
0534 #endif
0535     mov     %l4, %o1
0536     mov     %l5, %o2
0537     call        cheetah_cee_handler
0538      add        %sp, PTREGS_OFF, %o0
0539     ba,a,pt     %xcc, rtrap_irq
0540     .size       c_cee,.-c_cee
0541 
0542     /* Our caller has disabled I-cache+D-cache and performed membar Sync. */
0543     .globl      cheetah_deferred_trap
0544     .type       cheetah_deferred_trap,#function
0545 cheetah_deferred_trap:
0546     ldxa        [%g0] ASI_ESTATE_ERROR_EN, %g2
0547     andn        %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
0548     stxa        %g2, [%g0] ASI_ESTATE_ERROR_EN
0549     membar      #Sync
0550 
0551     /* Fetch and clear AFSR/AFAR */
0552     ldxa        [%g0] ASI_AFSR, %g4
0553     ldxa        [%g0] ASI_AFAR, %g5
0554     stxa        %g4, [%g0] ASI_AFSR
0555     membar      #Sync
0556 
0557     ba,pt       %xcc, __cheetah_log_error
0558      nop
0559     .size       cheetah_deferred_trap,.-cheetah_deferred_trap
0560 
0561     .type       c_deferred,#function
0562 c_deferred:
0563     rdpr        %pil, %g2
0564     wrpr        %g0, PIL_NORMAL_MAX, %pil
0565     ba,pt       %xcc, etrap_irq
0566      rd     %pc, %g7
0567 #ifdef CONFIG_TRACE_IRQFLAGS
0568     call        trace_hardirqs_off
0569      nop
0570 #endif
0571     mov     %l4, %o1
0572     mov     %l5, %o2
0573     call        cheetah_deferred_handler
0574      add        %sp, PTREGS_OFF, %o0
0575     ba,a,pt     %xcc, rtrap_irq
0576     .size       c_deferred,.-c_deferred
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