uapi/asm/perfctr.h

0001 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
0002 /*----------------------------------------
0003   PERFORMANCE INSTRUMENTATION
0004   Guillaume Thouvenin           08/10/98
0005   David S. Miller               10/06/98
0006   ---------------------------------------*/
0007 #ifndef PERF_COUNTER_API
0008 #define PERF_COUNTER_API
0009
0010 /* sys_perfctr() interface.  First arg is operation code
0011  * from enumeration below.  The meaning of further arguments
0012  * are determined by the operation code.
0013  *
0014  * NOTE: This system call is no longer provided, use the perf_events
0015  *       infrastructure.
0016  *
0017  * Pointers which are passed by the user are pointers to 64-bit
0018  * integers.
0019  *
0020  * Once enabled, performance counter state is retained until the
0021  * process either exits or performs an exec.  That is, performance
0022  * counters remain enabled for fork/clone children.
0023  */
0024 enum perfctr_opcode {
0025     /* Enable UltraSparc performance counters, ARG0 is pointer
0026      * to 64-bit accumulator for D0 counter in PIC, ARG1 is pointer
0027      * to 64-bit accumulator for D1 counter.  ARG2 is a pointer to
0028      * the initial PCR register value to use.
0029      */
0030     PERFCTR_ON,
0031
0032     /* Disable UltraSparc performance counters.  The PCR is written
0033      * with zero and the user counter accumulator pointers and
0034      * working PCR register value are forgotten.
0035      */
0036     PERFCTR_OFF,
0037
0038     /* Add current D0 and D1 PIC values into user pointers given
0039      * in PERFCTR_ON operation.  The PIC is cleared before returning.
0040      */
0041     PERFCTR_READ,
0042
0043     /* Clear the PIC register. */
0044     PERFCTR_CLRPIC,
0045
0046     /* Begin using a new PCR value, the pointer to which is passed
0047      * in ARG0.  The PIC is also cleared after the new PCR value is
0048      * written.
0049      */
0050     PERFCTR_SETPCR,
0051
0052     /* Store in pointer given in ARG0 the current PCR register value
0053      * being used.
0054      */
0055     PERFCTR_GETPCR
0056 };
0057
0058 #define  PRIV 0x00000001
0059 #define  SYS  0x00000002
0060 #define  USR  0x00000004
0061
0062 /* Pic.S0 Selection Bit Field Encoding, Ultra-I/II  */
0063 #define  CYCLE_CNT            0x00000000
0064 #define  INSTR_CNT            0x00000010
0065 #define  DISPATCH0_IC_MISS    0x00000020
0066 #define  DISPATCH0_STOREBUF   0x00000030
0067 #define  IC_REF               0x00000080
0068 #define  DC_RD                0x00000090
0069 #define  DC_WR                0x000000A0
0070 #define  LOAD_USE             0x000000B0
0071 #define  EC_REF               0x000000C0
0072 #define  EC_WRITE_HIT_RDO     0x000000D0
0073 #define  EC_SNOOP_INV         0x000000E0
0074 #define  EC_RD_HIT            0x000000F0
0075
0076 /* Pic.S0 Selection Bit Field Encoding, Ultra-III  */
0077 #define  US3_CYCLE_CNT          0x00000000
0078 #define  US3_INSTR_CNT          0x00000010
0079 #define  US3_DISPATCH0_IC_MISS  0x00000020
0080 #define  US3_DISPATCH0_BR_TGT   0x00000030
0081 #define  US3_DISPATCH0_2ND_BR   0x00000040
0082 #define  US3_RSTALL_STOREQ  0x00000050
0083 #define  US3_RSTALL_IU_USE  0x00000060
0084 #define  US3_IC_REF     0x00000080
0085 #define  US3_DC_RD      0x00000090
0086 #define  US3_DC_WR      0x000000a0
0087 #define  US3_EC_REF     0x000000c0
0088 #define  US3_EC_WR_HIT_RTO  0x000000d0
0089 #define  US3_EC_SNOOP_INV   0x000000e0
0090 #define  US3_EC_RD_MISS     0x000000f0
0091 #define  US3_PC_PORT0_RD    0x00000100
0092 #define  US3_SI_SNOOP       0x00000110
0093 #define  US3_SI_CIQ_FLOW    0x00000120
0094 #define  US3_SI_OWNED       0x00000130
0095 #define  US3_SW_COUNT_0     0x00000140
0096 #define  US3_IU_BR_MISS_TAKEN   0x00000150
0097 #define  US3_IU_BR_COUNT_TAKEN  0x00000160
0098 #define  US3_DISP_RS_MISPRED    0x00000170
0099 #define  US3_FA_PIPE_COMPL  0x00000180
0100 #define  US3_MC_READS_0     0x00000200
0101 #define  US3_MC_READS_1     0x00000210
0102 #define  US3_MC_READS_2     0x00000220
0103 #define  US3_MC_READS_3     0x00000230
0104 #define  US3_MC_STALLS_0    0x00000240
0105 #define  US3_MC_STALLS_2    0x00000250
0106
0107 /* Pic.S1 Selection Bit Field Encoding, Ultra-I/II  */
0108 #define  CYCLE_CNT_D1         0x00000000
0109 #define  INSTR_CNT_D1         0x00000800
0110 #define  DISPATCH0_IC_MISPRED 0x00001000
0111 #define  DISPATCH0_FP_USE     0x00001800
0112 #define  IC_HIT               0x00004000
0113 #define  DC_RD_HIT            0x00004800
0114 #define  DC_WR_HIT            0x00005000
0115 #define  LOAD_USE_RAW         0x00005800
0116 #define  EC_HIT               0x00006000
0117 #define  EC_WB                0x00006800
0118 #define  EC_SNOOP_CB          0x00007000
0119 #define  EC_IT_HIT            0x00007800
0120
0121 /* Pic.S1 Selection Bit Field Encoding, Ultra-III  */
0122 #define  US3_CYCLE_CNT_D1   0x00000000
0123 #define  US3_INSTR_CNT_D1   0x00000800
0124 #define  US3_DISPATCH0_MISPRED  0x00001000
0125 #define  US3_IC_MISS_CANCELLED  0x00001800
0126 #define  US3_RE_ENDIAN_MISS 0x00002000
0127 #define  US3_RE_FPU_BYPASS  0x00002800
0128 #define  US3_RE_DC_MISS     0x00003000
0129 #define  US3_RE_EC_MISS     0x00003800
0130 #define  US3_IC_MISS        0x00004000
0131 #define  US3_DC_RD_MISS     0x00004800
0132 #define  US3_DC_WR_MISS     0x00005000
0133 #define  US3_RSTALL_FP_USE  0x00005800
0134 #define  US3_EC_MISSES      0x00006000
0135 #define  US3_EC_WB      0x00006800
0136 #define  US3_EC_SNOOP_CB    0x00007000
0137 #define  US3_EC_IC_MISS     0x00007800
0138 #define  US3_RE_PC_MISS     0x00008000
0139 #define  US3_ITLB_MISS      0x00008800
0140 #define  US3_DTLB_MISS      0x00009000
0141 #define  US3_WC_MISS        0x00009800
0142 #define  US3_WC_SNOOP_CB    0x0000a000
0143 #define  US3_WC_SCRUBBED    0x0000a800
0144 #define  US3_WC_WB_WO_READ  0x0000b000
0145 #define  US3_PC_SOFT_HIT    0x0000c000
0146 #define  US3_PC_SNOOP_INV   0x0000c800
0147 #define  US3_PC_HARD_HIT    0x0000d000
0148 #define  US3_PC_PORT1_RD    0x0000d800
0149 #define  US3_SW_COUNT_1     0x0000e000
0150 #define  US3_IU_STAT_BR_MIS_UNTAKEN 0x0000e800
0151 #define  US3_IU_STAT_BR_COUNT_UNTAKEN   0x0000f000
0152 #define  US3_PC_MS_MISSES   0x0000f800
0153 #define  US3_MC_WRITES_0    0x00010800
0154 #define  US3_MC_WRITES_1    0x00011000
0155 #define  US3_MC_WRITES_2    0x00011800
0156 #define  US3_MC_WRITES_3    0x00012000
0157 #define  US3_MC_STALLS_1    0x00012800
0158 #define  US3_MC_STALLS_3    0x00013000
0159 #define  US3_RE_RAW_MISS    0x00013800
0160 #define  US3_FM_PIPE_COMPLETION 0x00014000
0161
0162 struct vcounter_struct {
0163   unsigned long long vcnt0;
0164   unsigned long long vcnt1;
0165 };
0166
0167 #endif /* !(PERF_COUNTER_API) */