include/asm/winmacro.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * winmacro.h: Window loading-unloading macros.
0004  *
0005  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
0006  */
0007
0008 #ifndef _SPARC_WINMACRO_H
0009 #define _SPARC_WINMACRO_H
0010
0011 #include <asm/ptrace.h>
0012
0013 /* Store the register window onto the 8-byte aligned area starting
0014  * at %reg.  It might be %sp, it might not, we don't care.
0015  */
0016 #define STORE_WINDOW(reg) \
0017     std %l0, [%reg + RW_L0]; \
0018     std %l2, [%reg + RW_L2]; \
0019     std %l4, [%reg + RW_L4]; \
0020     std %l6, [%reg + RW_L6]; \
0021     std %i0, [%reg + RW_I0]; \
0022     std %i2, [%reg + RW_I2]; \
0023     std %i4, [%reg + RW_I4]; \
0024     std %i6, [%reg + RW_I6];
0025
0026 /* Load a register window from the area beginning at %reg. */
0027 #define LOAD_WINDOW(reg) \
0028     ldd [%reg + RW_L0], %l0; \
0029     ldd [%reg + RW_L2], %l2; \
0030     ldd [%reg + RW_L4], %l4; \
0031     ldd [%reg + RW_L6], %l6; \
0032     ldd [%reg + RW_I0], %i0; \
0033     ldd [%reg + RW_I2], %i2; \
0034     ldd [%reg + RW_I4], %i4; \
0035     ldd [%reg + RW_I6], %i6;
0036
0037 /* Loading and storing struct pt_reg trap frames. */
0038 #define LOAD_PT_INS(base_reg) \
0039         ldd     [%base_reg + STACKFRAME_SZ + PT_I0], %i0; \
0040         ldd     [%base_reg + STACKFRAME_SZ + PT_I2], %i2; \
0041         ldd     [%base_reg + STACKFRAME_SZ + PT_I4], %i4; \
0042         ldd     [%base_reg + STACKFRAME_SZ + PT_I6], %i6;
0043
0044 #define LOAD_PT_GLOBALS(base_reg) \
0045         ld      [%base_reg + STACKFRAME_SZ + PT_G1], %g1; \
0046         ldd     [%base_reg + STACKFRAME_SZ + PT_G2], %g2; \
0047         ldd     [%base_reg + STACKFRAME_SZ + PT_G4], %g4; \
0048         ldd     [%base_reg + STACKFRAME_SZ + PT_G6], %g6;
0049
0050 #define LOAD_PT_YREG(base_reg, scratch) \
0051         ld      [%base_reg + STACKFRAME_SZ + PT_Y], %scratch; \
0052         wr      %scratch, 0x0, %y;
0053
0054 #define LOAD_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
0055         ld      [%base_reg + STACKFRAME_SZ + PT_PSR], %pt_psr; \
0056         ld      [%base_reg + STACKFRAME_SZ + PT_PC], %pt_pc; \
0057         ld      [%base_reg + STACKFRAME_SZ + PT_NPC], %pt_npc;
0058
0059 #define LOAD_PT_ALL(base_reg, pt_psr, pt_pc, pt_npc, scratch) \
0060         LOAD_PT_YREG(base_reg, scratch) \
0061         LOAD_PT_INS(base_reg) \
0062         LOAD_PT_GLOBALS(base_reg) \
0063         LOAD_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc)
0064
0065 #define STORE_PT_INS(base_reg) \
0066         std     %i0, [%base_reg + STACKFRAME_SZ + PT_I0]; \
0067         std     %i2, [%base_reg + STACKFRAME_SZ + PT_I2]; \
0068         std     %i4, [%base_reg + STACKFRAME_SZ + PT_I4]; \
0069         std     %i6, [%base_reg + STACKFRAME_SZ + PT_I6];
0070
0071 #define STORE_PT_GLOBALS(base_reg) \
0072         st      %g1, [%base_reg + STACKFRAME_SZ + PT_G1]; \
0073         std     %g2, [%base_reg + STACKFRAME_SZ + PT_G2]; \
0074         std     %g4, [%base_reg + STACKFRAME_SZ + PT_G4]; \
0075         std     %g6, [%base_reg + STACKFRAME_SZ + PT_G6];
0076
0077 #define STORE_PT_YREG(base_reg, scratch) \
0078         rd      %y, %scratch; \
0079         st      %scratch, [%base_reg + STACKFRAME_SZ + PT_Y];
0080
0081 #define STORE_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
0082         st      %pt_psr, [%base_reg + STACKFRAME_SZ + PT_PSR]; \
0083         st      %pt_pc,  [%base_reg + STACKFRAME_SZ + PT_PC]; \
0084         st      %pt_npc, [%base_reg + STACKFRAME_SZ + PT_NPC];
0085
0086 #define STORE_PT_ALL(base_reg, reg_psr, reg_pc, reg_npc, g_scratch) \
0087         STORE_PT_PRIV(base_reg, reg_psr, reg_pc, reg_npc) \
0088         STORE_PT_GLOBALS(base_reg) \
0089         STORE_PT_YREG(base_reg, g_scratch) \
0090         STORE_PT_INS(base_reg)
0091
0092 #define SAVE_BOLIXED_USER_STACK(cur_reg, scratch) \
0093         ld       [%cur_reg + TI_W_SAVED], %scratch; \
0094         sll      %scratch, 2, %scratch; \
0095         add      %scratch, %cur_reg, %scratch; \
0096         st       %sp, [%scratch + TI_RWIN_SPTRS]; \
0097         sub      %scratch, %cur_reg, %scratch; \
0098         sll      %scratch, 4, %scratch; \
0099         add      %scratch, %cur_reg, %scratch; \
0100         STORE_WINDOW(scratch + TI_REG_WINDOW); \
0101         sub      %scratch, %cur_reg, %scratch; \
0102         srl      %scratch, 6, %scratch; \
0103         add      %scratch, 1, %scratch; \
0104         st       %scratch, [%cur_reg + TI_W_SAVED];
0105
0106 #ifdef CONFIG_SMP
0107 #define LOAD_CURRENT(dest_reg, idreg)           \
0108 661:    rd  %tbr, %idreg;               \
0109     srl %idreg, 10, %idreg;         \
0110     and %idreg, 0xc, %idreg;            \
0111     .section    .cpuid_patch, "ax";     \
0112     /* Instruction location. */         \
0113     .word       661b;               \
0114     /* SUN4D implementation. */         \
0115     lda  [%g0] ASI_M_VIKING_TMP1, %idreg;   \
0116     sll  %idreg, 2, %idreg;         \
0117     nop;                        \
0118     /* LEON implementation. */          \
0119     rd  %asr17, %idreg;             \
0120     srl %idreg, 0x1c, %idreg;           \
0121     sll %idreg, 0x02, %idreg;           \
0122     .previous;                  \
0123     sethi    %hi(current_set), %dest_reg;       \
0124     or       %dest_reg, %lo(current_set), %dest_reg;\
0125     ld       [%idreg + %dest_reg], %dest_reg;
0126 #else
0127 #define LOAD_CURRENT(dest_reg, idreg) \
0128         sethi    %hi(current_set), %idreg; \
0129         ld       [%idreg + %lo(current_set)], %dest_reg;
0130 #endif
0131
0132 #endif /* !(_SPARC_WINMACRO_H) */