0001
0002 #ifndef _SPARC64_VISASM_H
0003 #define _SPARC64_VISASM_H
0004
0005
0006
0007
0008
0009
0010 #include <asm/pstate.h>
0011 #include <asm/ptrace.h>
0012
0013
0014
0015 #define VISEntry \
0016 rd %fprs, %o5; \
0017 andcc %o5, (FPRS_FEF|FPRS_DU), %g0; \
0018 be,pt %icc, 297f; \
0019 sethi %hi(297f), %g7; \
0020 sethi %hi(VISenter), %g1; \
0021 jmpl %g1 + %lo(VISenter), %g0; \
0022 or %g7, %lo(297f), %g7; \
0023 297: wr %g0, FPRS_FEF, %fprs; \
0024
0025 #define VISExit \
0026 wr %g0, 0, %fprs;
0027
0028
0029
0030
0031 #define VISEntryHalf \
0032 VISEntry
0033
0034 #define VISExitHalf \
0035 VISExit
0036
0037 #define VISEntryHalfFast(fail_label) \
0038 rd %fprs, %o5; \
0039 andcc %o5, FPRS_FEF, %g0; \
0040 be,pt %icc, 297f; \
0041 nop; \
0042 ba,a,pt %xcc, fail_label; \
0043 297: wr %o5, FPRS_FEF, %fprs;
0044
0045 #define VISExitHalfFast \
0046 wr %o5, 0, %fprs;
0047
0048 #ifndef __ASSEMBLY__
0049 static inline void save_and_clear_fpu(void) {
0050 __asm__ __volatile__ (
0051 " rd %%fprs, %%o5\n"
0052 " andcc %%o5, %0, %%g0\n"
0053 " be,pt %%icc, 299f\n"
0054 " sethi %%hi(298f), %%g7\n"
0055 " sethi %%hi(VISenter), %%g1\n"
0056 " jmpl %%g1 + %%lo(VISenter), %%g0\n"
0057 " or %%g7, %%lo(298f), %%g7\n"
0058 " 298: wr %%g0, 0, %%fprs\n"
0059 " 299:\n"
0060 " " : : "i" (FPRS_FEF|FPRS_DU) :
0061 "o5", "g1", "g2", "g3", "g7", "cc");
0062 }
0063
0064 int vis_emul(struct pt_regs *, unsigned int);
0065 #endif
0066
0067 #endif