include/asm/viking.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * viking.h:  Defines specific to the GNU/Viking MBUS module.
0004  *            This is SRMMU stuff.
0005  *
0006  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
0007  */
0008 #ifndef _SPARC_VIKING_H
0009 #define _SPARC_VIKING_H
0010
0011 #include <asm/asi.h>
0012 #include <asm/mxcc.h>
0013 #include <asm/pgtable.h>
0014 #include <asm/pgtsrmmu.h>
0015
0016 /* Bits in the SRMMU control register for GNU/Viking modules.
0017  *
0018  * -----------------------------------------------------------
0019  * |impl-vers| RSV |TC|AC|SP|BM|PC|MBM|SB|IC|DC|PSO|RSV|NF|ME|
0020  * -----------------------------------------------------------
0021  *  31     24 23-17 16 15 14 13 12 11  10  9  8  7  6-2  1  0
0022  *
0023  * TC: Tablewalk Cacheable -- 0 = Twalks are not cacheable in E-cache
0024  *                            1 = Twalks are cacheable in E-cache
0025  *
0026  * GNU/Viking will only cache tablewalks in the E-cache (mxcc) if present
0027  * and never caches them internally (or so states the docs).  Therefore
0028  * for machines lacking an E-cache (ie. in MBUS mode) this bit must
0029  * remain cleared.
0030  *
0031  * AC: Alternate Cacheable -- 0 = Passthru physical accesses not cacheable
0032  *                            1 = Passthru physical accesses cacheable
0033  *
0034  * This indicates whether accesses are cacheable when no cachable bit
0035  * is present in the pte when the processor is in boot-mode or the
0036  * access does not need pte's for translation (ie. pass-thru ASI's).
0037  * "Cachable" is only referring to E-cache (if present) and not the
0038  * on chip split I/D caches of the GNU/Viking.
0039  *
0040  * SP: SnooP Enable -- 0 = bus snooping off, 1 = bus snooping on
0041  *
0042  * This enables snooping on the GNU/Viking bus.  This must be on
0043  * for the hardware cache consistency mechanisms of the GNU/Viking
0044  * to work at all.  On non-mxcc GNU/Viking modules the split I/D
0045  * caches will snoop regardless of whether they are enabled, this
0046  * takes care of the case where the I or D or both caches are turned
0047  * off yet still contain valid data.  Note also that this bit does
0048  * not affect GNU/Viking store-buffer snoops, those happen if the
0049  * store-buffer is enabled no matter what.
0050  *
0051  * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
0052  *
0053  * This indicates whether the GNU/Viking is in boot-mode or not,
0054  * if it is then all instruction fetch physical addresses are
0055  * computed as 0xff0000000 + low 28 bits of requested address.
0056  * GNU/Viking boot-mode does not affect data accesses.  Also,
0057  * in boot mode instruction accesses bypass the split on chip I/D
0058  * caches, they may be cached by the GNU/MXCC if present and enabled.
0059  *
0060  * MBM: MBus Mode -- 0 = not in MBus mode, 1 = in MBus mode
0061  *
0062  * This indicated the GNU/Viking configuration present.  If in
0063  * MBUS mode, the GNU/Viking lacks a GNU/MXCC E-cache.  If it is
0064  * not then the GNU/Viking is on a module VBUS connected directly
0065  * to a GNU/MXCC cache controller.  The GNU/MXCC can be thus connected
0066  * to either an GNU/MBUS (sun4m) or the packet-switched GNU/XBus (sun4d).
0067  *
0068  * SB: StoreBuffer enable -- 0 = store buffer off, 1 = store buffer on
0069  *
0070  * The GNU/Viking store buffer allows the chip to continue execution
0071  * after a store even if the data cannot be placed in one of the
0072  * caches during that cycle.  If disabled, all stores operations
0073  * occur synchronously.
0074  *
0075  * IC: Instruction Cache -- 0 = off, 1 = on
0076  * DC: Data Cache -- 0 = off, 1 = 0n
0077  *
0078  * These bits enable the on-cpu GNU/Viking split I/D caches.  Note,
0079  * as mentioned above, these caches will snoop the bus in GNU/MBUS
0080  * configurations even when disabled to avoid data corruption.
0081  *
0082  * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
0083  * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
0084  *
0085  */
0086
0087 #define VIKING_MMUENABLE    0x00000001
0088 #define VIKING_NOFAULT      0x00000002
0089 #define VIKING_PSO          0x00000080
0090 #define VIKING_DCENABLE     0x00000100   /* Enable data cache */
0091 #define VIKING_ICENABLE     0x00000200   /* Enable instruction cache */
0092 #define VIKING_SBENABLE     0x00000400   /* Enable store buffer */
0093 #define VIKING_MMODE        0x00000800   /* MBUS mode */
0094 #define VIKING_PCENABLE     0x00001000   /* Enable parity checking */
0095 #define VIKING_BMODE        0x00002000
0096 #define VIKING_SPENABLE     0x00004000   /* Enable bus cache snooping */
0097 #define VIKING_ACENABLE     0x00008000   /* Enable alternate caching */
0098 #define VIKING_TCENABLE     0x00010000   /* Enable table-walks to be cached */
0099 #define VIKING_DPENABLE     0x00040000   /* Enable the data prefetcher */
0100
0101 /*
0102  * GNU/Viking Breakpoint Action Register fields.
0103  */
0104 #define VIKING_ACTION_MIX   0x00001000   /* Enable multiple instructions */
0105
0106 /*
0107  * GNU/Viking Cache Tags.
0108  */
0109 #define VIKING_PTAG_VALID   0x01000000   /* Cache block is valid */
0110 #define VIKING_PTAG_DIRTY   0x00010000   /* Block has been modified */
0111 #define VIKING_PTAG_SHARED  0x00000100   /* Shared with some other cache */
0112
0113 #ifndef __ASSEMBLY__
0114
0115 static inline void viking_flush_icache(void)
0116 {
0117     __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
0118                  : /* no outputs */
0119                  : "i" (ASI_M_IC_FLCLEAR)
0120                  : "memory");
0121 }
0122
0123 static inline void viking_flush_dcache(void)
0124 {
0125     __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
0126                  : /* no outputs */
0127                  : "i" (ASI_M_DC_FLCLEAR)
0128                  : "memory");
0129 }
0130
0131 static inline void viking_unlock_icache(void)
0132 {
0133     __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
0134                  : /* no outputs */
0135                  : "r" (0x80000000), "i" (ASI_M_IC_FLCLEAR)
0136                  : "memory");
0137 }
0138
0139 static inline void viking_unlock_dcache(void)
0140 {
0141     __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
0142                  : /* no outputs */
0143                  : "r" (0x80000000), "i" (ASI_M_DC_FLCLEAR)
0144                  : "memory");
0145 }
0146
0147 static inline void viking_set_bpreg(unsigned long regval)
0148 {
0149     __asm__ __volatile__("sta %0, [%%g0] %1\n\t"
0150                  : /* no outputs */
0151                  : "r" (regval), "i" (ASI_M_ACTION)
0152                  : "memory");
0153 }
0154
0155 static inline unsigned long viking_get_bpreg(void)
0156 {
0157     unsigned long regval;
0158
0159     __asm__ __volatile__("lda [%%g0] %1, %0\n\t"
0160                  : "=r" (regval)
0161                  : "i" (ASI_M_ACTION));
0162     return regval;
0163 }
0164
0165 static inline void viking_get_dcache_ptag(int set, int block,
0166                           unsigned long *data)
0167 {
0168     unsigned long ptag = ((set & 0x7f) << 5) | ((block & 0x3) << 26) |
0169                  0x80000000;
0170     unsigned long info, page;
0171
0172     __asm__ __volatile__ ("ldda [%2] %3, %%g2\n\t"
0173                   "or %%g0, %%g2, %0\n\t"
0174                   "or %%g0, %%g3, %1\n\t"
0175                   : "=r" (info), "=r" (page)
0176                   : "r" (ptag), "i" (ASI_M_DATAC_TAG)
0177                   : "g2", "g3");
0178     data[0] = info;
0179     data[1] = page;
0180 }
0181
0182 static inline void viking_mxcc_turn_off_parity(unsigned long *mregp,
0183                            unsigned long *mxcc_cregp)
0184 {
0185     unsigned long mreg = *mregp;
0186     unsigned long mxcc_creg = *mxcc_cregp;
0187
0188     mreg &= ~(VIKING_PCENABLE);
0189     mxcc_creg &= ~(MXCC_CTL_PARE);
0190
0191     __asm__ __volatile__ ("set 1f, %%g2\n\t"
0192                   "andcc %%g2, 4, %%g0\n\t"
0193                   "bne 2f\n\t"
0194                   " nop\n"
0195                   "1:\n\t"
0196                   "sta %0, [%%g0] %3\n\t"
0197                   "sta %1, [%2] %4\n\t"
0198                   "b 1f\n\t"
0199                   " nop\n\t"
0200                   "nop\n"
0201                   "2:\n\t"
0202                   "sta %0, [%%g0] %3\n\t"
0203                   "sta %1, [%2] %4\n"
0204                   "1:\n\t"
0205                   : /* no output */
0206                   : "r" (mreg), "r" (mxcc_creg),
0207                     "r" (MXCC_CREG), "i" (ASI_M_MMUREGS),
0208                     "i" (ASI_M_MXCC)
0209                   : "g2", "memory", "cc");
0210     *mregp = mreg;
0211     *mxcc_cregp = mxcc_creg;
0212 }
0213
0214 static inline unsigned long viking_hwprobe(unsigned long vaddr)
0215 {
0216     unsigned long val;
0217
0218     vaddr &= PAGE_MASK;
0219     /* Probe all MMU entries. */
0220     __asm__ __volatile__("lda [%1] %2, %0\n\t"
0221                  : "=r" (val)
0222                  : "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
0223     if (!val)
0224         return 0;
0225
0226     /* Probe region. */
0227     __asm__ __volatile__("lda [%1] %2, %0\n\t"
0228                  : "=r" (val)
0229                  : "r" (vaddr | 0x200), "i" (ASI_M_FLUSH_PROBE));
0230     if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
0231         vaddr &= ~PGDIR_MASK;
0232         vaddr >>= PAGE_SHIFT;
0233         return val | (vaddr << 8);
0234     }
0235
0236     /* Probe segment. */
0237     __asm__ __volatile__("lda [%1] %2, %0\n\t"
0238                  : "=r" (val)
0239                  : "r" (vaddr | 0x100), "i" (ASI_M_FLUSH_PROBE));
0240     if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
0241         vaddr &= ~PMD_MASK;
0242         vaddr >>= PAGE_SHIFT;
0243         return val | (vaddr << 8);
0244     }
0245
0246     /* Probe page. */
0247     __asm__ __volatile__("lda [%1] %2, %0\n\t"
0248                  : "=r" (val)
0249                  : "r" (vaddr), "i" (ASI_M_FLUSH_PROBE));
0250     return val;
0251 }
0252
0253 #endif /* !__ASSEMBLY__ */
0254
0255 #endif /* !(_SPARC_VIKING_H) */