include/asm/turbosparc.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * turbosparc.h:  Defines specific to the TurboSparc module.
0004  *            This is SRMMU stuff.
0005  *
0006  * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
0007  */
0008 #ifndef _SPARC_TURBOSPARC_H
0009 #define _SPARC_TURBOSPARC_H
0010
0011 #include <asm/asi.h>
0012 #include <asm/pgtsrmmu.h>
0013
0014 /* Bits in the SRMMU control register for TurboSparc modules.
0015  *
0016  * -------------------------------------------------------------------
0017  * |impl-vers| RSV| PMC |PE|PC| RSV |BM| RFR |IC|DC|PSO|RSV|ICS|NF|ME|
0018  * -------------------------------------------------------------------
0019  *  31    24 23-21 20-19 18 17 16-15 14 13-10  9  8  7  6-3   2  1  0
0020  *
0021  * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
0022  *
0023  * This indicates whether the TurboSparc is in boot-mode or not.
0024  *
0025  * IC: Instruction Cache -- 0 = off, 1 = on
0026  * DC: Data Cache -- 0 = off, 1 = 0n
0027  *
0028  * These bits enable the on-cpu TurboSparc split I/D caches.
0029  *
0030  * ICS: ICache Snooping -- 0 = disable, 1 = enable snooping of icache
0031  * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
0032  * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
0033  *
0034  */
0035
0036 #define TURBOSPARC_MMUENABLE    0x00000001
0037 #define TURBOSPARC_NOFAULT      0x00000002
0038 #define TURBOSPARC_ICSNOOP  0x00000004
0039 #define TURBOSPARC_PSO          0x00000080
0040 #define TURBOSPARC_DCENABLE     0x00000100   /* Enable data cache */
0041 #define TURBOSPARC_ICENABLE     0x00000200   /* Enable instruction cache */
0042 #define TURBOSPARC_BMODE        0x00004000
0043 #define TURBOSPARC_PARITYODD    0x00020000   /* Parity odd, if enabled */
0044 #define TURBOSPARC_PCENABLE 0x00040000   /* Enable parity checking */
0045
0046 /* Bits in the CPU configuration register for TurboSparc modules.
0047  *
0048  * -------------------------------------------------------
0049  * |IOClk|SNP|AXClk| RAH |  WS |  RSV  |SBC|WT|uS2|SE|SCC|
0050  * -------------------------------------------------------
0051  *    31   30 29-28 27-26 25-23   22-8  7-6  5  4   3 2-0
0052  *
0053  */
0054
0055 #define TURBOSPARC_SCENABLE 0x00000008   /* Secondary cache enable */
0056 #define TURBOSPARC_uS2      0x00000010   /* Swift compatibility mode */
0057 #define TURBOSPARC_WTENABLE 0x00000020   /* Write thru for dcache */
0058 #define TURBOSPARC_SNENABLE 0x40000000   /* DVMA snoop enable */
0059
0060 #ifndef __ASSEMBLY__
0061
0062 /* Bits [13:5] select one of 512 instruction cache tags */
0063 static inline void turbosparc_inv_insn_tag(unsigned long addr)
0064 {
0065         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
0066                  : /* no outputs */
0067                  : "r" (addr), "i" (ASI_M_TXTC_TAG)
0068                  : "memory");
0069 }
0070
0071 /* Bits [13:5] select one of 512 data cache tags */
0072 static inline void turbosparc_inv_data_tag(unsigned long addr)
0073 {
0074         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
0075                  : /* no outputs */
0076                  : "r" (addr), "i" (ASI_M_DATAC_TAG)
0077                  : "memory");
0078 }
0079
0080 static inline void turbosparc_flush_icache(void)
0081 {
0082     unsigned long addr;
0083
0084         for (addr = 0; addr < 0x4000; addr += 0x20)
0085                 turbosparc_inv_insn_tag(addr);
0086 }
0087
0088 static inline void turbosparc_flush_dcache(void)
0089 {
0090     unsigned long addr;
0091
0092         for (addr = 0; addr < 0x4000; addr += 0x20)
0093                 turbosparc_inv_data_tag(addr);
0094 }
0095
0096 static inline void turbosparc_idflash_clear(void)
0097 {
0098     unsigned long addr;
0099
0100         for (addr = 0; addr < 0x4000; addr += 0x20) {
0101                 turbosparc_inv_insn_tag(addr);
0102                 turbosparc_inv_data_tag(addr);
0103     }
0104 }
0105
0106 static inline void turbosparc_set_ccreg(unsigned long regval)
0107 {
0108     __asm__ __volatile__("sta %0, [%1] %2\n\t"
0109                  : /* no outputs */
0110                  : "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS)
0111                  : "memory");
0112 }
0113
0114 static inline unsigned long turbosparc_get_ccreg(void)
0115 {
0116     unsigned long regval;
0117
0118     __asm__ __volatile__("lda [%1] %2, %0\n\t"
0119                  : "=r" (regval)
0120                  : "r" (0x600), "i" (ASI_M_MMUREGS));
0121     return regval;
0122 }
0123
0124 #endif /* !__ASSEMBLY__ */
0125
0126 #endif /* !(_SPARC_TURBOSPARC_H) */