include/asm/trap_block.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _SPARC_TRAP_BLOCK_H
0003 #define _SPARC_TRAP_BLOCK_H
0004
0005 #include <linux/threads.h>
0006
0007 #include <asm/hypervisor.h>
0008 #include <asm/asi.h>
0009
0010 #ifndef __ASSEMBLY__
0011
0012 /* Trap handling code needs to get at a few critical values upon
0013  * trap entry and to process TSB misses.  These cannot be in the
0014  * per_cpu() area as we really need to lock them into the TLB and
0015  * thus make them part of the main kernel image.  As a result we
0016  * try to make this as small as possible.
0017  *
0018  * This is padded out and aligned to 64-bytes to avoid false sharing
0019  * on SMP.
0020  */
0021
0022 /* If you modify the size of this structure, please update
0023  * TRAP_BLOCK_SZ_SHIFT below.
0024  */
0025 struct thread_info;
0026 struct trap_per_cpu {
0027 /* D-cache line 1: Basic thread information, cpu and device mondo queues */
0028     struct thread_info  *thread;
0029     unsigned long       pgd_paddr;
0030     unsigned long       cpu_mondo_pa;
0031     unsigned long       dev_mondo_pa;
0032
0033 /* D-cache line 2: Error Mondo Queue and kernel buffer pointers */
0034     unsigned long       resum_mondo_pa;
0035     unsigned long       resum_kernel_buf_pa;
0036     unsigned long       nonresum_mondo_pa;
0037     unsigned long       nonresum_kernel_buf_pa;
0038
0039 /* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */
0040     struct hv_fault_status  fault_info;
0041
0042 /* Dcache line 7: Physical addresses of CPU send mondo block and CPU list.  */
0043     unsigned long       cpu_mondo_block_pa;
0044     unsigned long       cpu_list_pa;
0045     unsigned long       tsb_huge;
0046     unsigned long       tsb_huge_temp;
0047
0048 /* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size.  */
0049     unsigned long       irq_worklist_pa;
0050     unsigned int        cpu_mondo_qmask;
0051     unsigned int        dev_mondo_qmask;
0052     unsigned int        resum_qmask;
0053     unsigned int        nonresum_qmask;
0054     unsigned long       __per_cpu_base;
0055 } __attribute__((aligned(64)));
0056 extern struct trap_per_cpu trap_block[NR_CPUS];
0057 void init_cur_cpu_trap(struct thread_info *);
0058 void setup_tba(void);
0059 extern int ncpus_probed;
0060 extern u64 cpu_mondo_counter[NR_CPUS];
0061
0062 unsigned long real_hard_smp_processor_id(void);
0063
0064 struct cpuid_patch_entry {
0065     unsigned int    addr;
0066     unsigned int    cheetah_safari[4];
0067     unsigned int    cheetah_jbus[4];
0068     unsigned int    starfire[4];
0069     unsigned int    sun4v[4];
0070 };
0071 extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
0072
0073 struct sun4v_1insn_patch_entry {
0074     unsigned int    addr;
0075     unsigned int    insn;
0076 };
0077 extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
0078     __sun4v_1insn_patch_end;
0079 extern struct sun4v_1insn_patch_entry __fast_win_ctrl_1insn_patch,
0080     __fast_win_ctrl_1insn_patch_end;
0081 extern struct sun4v_1insn_patch_entry __sun_m7_1insn_patch,
0082     __sun_m7_1insn_patch_end;
0083
0084 struct sun4v_2insn_patch_entry {
0085     unsigned int    addr;
0086     unsigned int    insns[2];
0087 };
0088 extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
0089     __sun4v_2insn_patch_end;
0090 extern struct sun4v_2insn_patch_entry __sun_m7_2insn_patch,
0091     __sun_m7_2insn_patch_end;
0092
0093
0094 #endif /* !(__ASSEMBLY__) */
0095
0096 #define TRAP_PER_CPU_THREAD     0x00
0097 #define TRAP_PER_CPU_PGD_PADDR      0x08
0098 #define TRAP_PER_CPU_CPU_MONDO_PA   0x10
0099 #define TRAP_PER_CPU_DEV_MONDO_PA   0x18
0100 #define TRAP_PER_CPU_RESUM_MONDO_PA 0x20
0101 #define TRAP_PER_CPU_RESUM_KBUF_PA  0x28
0102 #define TRAP_PER_CPU_NONRESUM_MONDO_PA  0x30
0103 #define TRAP_PER_CPU_NONRESUM_KBUF_PA   0x38
0104 #define TRAP_PER_CPU_FAULT_INFO     0x40
0105 #define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA 0xc0
0106 #define TRAP_PER_CPU_CPU_LIST_PA    0xc8
0107 #define TRAP_PER_CPU_TSB_HUGE       0xd0
0108 #define TRAP_PER_CPU_TSB_HUGE_TEMP  0xd8
0109 #define TRAP_PER_CPU_IRQ_WORKLIST_PA    0xe0
0110 #define TRAP_PER_CPU_CPU_MONDO_QMASK    0xe8
0111 #define TRAP_PER_CPU_DEV_MONDO_QMASK    0xec
0112 #define TRAP_PER_CPU_RESUM_QMASK    0xf0
0113 #define TRAP_PER_CPU_NONRESUM_QMASK 0xf4
0114 #define TRAP_PER_CPU_PER_CPU_BASE   0xf8
0115
0116 #define TRAP_BLOCK_SZ_SHIFT     8
0117
0118 #include <asm/scratchpad.h>
0119
0120 #define __GET_CPUID(REG)                \
0121     /* Spitfire implementation (default). */    \
0122 661:    ldxa        [%g0] ASI_UPA_CONFIG, REG;  \
0123     srlx        REG, 17, REG;           \
0124      and        REG, 0x1f, REG;         \
0125     nop;                        \
0126     .section    .cpuid_patch, "ax";     \
0127     /* Instruction location. */         \
0128     .word       661b;               \
0129     /* Cheetah Safari implementation. */        \
0130     ldxa        [%g0] ASI_SAFARI_CONFIG, REG;   \
0131     srlx        REG, 17, REG;           \
0132     and     REG, 0x3ff, REG;        \
0133     nop;                        \
0134     /* Cheetah JBUS implementation. */      \
0135     ldxa        [%g0] ASI_JBUS_CONFIG, REG; \
0136     srlx        REG, 17, REG;           \
0137     and     REG, 0x1f, REG;         \
0138     nop;                        \
0139     /* Starfire implementation. */          \
0140     sethi       %hi(0x1fff40000d0 >> 9), REG;   \
0141     sllx        REG, 9, REG;            \
0142     or      REG, 0xd0, REG;         \
0143     lduwa       [REG] ASI_PHYS_BYPASS_EC_E, REG;\
0144     /* sun4v implementation. */         \
0145     mov     SCRATCHPAD_CPUID, REG;      \
0146     ldxa        [REG] ASI_SCRATCHPAD, REG;  \
0147     nop;                        \
0148     nop;                        \
0149     .previous;
0150
0151 #ifdef CONFIG_SMP
0152
0153 #define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)     \
0154     __GET_CPUID(TMP)            \
0155     sethi   %hi(trap_block), DEST;      \
0156     sllx    TMP, TRAP_BLOCK_SZ_SHIFT, TMP;  \
0157     or  DEST, %lo(trap_block), DEST;    \
0158     add DEST, TMP, DEST;        \
0159
0160 /* Clobbers TMP, current address space PGD phys address into DEST.  */
0161 #define TRAP_LOAD_PGD_PHYS(DEST, TMP)       \
0162     TRAP_LOAD_TRAP_BLOCK(DEST, TMP)     \
0163     ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
0164
0165 /* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
0166 #define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP)    \
0167     TRAP_LOAD_TRAP_BLOCK(DEST, TMP)     \
0168     add DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
0169
0170 /* Clobbers TMP, loads DEST with current thread info pointer.  */
0171 #define TRAP_LOAD_THREAD_REG(DEST, TMP)     \
0172     TRAP_LOAD_TRAP_BLOCK(DEST, TMP)     \
0173     ldx [DEST + TRAP_PER_CPU_THREAD], DEST;
0174
0175 /* Given the current thread info pointer in THR, load the per-cpu
0176  * area base of the current processor into DEST.  REG1, REG2, and REG3 are
0177  * clobbered.
0178  *
0179  * You absolutely cannot use DEST as a temporary in this code.  The
0180  * reason is that traps can happen during execution, and return from
0181  * trap will load the fully resolved DEST per-cpu base.  This can corrupt
0182  * the calculations done by the macro mid-stream.
0183  */
0184 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)  \
0185     lduh    [THR + TI_CPU], REG1;           \
0186     sethi   %hi(trap_block), REG2;          \
0187     sllx    REG1, TRAP_BLOCK_SZ_SHIFT, REG1;    \
0188     or  REG2, %lo(trap_block), REG2;        \
0189     add REG2, REG1, REG2;           \
0190     ldx [REG2 + TRAP_PER_CPU_PER_CPU_BASE], DEST;
0191
0192 #else
0193
0194 #define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)     \
0195     sethi   %hi(trap_block), DEST;      \
0196     or  DEST, %lo(trap_block), DEST;    \
0197
0198 /* Uniprocessor versions, we know the cpuid is zero.  */
0199 #define TRAP_LOAD_PGD_PHYS(DEST, TMP)       \
0200     TRAP_LOAD_TRAP_BLOCK(DEST, TMP)     \
0201     ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
0202
0203 /* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
0204 #define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP)    \
0205     TRAP_LOAD_TRAP_BLOCK(DEST, TMP)     \
0206     add DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
0207
0208 #define TRAP_LOAD_THREAD_REG(DEST, TMP)     \
0209     TRAP_LOAD_TRAP_BLOCK(DEST, TMP)     \
0210     ldx [DEST + TRAP_PER_CPU_THREAD], DEST;
0211
0212 /* No per-cpu areas on uniprocessor, so no need to load DEST.  */
0213 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
0214
0215 #endif /* !(CONFIG_SMP) */
0216
0217 #endif /* _SPARC_TRAP_BLOCK_H */