include/asm/timer_32.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * timer.h:  Definitions for the timer chips on the Sparc.
0004  *
0005  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
0006  */
0007
0008
0009 #ifndef _SPARC_TIMER_H
0010 #define _SPARC_TIMER_H
0011
0012 #include <linux/clocksource.h>
0013 #include <linux/irqreturn.h>
0014
0015 #include <asm-generic/percpu.h>
0016
0017 #include <asm/cpu_type.h>  /* For SUN4M_NCPUS */
0018
0019 #define SBUS_CLOCK_RATE   2000000 /* 2MHz */
0020 #define TIMER_VALUE_SHIFT 9
0021 #define TIMER_VALUE_MASK  0x3fffff
0022 #define TIMER_LIMIT_BIT   (1 << 31)  /* Bit 31 in Counter-Timer register */
0023
0024 /* The counter timer register has the value offset by 9 bits.
0025  * From sun4m manual:
0026  * When a counter reaches the value in the corresponding limit register,
0027  * the Limit bit is set and the counter is set to 500 nS (i.e. 0x00000200).
0028  *
0029  * To compensate for this add one to the value.
0030  */
0031 static inline unsigned int timer_value(unsigned int value)
0032 {
0033     return (value + 1) << TIMER_VALUE_SHIFT;
0034 }
0035
0036 extern volatile u32 __iomem *master_l10_counter;
0037
0038 irqreturn_t notrace timer_interrupt(int dummy, void *dev_id);
0039
0040 #ifdef CONFIG_SMP
0041 DECLARE_PER_CPU(struct clock_event_device, sparc32_clockevent);
0042 void register_percpu_ce(int cpu);
0043 #endif
0044
0045 #endif /* !(_SPARC_TIMER_H) */