include/asm/switch_to_32.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __SPARC_SWITCH_TO_H
0003 #define __SPARC_SWITCH_TO_H
0004
0005 #include <asm/smp.h>
0006
0007 extern struct thread_info *current_set[NR_CPUS];
0008
0009 /*
0010  * Flush windows so that the VM switch which follows
0011  * would not pull the stack from under us.
0012  *
0013  * SWITCH_ENTER and SWITCH_DO_LAZY_FPU do not work yet (e.g. SMP does not work)
0014  * XXX WTF is the above comment? Found in late teen 2.4.x.
0015  */
0016 #ifdef CONFIG_SMP
0017 #define SWITCH_ENTER(prv) \
0018     do {            \
0019     if (test_tsk_thread_flag(prv, TIF_USEDFPU)) { \
0020         put_psr(get_psr() | PSR_EF); \
0021         fpsave(&(prv)->thread.float_regs[0], &(prv)->thread.fsr, \
0022                &(prv)->thread.fpqueue[0], &(prv)->thread.fpqdepth); \
0023         clear_tsk_thread_flag(prv, TIF_USEDFPU); \
0024         (prv)->thread.kregs->psr &= ~PSR_EF; \
0025     } \
0026     } while(0)
0027
0028 #define SWITCH_DO_LAZY_FPU(next)    /* */
0029 #else
0030 #define SWITCH_ENTER(prv)       /* */
0031 #define SWITCH_DO_LAZY_FPU(nxt) \
0032     do {            \
0033     if (last_task_used_math != (nxt))       \
0034         (nxt)->thread.kregs->psr&=~PSR_EF;  \
0035     } while(0)
0036 #endif
0037
0038 #define prepare_arch_switch(next) do { \
0039     __asm__ __volatile__( \
0040     ".globl\tflush_patch_switch\nflush_patch_switch:\n\t" \
0041     "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
0042     "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
0043     "save %sp, -0x40, %sp\n\t" \
0044     "restore; restore; restore; restore; restore; restore; restore"); \
0045 } while(0)
0046
0047     /* Much care has gone into this code, do not touch it.
0048      *
0049      * We need to loadup regs l0/l1 for the newly forked child
0050      * case because the trap return path relies on those registers
0051      * holding certain values, gcc is told that they are clobbered.
0052      * Gcc needs registers for 3 values in and 1 value out, so we
0053      * clobber every non-fixed-usage register besides l2/l3/o4/o5.  -DaveM
0054      *
0055      * Hey Dave, that do not touch sign is too much of an incentive
0056      * - Anton & Pete
0057      */
0058 #define switch_to(prev, next, last) do {                        \
0059     SWITCH_ENTER(prev);                             \
0060     SWITCH_DO_LAZY_FPU(next);                           \
0061     cpumask_set_cpu(smp_processor_id(), mm_cpumask(next->active_mm));       \
0062     __asm__ __volatile__(                               \
0063     "sethi  %%hi(here - 0x8), %%o7\n\t"                     \
0064     "mov    %%g6, %%g3\n\t"                             \
0065     "or %%o7, %%lo(here - 0x8), %%o7\n\t"                   \
0066     "rd %%psr, %%g4\n\t"                            \
0067     "std    %%sp, [%%g6 + %4]\n\t"                          \
0068     "rd %%wim, %%g5\n\t"                            \
0069     "wr %%g4, 0x20, %%psr\n\t"                          \
0070     "nop\n\t"                                   \
0071     "std    %%g4, [%%g6 + %3]\n\t"                          \
0072     "ldd    [%2 + %3], %%g4\n\t"                            \
0073     "mov    %2, %%g6\n\t"                               \
0074     ".globl patchme_store_new_current\n"                        \
0075 "patchme_store_new_current:\n\t"                            \
0076     "st %2, [%1]\n\t"                               \
0077     "wr %%g4, 0x20, %%psr\n\t"                          \
0078     "nop\n\t"                                   \
0079     "nop\n\t"                                   \
0080     "nop\n\t"   /* LEON needs all 3 nops: load to %sp depends on CWP. */        \
0081     "ldd    [%%g6 + %4], %%sp\n\t"                          \
0082     "wr %%g5, 0x0, %%wim\n\t"                           \
0083     "ldd    [%%sp + 0x00], %%l0\n\t"                        \
0084     "ldd    [%%sp + 0x38], %%i6\n\t"                        \
0085     "wr %%g4, 0x0, %%psr\n\t"                           \
0086     "nop\n\t"                                   \
0087     "nop\n\t"                                   \
0088     "jmpl   %%o7 + 0x8, %%g0\n\t"                           \
0089     " ld    [%%g3 + %5], %0\n\t"                            \
0090     "here:\n"                                   \
0091         : "=&r" (last)                                  \
0092         : "r" (&(current_set[hard_smp_processor_id()])),    \
0093       "r" (task_thread_info(next)),             \
0094       "i" (TI_KPSR),                    \
0095       "i" (TI_KSP),                     \
0096       "i" (TI_TASK)                     \
0097     :       "g1", "g2", "g3", "g4", "g5",       "g7",   \
0098       "l0", "l1",       "l3", "l4", "l5", "l6", "l7",   \
0099       "i0", "i1", "i2", "i3", "i4", "i5",           \
0100       "o0", "o1", "o2", "o3",                   "o7");  \
0101     } while(0)
0102
0103 void fpsave(unsigned long *fpregs, unsigned long *fsr,
0104         void *fpqueue, unsigned long *fpqdepth);
0105 void synchronize_user_stack(void);
0106
0107 #endif /* __SPARC_SWITCH_TO_H */