include/asm/sunbpp.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * include/asm/sunbpp.h
0004  */
0005
0006 #ifndef _ASM_SPARC_SUNBPP_H
0007 #define _ASM_SPARC_SUNBPP_H
0008
0009 struct bpp_regs {
0010   /* DMA registers */
0011   __volatile__ __u32 p_csr;     /* DMA Control/Status Register */
0012   __volatile__ __u32 p_addr;        /* Address Register */
0013   __volatile__ __u32 p_bcnt;        /* Byte Count Register */
0014   __volatile__ __u32 p_tst_csr;     /* Test Control/Status (DMA2 only) */
0015   /* Parallel Port registers */
0016   __volatile__ __u16 p_hcr;     /* Hardware Configuration Register */
0017   __volatile__ __u16 p_ocr;     /* Operation Configuration Register */
0018   __volatile__ __u8 p_dr;       /* Parallel Data Register */
0019   __volatile__ __u8 p_tcr;      /* Transfer Control Register */
0020   __volatile__ __u8 p_or;       /* Output Register */
0021   __volatile__ __u8 p_ir;       /* Input Register */
0022   __volatile__ __u16 p_icr;     /* Interrupt Control Register */
0023 };
0024
0025 /* P_HCR. Time is in increments of SBus clock. */
0026 #define P_HCR_TEST      0x8000      /* Allows buried counters to be read */
0027 #define P_HCR_DSW       0x7f00      /* Data strobe width (in ticks) */
0028 #define P_HCR_DDS       0x007f      /* Data setup before strobe (in ticks) */
0029
0030 /* P_OCR. */
0031 #define P_OCR_MEM_CLR   0x8000
0032 #define P_OCR_DATA_SRC  0x4000      /* )                  */
0033 #define P_OCR_DS_DSEL   0x2000      /* )  Bidirectional      */
0034 #define P_OCR_BUSY_DSEL 0x1000      /* )    selects            */
0035 #define P_OCR_ACK_DSEL  0x0800      /* )                  */
0036 #define P_OCR_EN_DIAG   0x0400
0037 #define P_OCR_BUSY_OP   0x0200      /* Busy operation */
0038 #define P_OCR_ACK_OP    0x0100      /* Ack operation */
0039 #define P_OCR_SRST      0x0080      /* Reset state machines. Not selfcleaning. */
0040 #define P_OCR_IDLE      0x0008      /* PP data transfer state machine is idle */
0041 #define P_OCR_V_ILCK    0x0002      /* Versatec faded. Zebra only. */
0042 #define P_OCR_EN_VER    0x0001      /* Enable Versatec (0 - enable). Zebra only. */
0043
0044 /* P_TCR */
0045 #define P_TCR_DIR       0x08
0046 #define P_TCR_BUSY      0x04
0047 #define P_TCR_ACK       0x02
0048 #define P_TCR_DS        0x01        /* Strobe */
0049
0050 /* P_OR */
0051 #define P_OR_V3         0x20        /* )                 */
0052 #define P_OR_V2         0x10        /* ) on Zebra only   */
0053 #define P_OR_V1         0x08        /* )                 */
0054 #define P_OR_INIT       0x04
0055 #define P_OR_AFXN       0x02        /* Auto Feed */
0056 #define P_OR_SLCT_IN    0x01
0057
0058 /* P_IR */
0059 #define P_IR_PE         0x04
0060 #define P_IR_SLCT       0x02
0061 #define P_IR_ERR        0x01
0062
0063 /* P_ICR */
0064 #define P_DS_IRQ        0x8000      /* RW1  */
0065 #define P_ACK_IRQ       0x4000      /* RW1  */
0066 #define P_BUSY_IRQ      0x2000      /* RW1  */
0067 #define P_PE_IRQ        0x1000      /* RW1  */
0068 #define P_SLCT_IRQ      0x0800      /* RW1  */
0069 #define P_ERR_IRQ       0x0400      /* RW1  */
0070 #define P_DS_IRQ_EN     0x0200      /* RW   Always on rising edge */
0071 #define P_ACK_IRQ_EN    0x0100      /* RW   Always on rising edge */
0072 #define P_BUSY_IRP      0x0080      /* RW   1= rising edge */
0073 #define P_BUSY_IRQ_EN   0x0040      /* RW   */
0074 #define P_PE_IRP        0x0020      /* RW   1= rising edge */
0075 #define P_PE_IRQ_EN     0x0010      /* RW   */
0076 #define P_SLCT_IRP      0x0008      /* RW   1= rising edge */
0077 #define P_SLCT_IRQ_EN   0x0004      /* RW   */
0078 #define P_ERR_IRP       0x0002      /* RW1  1= rising edge */
0079 #define P_ERR_IRQ_EN    0x0001      /* RW   */
0080
0081 #endif /* !(_ASM_SPARC_SUNBPP_H) */