include/asm/spitfire.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
0003  *
0004  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
0005  */
0006
0007 #ifndef _SPARC64_SPITFIRE_H
0008 #define _SPARC64_SPITFIRE_H
0009
0010 #ifdef CONFIG_SPARC64
0011
0012 #include <asm/asi.h>
0013
0014 /* The following register addresses are accessible via ASI_DMMU
0015  * and ASI_IMMU, that is there is a distinct and unique copy of
0016  * each these registers for each TLB.
0017  */
0018 #define TSB_TAG_TARGET      0x0000000000000000 /* All chips             */
0019 #define TLB_SFSR        0x0000000000000018 /* All chips             */
0020 #define TSB_REG         0x0000000000000028 /* All chips             */
0021 #define TLB_TAG_ACCESS      0x0000000000000030 /* All chips             */
0022 #define VIRT_WATCHPOINT     0x0000000000000038 /* All chips             */
0023 #define PHYS_WATCHPOINT     0x0000000000000040 /* All chips             */
0024 #define TSB_EXTENSION_P     0x0000000000000048 /* Ultra-III and later       */
0025 #define TSB_EXTENSION_S     0x0000000000000050 /* Ultra-III and later, D-TLB only   */
0026 #define TSB_EXTENSION_N     0x0000000000000058 /* Ultra-III and later       */
0027 #define TLB_TAG_ACCESS_EXT  0x0000000000000060 /* Ultra-III+ and later      */
0028
0029 /* These registers only exist as one entity, and are accessed
0030  * via ASI_DMMU only.
0031  */
0032 #define PRIMARY_CONTEXT     0x0000000000000008
0033 #define SECONDARY_CONTEXT   0x0000000000000010
0034 #define DMMU_SFAR       0x0000000000000020
0035 #define VIRT_WATCHPOINT     0x0000000000000038
0036 #define PHYS_WATCHPOINT     0x0000000000000040
0037
0038 #define SPITFIRE_HIGHEST_LOCKED_TLBENT  (64 - 1)
0039 #define CHEETAH_HIGHEST_LOCKED_TLBENT   (16 - 1)
0040
0041 #define L1DCACHE_SIZE       0x4000
0042
0043 #define SUN4V_CHIP_INVALID  0x00
0044 #define SUN4V_CHIP_NIAGARA1 0x01
0045 #define SUN4V_CHIP_NIAGARA2 0x02
0046 #define SUN4V_CHIP_NIAGARA3 0x03
0047 #define SUN4V_CHIP_NIAGARA4 0x04
0048 #define SUN4V_CHIP_NIAGARA5 0x05
0049 #define SUN4V_CHIP_SPARC_M6 0x06
0050 #define SUN4V_CHIP_SPARC_M7 0x07
0051 #define SUN4V_CHIP_SPARC_M8 0x08
0052 #define SUN4V_CHIP_SPARC64X 0x8a
0053 #define SUN4V_CHIP_SPARC_SN 0x8b
0054 #define SUN4V_CHIP_UNKNOWN  0xff
0055
0056 /*
0057  * The following CPU_ID_xxx constants are used
0058  * to identify the CPU type in the setup phase
0059  * (see head_64.S)
0060  */
0061 #define CPU_ID_NIAGARA1     ('1')
0062 #define CPU_ID_NIAGARA2     ('2')
0063 #define CPU_ID_NIAGARA3     ('3')
0064 #define CPU_ID_NIAGARA4     ('4')
0065 #define CPU_ID_NIAGARA5     ('5')
0066 #define CPU_ID_M6       ('6')
0067 #define CPU_ID_M7       ('7')
0068 #define CPU_ID_M8       ('8')
0069 #define CPU_ID_SONOMA1      ('N')
0070
0071 #ifndef __ASSEMBLY__
0072
0073 enum ultra_tlb_layout {
0074     spitfire = 0,
0075     cheetah = 1,
0076     cheetah_plus = 2,
0077     hypervisor = 3,
0078 };
0079
0080 extern enum ultra_tlb_layout tlb_type;
0081
0082 extern int sun4v_chip_type;
0083
0084 extern int cheetah_pcache_forced_on;
0085 void cheetah_enable_pcache(void);
0086
0087 #define sparc64_highest_locked_tlbent() \
0088     (tlb_type == spitfire ? \
0089      SPITFIRE_HIGHEST_LOCKED_TLBENT : \
0090      CHEETAH_HIGHEST_LOCKED_TLBENT)
0091
0092 extern int num_kernel_image_mappings;
0093
0094 /* The data cache is write through, so this just invalidates the
0095  * specified line.
0096  */
0097 static inline void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
0098 {
0099     __asm__ __volatile__("stxa  %0, [%1] %2\n\t"
0100                  "membar    #Sync"
0101                  : /* No outputs */
0102                  : "r" (tag), "r" (addr), "i" (ASI_DCACHE_TAG));
0103 }
0104
0105 /* The instruction cache lines are flushed with this, but note that
0106  * this does not flush the pipeline.  It is possible for a line to
0107  * get flushed but stale instructions to still be in the pipeline,
0108  * a flush instruction (to any address) is sufficient to handle
0109  * this issue after the line is invalidated.
0110  */
0111 static inline void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
0112 {
0113     __asm__ __volatile__("stxa  %0, [%1] %2\n\t"
0114                  "membar    #Sync"
0115                  : /* No outputs */
0116                  : "r" (tag), "r" (addr), "i" (ASI_IC_TAG));
0117 }
0118
0119 static inline unsigned long spitfire_get_dtlb_data(int entry)
0120 {
0121     unsigned long data;
0122
0123     __asm__ __volatile__("ldxa  [%1] %2, %0"
0124                  : "=r" (data)
0125                  : "r" (entry << 3), "i" (ASI_DTLB_DATA_ACCESS));
0126
0127     /* Clear TTE diag bits. */
0128     data &= ~0x0003fe0000000000UL;
0129
0130     return data;
0131 }
0132
0133 static inline unsigned long spitfire_get_dtlb_tag(int entry)
0134 {
0135     unsigned long tag;
0136
0137     __asm__ __volatile__("ldxa  [%1] %2, %0"
0138                  : "=r" (tag)
0139                  : "r" (entry << 3), "i" (ASI_DTLB_TAG_READ));
0140     return tag;
0141 }
0142
0143 static inline void spitfire_put_dtlb_data(int entry, unsigned long data)
0144 {
0145     __asm__ __volatile__("stxa  %0, [%1] %2\n\t"
0146                  "membar    #Sync"
0147                  : /* No outputs */
0148                  : "r" (data), "r" (entry << 3),
0149                    "i" (ASI_DTLB_DATA_ACCESS));
0150 }
0151
0152 static inline unsigned long spitfire_get_itlb_data(int entry)
0153 {
0154     unsigned long data;
0155
0156     __asm__ __volatile__("ldxa  [%1] %2, %0"
0157                  : "=r" (data)
0158                  : "r" (entry << 3), "i" (ASI_ITLB_DATA_ACCESS));
0159
0160     /* Clear TTE diag bits. */
0161     data &= ~0x0003fe0000000000UL;
0162
0163     return data;
0164 }
0165
0166 static inline unsigned long spitfire_get_itlb_tag(int entry)
0167 {
0168     unsigned long tag;
0169
0170     __asm__ __volatile__("ldxa  [%1] %2, %0"
0171                  : "=r" (tag)
0172                  : "r" (entry << 3), "i" (ASI_ITLB_TAG_READ));
0173     return tag;
0174 }
0175
0176 static inline void spitfire_put_itlb_data(int entry, unsigned long data)
0177 {
0178     __asm__ __volatile__("stxa  %0, [%1] %2\n\t"
0179                  "membar    #Sync"
0180                  : /* No outputs */
0181                  : "r" (data), "r" (entry << 3),
0182                    "i" (ASI_ITLB_DATA_ACCESS));
0183 }
0184
0185 static inline void spitfire_flush_dtlb_nucleus_page(unsigned long page)
0186 {
0187     __asm__ __volatile__("stxa  %%g0, [%0] %1\n\t"
0188                  "membar    #Sync"
0189                  : /* No outputs */
0190                  : "r" (page | 0x20), "i" (ASI_DMMU_DEMAP));
0191 }
0192
0193 static inline void spitfire_flush_itlb_nucleus_page(unsigned long page)
0194 {
0195     __asm__ __volatile__("stxa  %%g0, [%0] %1\n\t"
0196                  "membar    #Sync"
0197                  : /* No outputs */
0198                  : "r" (page | 0x20), "i" (ASI_IMMU_DEMAP));
0199 }
0200
0201 /* Cheetah has "all non-locked" tlb flushes. */
0202 static inline void cheetah_flush_dtlb_all(void)
0203 {
0204     __asm__ __volatile__("stxa  %%g0, [%0] %1\n\t"
0205                  "membar    #Sync"
0206                  : /* No outputs */
0207                  : "r" (0x80), "i" (ASI_DMMU_DEMAP));
0208 }
0209
0210 static inline void cheetah_flush_itlb_all(void)
0211 {
0212     __asm__ __volatile__("stxa  %%g0, [%0] %1\n\t"
0213                  "membar    #Sync"
0214                  : /* No outputs */
0215                  : "r" (0x80), "i" (ASI_IMMU_DEMAP));
0216 }
0217
0218 /* Cheetah has a 4-tlb layout so direct access is a bit different.
0219  * The first two TLBs are fully assosciative, hold 16 entries, and are
0220  * used only for locked and >8K sized translations.  One exists for
0221  * data accesses and one for instruction accesses.
0222  *
0223  * The third TLB is for data accesses to 8K non-locked translations, is
0224  * 2 way assosciative, and holds 512 entries.  The fourth TLB is for
0225  * instruction accesses to 8K non-locked translations, is 2 way
0226  * assosciative, and holds 128 entries.
0227  *
0228  * Cheetah has some bug where bogus data can be returned from
0229  * ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes
0230  * the problem for me. -DaveM
0231  */
0232 static inline unsigned long cheetah_get_ldtlb_data(int entry)
0233 {
0234     unsigned long data;
0235
0236     __asm__ __volatile__("ldxa  [%1] %2, %%g0\n\t"
0237                  "ldxa  [%1] %2, %0"
0238                  : "=r" (data)
0239                  : "r" ((0 << 16) | (entry << 3)),
0240                  "i" (ASI_DTLB_DATA_ACCESS));
0241
0242     return data;
0243 }
0244
0245 static inline unsigned long cheetah_get_litlb_data(int entry)
0246 {
0247     unsigned long data;
0248
0249     __asm__ __volatile__("ldxa  [%1] %2, %%g0\n\t"
0250                  "ldxa  [%1] %2, %0"
0251                  : "=r" (data)
0252                  : "r" ((0 << 16) | (entry << 3)),
0253                  "i" (ASI_ITLB_DATA_ACCESS));
0254
0255     return data;
0256 }
0257
0258 static inline unsigned long cheetah_get_ldtlb_tag(int entry)
0259 {
0260     unsigned long tag;
0261
0262     __asm__ __volatile__("ldxa  [%1] %2, %0"
0263                  : "=r" (tag)
0264                  : "r" ((0 << 16) | (entry << 3)),
0265                  "i" (ASI_DTLB_TAG_READ));
0266
0267     return tag;
0268 }
0269
0270 static inline unsigned long cheetah_get_litlb_tag(int entry)
0271 {
0272     unsigned long tag;
0273
0274     __asm__ __volatile__("ldxa  [%1] %2, %0"
0275                  : "=r" (tag)
0276                  : "r" ((0 << 16) | (entry << 3)),
0277                  "i" (ASI_ITLB_TAG_READ));
0278
0279     return tag;
0280 }
0281
0282 static inline void cheetah_put_ldtlb_data(int entry, unsigned long data)
0283 {
0284     __asm__ __volatile__("stxa  %0, [%1] %2\n\t"
0285                  "membar    #Sync"
0286                  : /* No outputs */
0287                  : "r" (data),
0288                    "r" ((0 << 16) | (entry << 3)),
0289                    "i" (ASI_DTLB_DATA_ACCESS));
0290 }
0291
0292 static inline void cheetah_put_litlb_data(int entry, unsigned long data)
0293 {
0294     __asm__ __volatile__("stxa  %0, [%1] %2\n\t"
0295                  "membar    #Sync"
0296                  : /* No outputs */
0297                  : "r" (data),
0298                    "r" ((0 << 16) | (entry << 3)),
0299                    "i" (ASI_ITLB_DATA_ACCESS));
0300 }
0301
0302 static inline unsigned long cheetah_get_dtlb_data(int entry, int tlb)
0303 {
0304     unsigned long data;
0305
0306     __asm__ __volatile__("ldxa  [%1] %2, %%g0\n\t"
0307                  "ldxa  [%1] %2, %0"
0308                  : "=r" (data)
0309                  : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_DATA_ACCESS));
0310
0311     return data;
0312 }
0313
0314 static inline unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
0315 {
0316     unsigned long tag;
0317
0318     __asm__ __volatile__("ldxa  [%1] %2, %0"
0319                  : "=r" (tag)
0320                  : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_TAG_READ));
0321     return tag;
0322 }
0323
0324 static inline void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb)
0325 {
0326     __asm__ __volatile__("stxa  %0, [%1] %2\n\t"
0327                  "membar    #Sync"
0328                  : /* No outputs */
0329                  : "r" (data),
0330                    "r" ((tlb << 16) | (entry << 3)),
0331                    "i" (ASI_DTLB_DATA_ACCESS));
0332 }
0333
0334 static inline unsigned long cheetah_get_itlb_data(int entry)
0335 {
0336     unsigned long data;
0337
0338     __asm__ __volatile__("ldxa  [%1] %2, %%g0\n\t"
0339                  "ldxa  [%1] %2, %0"
0340                  : "=r" (data)
0341                  : "r" ((2 << 16) | (entry << 3)),
0342                                "i" (ASI_ITLB_DATA_ACCESS));
0343
0344     return data;
0345 }
0346
0347 static inline unsigned long cheetah_get_itlb_tag(int entry)
0348 {
0349     unsigned long tag;
0350
0351     __asm__ __volatile__("ldxa  [%1] %2, %0"
0352                  : "=r" (tag)
0353                  : "r" ((2 << 16) | (entry << 3)), "i" (ASI_ITLB_TAG_READ));
0354     return tag;
0355 }
0356
0357 static inline void cheetah_put_itlb_data(int entry, unsigned long data)
0358 {
0359     __asm__ __volatile__("stxa  %0, [%1] %2\n\t"
0360                  "membar    #Sync"
0361                  : /* No outputs */
0362                  : "r" (data), "r" ((2 << 16) | (entry << 3)),
0363                    "i" (ASI_ITLB_DATA_ACCESS));
0364 }
0365
0366 #endif /* !(__ASSEMBLY__) */
0367 #endif /* CONFIG_SPARC64 */
0368 #endif /* !(_SPARC64_SPITFIRE_H) */