include/asm/sbi.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * sbi.h:  SBI (Sbus Interface on sun4d) definitions
0004  *
0005  * Copyright (C) 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz>
0006  */
0007
0008 #ifndef _SPARC_SBI_H
0009 #define _SPARC_SBI_H
0010
0011 #include <asm/obio.h>
0012
0013 /* SBI */
0014 struct sbi_regs {
0015 /* 0x0000 */    u32     cid;        /* Component ID */
0016 /* 0x0004 */    u32     ctl;        /* Control */
0017 /* 0x0008 */    u32     status;     /* Status */
0018         u32     _unused1;
0019
0020 /* 0x0010 */    u32     cfg0;       /* Slot0 config reg */
0021 /* 0x0014 */    u32     cfg1;       /* Slot1 config reg */
0022 /* 0x0018 */    u32     cfg2;       /* Slot2 config reg */
0023 /* 0x001c */    u32     cfg3;       /* Slot3 config reg */
0024
0025 /* 0x0020 */    u32     stb0;       /* Streaming buf control for slot 0 */
0026 /* 0x0024 */    u32     stb1;       /* Streaming buf control for slot 1 */
0027 /* 0x0028 */    u32     stb2;       /* Streaming buf control for slot 2 */
0028 /* 0x002c */    u32     stb3;       /* Streaming buf control for slot 3 */
0029
0030 /* 0x0030 */    u32     intr_state; /* Interrupt state */
0031 /* 0x0034 */    u32     intr_tid;   /* Interrupt target ID */
0032 /* 0x0038 */    u32     intr_diag;  /* Interrupt diagnostics */
0033 };
0034
0035 #define SBI_CID         0x02800000
0036 #define SBI_CTL         0x02800004
0037 #define SBI_STATUS      0x02800008
0038 #define SBI_CFG0        0x02800010
0039 #define SBI_CFG1        0x02800014
0040 #define SBI_CFG2        0x02800018
0041 #define SBI_CFG3        0x0280001c
0042 #define SBI_STB0        0x02800020
0043 #define SBI_STB1        0x02800024
0044 #define SBI_STB2        0x02800028
0045 #define SBI_STB3        0x0280002c
0046 #define SBI_INTR_STATE      0x02800030
0047 #define SBI_INTR_TID        0x02800034
0048 #define SBI_INTR_DIAG       0x02800038
0049
0050 /* Burst bits for 8, 16, 32, 64 are in cfgX registers at bits 2, 3, 4, 5 respectively */
0051 #define SBI_CFG_BURST_MASK  0x0000001e
0052
0053 /* How to make devid from sbi no */
0054 #define SBI2DEVID(sbino) ((sbino<<4)|2)
0055
0056 /* intr_state has 4 bits for slots 0 .. 3 and these bits are repeated for each sbus irq level
0057  *
0058  *         +-------+-------+-------+-------+-------+-------+-------+-------+
0059  *  SBUS IRQ LEVEL |   7   |   6   |   5   |   4   |   3   |   2   |   1   |       |
0060  *         +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ Reser |
0061  *  SLOT #         |3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|  ved  |
0062  *                 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------+
0063  *  Bits           31      27      23      19      15      11      7       3      0
0064  */
0065
0066
0067 #ifndef __ASSEMBLY__
0068
0069 static inline int acquire_sbi(int devid, int mask)
0070 {
0071     __asm__ __volatile__ ("swapa [%2] %3, %0" :
0072                   "=r" (mask) :
0073                   "0" (mask),
0074                   "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
0075                   "i" (ASI_M_CTL));
0076     return mask;
0077 }
0078
0079 static inline void release_sbi(int devid, int mask)
0080 {
0081     __asm__ __volatile__ ("sta %0, [%1] %2" : :
0082                   "r" (mask),
0083                   "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
0084                   "i" (ASI_M_CTL));
0085 }
0086
0087 static inline void set_sbi_tid(int devid, int targetid)
0088 {
0089     __asm__ __volatile__ ("sta %0, [%1] %2" : :
0090                   "r" (targetid),
0091                   "r" (ECSR_DEV_BASE(devid) | SBI_INTR_TID),
0092                   "i" (ASI_M_CTL));
0093 }
0094
0095 static inline int get_sbi_ctl(int devid, int cfgno)
0096 {
0097     int cfg;
0098
0099     __asm__ __volatile__ ("lda [%1] %2, %0" :
0100                   "=r" (cfg) :
0101                   "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
0102                   "i" (ASI_M_CTL));
0103     return cfg;
0104 }
0105
0106 static inline void set_sbi_ctl(int devid, int cfgno, int cfg)
0107 {
0108     __asm__ __volatile__ ("sta %0, [%1] %2" : :
0109                   "r" (cfg),
0110                   "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
0111                   "i" (ASI_M_CTL));
0112 }
0113
0114 #endif /* !__ASSEMBLY__ */
0115
0116 #endif /* !(_SPARC_SBI_H) */