include/asm/ross.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * ross.h: Ross module specific definitions and defines.
0004  *
0005  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
0006  */
0007
0008 #ifndef _SPARC_ROSS_H
0009 #define _SPARC_ROSS_H
0010
0011 #include <asm/asi.h>
0012 #include <asm/page.h>
0013
0014 /* Ross made Hypersparcs have a %psr 'impl' field of '0001'.  The 'vers'
0015  * field has '1111'.
0016  */
0017
0018 /* The MMU control register fields on the HyperSparc.
0019  *
0020  * -----------------------------------------------------------------
0021  * |implvers| RSV |CWR|SE|WBE| MID |BM| C|CS|MR|CM|RSV|CE|RSV|NF|ME|
0022  * -----------------------------------------------------------------
0023  *  31    24 23-22 21  20  19 18-15 14 13 12 11 10  9   8 7-2  1  0
0024  *
0025  * Phew, lots of fields there ;-)
0026  *
0027  * CWR: Cache Wrapping Enabled, if one cache wrapping is on.
0028  * SE: Snoop Enable, turns on bus snooping for cache activity if one.
0029  * WBE: Write Buffer Enable, one turns it on.
0030  * MID: The ModuleID of the chip for MBus transactions.
0031  * BM: Boot-Mode. One indicates the MMU is in boot mode.
0032  * C: Indicates whether accesses are cachable while the MMU is
0033  *    disabled.
0034  * CS: Cache Size -- 0 = 128k, 1 = 256k
0035  * MR: Memory Reflection, one indicates that the memory bus connected
0036  *     to the MBus supports memory reflection.
0037  * CM: Cache Mode -- 0 = write-through, 1 = copy-back
0038  * CE: Cache Enable -- 0 = no caching, 1 = cache is on
0039  * NF: No Fault -- 0 = faults trap the CPU from supervisor mode
0040  *                 1 = faults from supervisor mode do not generate traps
0041  * ME: MMU Enable -- 0 = MMU is off, 1 = MMU is on
0042  */
0043
0044 #define HYPERSPARC_CWENABLE   0x00200000
0045 #define HYPERSPARC_SBENABLE   0x00100000
0046 #define HYPERSPARC_WBENABLE   0x00080000
0047 #define HYPERSPARC_MIDMASK    0x00078000
0048 #define HYPERSPARC_BMODE      0x00004000
0049 #define HYPERSPARC_ACENABLE   0x00002000
0050 #define HYPERSPARC_CSIZE      0x00001000
0051 #define HYPERSPARC_MRFLCT     0x00000800
0052 #define HYPERSPARC_CMODE      0x00000400
0053 #define HYPERSPARC_CENABLE    0x00000100
0054 #define HYPERSPARC_NFAULT     0x00000002
0055 #define HYPERSPARC_MENABLE    0x00000001
0056
0057
0058 /* The ICCR instruction cache register on the HyperSparc.
0059  *
0060  * -----------------------------------------------
0061  * |                                 | FTD | ICE |
0062  * -----------------------------------------------
0063  *  31                                  1     0
0064  *
0065  * This register is accessed using the V8 'wrasr' and 'rdasr'
0066  * opcodes, since not all assemblers understand them and those
0067  * that do use different semantics I will just hard code the
0068  * instruction with a '.word' statement.
0069  *
0070  * FTD:  If set to one flush instructions executed during an
0071  *       instruction cache hit occurs, the corresponding line
0072  *       for said cache-hit is invalidated.  If FTD is zero,
0073  *       an unimplemented 'flush' trap will occur when any
0074  *       flush is executed by the processor.
0075  *
0076  * ICE:  If set to one, the instruction cache is enabled.  If
0077  *       zero, the cache will not be used for instruction fetches.
0078  *
0079  * All other bits are read as zeros, and writes to them have no
0080  * effect.
0081  *
0082  * Wheee, not many assemblers understand the %iccr register nor
0083  * the generic asr r/w instructions.
0084  *
0085  *  1000 0011 0100 0111 1100 0000 0000 0000   ! rd %iccr, %g1
0086  *
0087  * 0x  8    3    4    7    c    0    0    0   ! 0x8347c000
0088  *
0089  *  1011 1111 1000 0000 0110 0000 0000 0000   ! wr %g1, 0x0, %iccr
0090  *
0091  * 0x  b    f    8    0    6    0    0    0   ! 0xbf806000
0092  *
0093  */
0094
0095 #define HYPERSPARC_ICCR_FTD     0x00000002
0096 #define HYPERSPARC_ICCR_ICE     0x00000001
0097
0098 #ifndef __ASSEMBLY__
0099
0100 static inline unsigned int get_ross_icr(void)
0101 {
0102     unsigned int icreg;
0103
0104     __asm__ __volatile__(".word 0x8347c000\n\t" /* rd %iccr, %g1 */
0105                  "mov %%g1, %0\n\t"
0106                  : "=r" (icreg)
0107                  : /* no inputs */
0108                  : "g1", "memory");
0109
0110     return icreg;
0111 }
0112
0113 static inline void put_ross_icr(unsigned int icreg)
0114 {
0115     __asm__ __volatile__("or %%g0, %0, %%g1\n\t"
0116                  ".word 0xbf806000\n\t" /* wr %g1, 0x0, %iccr */
0117                  "nop\n\t"
0118                  "nop\n\t"
0119                  "nop\n\t"
0120                  : /* no outputs */
0121                  : "r" (icreg)
0122                  : "g1", "memory");
0123
0124     return;
0125 }
0126
0127 /* HyperSparc specific cache flushing. */
0128
0129 /* This is for the on-chip instruction cache. */
0130 static inline void hyper_flush_whole_icache(void)
0131 {
0132     __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
0133                  : /* no outputs */
0134                  : "i" (ASI_M_FLUSH_IWHOLE)
0135                  : "memory");
0136     return;
0137 }
0138
0139 extern int vac_cache_size;
0140 extern int vac_line_size;
0141
0142 static inline void hyper_clear_all_tags(void)
0143 {
0144     unsigned long addr;
0145
0146     for(addr = 0; addr < vac_cache_size; addr += vac_line_size)
0147         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
0148                      : /* no outputs */
0149                      : "r" (addr), "i" (ASI_M_DATAC_TAG)
0150                      : "memory");
0151 }
0152
0153 static inline void hyper_flush_unconditional_combined(void)
0154 {
0155     unsigned long addr;
0156
0157     for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
0158         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
0159                      : /* no outputs */
0160                      : "r" (addr), "i" (ASI_M_FLUSH_CTX)
0161                      : "memory");
0162 }
0163
0164 static inline void hyper_flush_cache_user(void)
0165 {
0166     unsigned long addr;
0167
0168     for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
0169         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
0170                      : /* no outputs */
0171                      : "r" (addr), "i" (ASI_M_FLUSH_USER)
0172                      : "memory");
0173 }
0174
0175 static inline void hyper_flush_cache_page(unsigned long page)
0176 {
0177     unsigned long end;
0178
0179     page &= PAGE_MASK;
0180     end = page + PAGE_SIZE;
0181     while (page < end) {
0182         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
0183                      : /* no outputs */
0184                      : "r" (page), "i" (ASI_M_FLUSH_PAGE)
0185                      : "memory");
0186         page += vac_line_size;
0187     }
0188 }
0189
0190 #endif /* !(__ASSEMBLY__) */
0191
0192 #endif /* !(_SPARC_ROSS_H) */