include/asm/pgtsrmmu.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * pgtsrmmu.h:  SRMMU page table defines and code.
0004  *
0005  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
0006  */
0007
0008 #ifndef _SPARC_PGTSRMMU_H
0009 #define _SPARC_PGTSRMMU_H
0010
0011 #include <asm/page.h>
0012
0013 #ifdef __ASSEMBLY__
0014 #include <asm/thread_info.h>    /* TI_UWINMASK for WINDOW_FLUSH */
0015 #endif
0016
0017 /* Number of contexts is implementation-dependent; 64k is the most we support */
0018 #define SRMMU_MAX_CONTEXTS  65536
0019
0020 #define SRMMU_PTE_TABLE_SIZE        (PTRS_PER_PTE*4)
0021 #define SRMMU_PMD_TABLE_SIZE        (PTRS_PER_PMD*4)
0022 #define SRMMU_PGD_TABLE_SIZE        (PTRS_PER_PGD*4)
0023
0024 /* Definition of the values in the ET field of PTD's and PTE's */
0025 #define SRMMU_ET_MASK         0x3
0026 #define SRMMU_ET_INVALID      0x0
0027 #define SRMMU_ET_PTD          0x1
0028 #define SRMMU_ET_PTE          0x2
0029 #define SRMMU_ET_REPTE        0x3 /* AIEEE, SuperSparc II reverse endian page! */
0030
0031 /* Physical page extraction from PTP's and PTE's. */
0032 #define SRMMU_CTX_PMASK    0xfffffff0
0033 #define SRMMU_PTD_PMASK    0xfffffff0
0034 #define SRMMU_PTE_PMASK    0xffffff00
0035
0036 /* The pte non-page bits.  Some notes:
0037  * 1) cache, dirty, valid, and ref are frobbable
0038  *    for both supervisor and user pages.
0039  * 2) exec and write will only give the desired effect
0040  *    on user pages
0041  * 3) use priv and priv_readonly for changing the
0042  *    characteristics of supervisor ptes
0043  */
0044 #define SRMMU_CACHE        0x80
0045 #define SRMMU_DIRTY        0x40
0046 #define SRMMU_REF          0x20
0047 #define SRMMU_NOREAD       0x10
0048 #define SRMMU_EXEC         0x08
0049 #define SRMMU_WRITE        0x04
0050 #define SRMMU_VALID        0x02 /* SRMMU_ET_PTE */
0051 #define SRMMU_PRIV         0x1c
0052 #define SRMMU_PRIV_RDONLY  0x18
0053
0054 #define SRMMU_CHG_MASK    (0xffffff00 | SRMMU_REF | SRMMU_DIRTY)
0055
0056 /* SRMMU swap entry encoding
0057  *
0058  * We use 5 bits for the type and 19 for the offset.  This gives us
0059  * 32 swapfiles of 4GB each.  Encoding looks like:
0060  *
0061  * oooooooooooooooooootttttRRRRRRRR
0062  * fedcba9876543210fedcba9876543210
0063  *
0064  * The bottom 7 bits are reserved for protection and status bits, especially
0065  * PRESENT.
0066  */
0067 #define SRMMU_SWP_TYPE_MASK 0x1f
0068 #define SRMMU_SWP_TYPE_SHIFT    7
0069 #define SRMMU_SWP_OFF_MASK  0xfffff
0070 #define SRMMU_SWP_OFF_SHIFT (SRMMU_SWP_TYPE_SHIFT + 5)
0071
0072 /* Some day I will implement true fine grained access bits for
0073  * user pages because the SRMMU gives us the capabilities to
0074  * enforce all the protection levels that vma's can have.
0075  * XXX But for now...
0076  */
0077 #define SRMMU_PAGE_NONE    __pgprot(SRMMU_CACHE | \
0078                     SRMMU_PRIV | SRMMU_REF)
0079 #define SRMMU_PAGE_SHARED  __pgprot(SRMMU_VALID | SRMMU_CACHE | \
0080                     SRMMU_EXEC | SRMMU_WRITE | SRMMU_REF)
0081 #define SRMMU_PAGE_COPY    __pgprot(SRMMU_VALID | SRMMU_CACHE | \
0082                     SRMMU_EXEC | SRMMU_REF)
0083 #define SRMMU_PAGE_RDONLY  __pgprot(SRMMU_VALID | SRMMU_CACHE | \
0084                     SRMMU_EXEC | SRMMU_REF)
0085 #define SRMMU_PAGE_KERNEL  __pgprot(SRMMU_VALID | SRMMU_CACHE | SRMMU_PRIV | \
0086                     SRMMU_DIRTY | SRMMU_REF)
0087
0088 /* SRMMU Register addresses in ASI 0x4.  These are valid for all
0089  * current SRMMU implementations that exist.
0090  */
0091 #define SRMMU_CTRL_REG           0x00000000
0092 #define SRMMU_CTXTBL_PTR         0x00000100
0093 #define SRMMU_CTX_REG            0x00000200
0094 #define SRMMU_FAULT_STATUS       0x00000300
0095 #define SRMMU_FAULT_ADDR         0x00000400
0096
0097 #define WINDOW_FLUSH(tmp1, tmp2)                    \
0098     mov 0, tmp1;                        \
0099 98: ld  [%g6 + TI_UWINMASK], tmp2;              \
0100     orcc    %g0, tmp2, %g0;                     \
0101     add tmp1, 1, tmp1;                      \
0102     bne 98b;                            \
0103      save   %sp, -64, %sp;                      \
0104 99: subcc   tmp1, 1, tmp1;                      \
0105     bne 99b;                            \
0106      restore %g0, %g0, %g0;
0107
0108 #ifndef __ASSEMBLY__
0109 extern unsigned long last_valid_pfn;
0110
0111 /* This makes sense. Honest it does - Anton */
0112 /* XXX Yes but it's ugly as sin.  FIXME. -KMW */
0113 extern void *srmmu_nocache_pool;
0114 #define __nocache_pa(VADDR) (((unsigned long)VADDR) - SRMMU_NOCACHE_VADDR + __pa((unsigned long)srmmu_nocache_pool))
0115 #define __nocache_va(PADDR) (__va((unsigned long)PADDR) - (unsigned long)srmmu_nocache_pool + SRMMU_NOCACHE_VADDR)
0116 #define __nocache_fix(VADDR) ((__typeof__(VADDR))__va(__nocache_pa(VADDR)))
0117
0118 /* Accessing the MMU control register. */
0119 unsigned int srmmu_get_mmureg(void);
0120 void srmmu_set_mmureg(unsigned long regval);
0121 void srmmu_set_ctable_ptr(unsigned long paddr);
0122 void srmmu_set_context(int context);
0123 int srmmu_get_context(void);
0124 unsigned int srmmu_get_fstatus(void);
0125 unsigned int srmmu_get_faddr(void);
0126
0127 /* This is guaranteed on all SRMMU's. */
0128 static inline void srmmu_flush_whole_tlb(void)
0129 {
0130     __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
0131                  "r" (0x400),        /* Flush entire TLB!! */
0132                  "i" (ASI_M_FLUSH_PROBE) : "memory");
0133
0134 }
0135
0136 static inline int
0137 srmmu_get_pte (unsigned long addr)
0138 {
0139     register unsigned long entry;
0140
0141     __asm__ __volatile__("\n\tlda [%1] %2,%0\n\t" :
0142                 "=r" (entry):
0143                 "r" ((addr & 0xfffff000) | 0x400), "i" (ASI_M_FLUSH_PROBE));
0144     return entry;
0145 }
0146
0147 #endif /* !(__ASSEMBLY__) */
0148
0149 #endif /* !(_SPARC_PGTSRMMU_H) */