include/asm/pcic.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * pcic.h: JavaEngine 1 specific PCI definitions.
0004  *
0005  * Copyright (C) 1998 V. Roganov and G. Raiko
0006  */
0007
0008 #ifndef __SPARC_PCIC_H
0009 #define __SPARC_PCIC_H
0010
0011 #ifndef __ASSEMBLY__
0012
0013 #include <linux/types.h>
0014 #include <linux/smp.h>
0015 #include <linux/pci.h>
0016 #include <linux/ioport.h>
0017 #include <asm/pbm.h>
0018
0019 struct linux_pcic {
0020         void __iomem            *pcic_regs;
0021         unsigned long           pcic_io;
0022         void __iomem            *pcic_config_space_addr;
0023         void __iomem            *pcic_config_space_data;
0024     struct resource     pcic_res_regs;
0025     struct resource     pcic_res_io;
0026     struct resource     pcic_res_cfg_addr;
0027     struct resource     pcic_res_cfg_data;
0028         struct linux_pbm_info   pbm;
0029     struct pcic_ca2irq  *pcic_imap;
0030     int         pcic_imdim;
0031 };
0032
0033 #ifdef CONFIG_PCIC_PCI
0034 int pcic_present(void);
0035 int pcic_probe(void);
0036 void pci_time_init(void);
0037 void sun4m_pci_init_IRQ(void);
0038 #else
0039 static inline int pcic_present(void) { return 0; }
0040 static inline int pcic_probe(void) { return 0; }
0041 static inline void pci_time_init(void) {}
0042 static inline void sun4m_pci_init_IRQ(void) {}
0043 #endif
0044 #endif
0045
0046 /* Size of PCI I/O space which we relocate. */
0047 #define PCI_SPACE_SIZE                  0x1000000       /* 16 MB */
0048
0049 /* PCIC Register Set. */
0050 #define PCI_DIAGNOSTIC_0                0x40    /* 32 bits */
0051 #define PCI_SIZE_0                      0x44    /* 32 bits */
0052 #define PCI_SIZE_1                      0x48    /* 32 bits */
0053 #define PCI_SIZE_2                      0x4c    /* 32 bits */
0054 #define PCI_SIZE_3                      0x50    /* 32 bits */
0055 #define PCI_SIZE_4                      0x54    /* 32 bits */
0056 #define PCI_SIZE_5                      0x58    /* 32 bits */
0057 #define PCI_PIO_CONTROL                 0x60    /* 8  bits */
0058 #define PCI_DVMA_CONTROL                0x62    /* 8  bits */
0059 #define  PCI_DVMA_CONTROL_INACTIVITY_REQ        (1<<0)
0060 #define  PCI_DVMA_CONTROL_IOTLB_ENABLE          (1<<0)
0061 #define  PCI_DVMA_CONTROL_IOTLB_DISABLE         0
0062 #define  PCI_DVMA_CONTROL_INACTIVITY_ACK        (1<<4)
0063 #define PCI_INTERRUPT_CONTROL           0x63    /* 8  bits */
0064 #define PCI_CPU_INTERRUPT_PENDING       0x64    /* 32 bits */
0065 #define PCI_DIAGNOSTIC_1                0x68    /* 16 bits */
0066 #define PCI_SOFTWARE_INT_CLEAR          0x6a    /* 16 bits */
0067 #define PCI_SOFTWARE_INT_SET            0x6e    /* 16 bits */
0068 #define PCI_SYS_INT_PENDING             0x70    /* 32 bits */
0069 #define  PCI_SYS_INT_PENDING_PIO        0x40000000
0070 #define  PCI_SYS_INT_PENDING_DMA        0x20000000
0071 #define  PCI_SYS_INT_PENDING_PCI        0x10000000
0072 #define  PCI_SYS_INT_PENDING_APSR       0x08000000
0073 #define PCI_SYS_INT_TARGET_MASK         0x74    /* 32 bits */
0074 #define PCI_SYS_INT_TARGET_MASK_CLEAR   0x78    /* 32 bits */
0075 #define PCI_SYS_INT_TARGET_MASK_SET     0x7c    /* 32 bits */
0076 #define PCI_SYS_INT_PENDING_CLEAR       0x83    /* 8  bits */
0077 #define  PCI_SYS_INT_PENDING_CLEAR_ALL      0x80
0078 #define  PCI_SYS_INT_PENDING_CLEAR_PIO      0x40
0079 #define  PCI_SYS_INT_PENDING_CLEAR_DMA      0x20
0080 #define  PCI_SYS_INT_PENDING_CLEAR_PCI      0x10
0081 #define PCI_IOTLB_CONTROL               0x84    /* 8  bits */
0082 #define PCI_INT_SELECT_LO               0x88    /* 16 bits */
0083 #define PCI_ARBITRATION_SELECT          0x8a    /* 16 bits */
0084 #define PCI_INT_SELECT_HI               0x8c    /* 16 bits */
0085 #define PCI_HW_INT_OUTPUT               0x8e    /* 16 bits */
0086 #define PCI_IOTLB_RAM_INPUT             0x90    /* 32 bits */
0087 #define PCI_IOTLB_CAM_INPUT             0x94    /* 32 bits */
0088 #define PCI_IOTLB_RAM_OUTPUT            0x98    /* 32 bits */
0089 #define PCI_IOTLB_CAM_OUTPUT            0x9c    /* 32 bits */
0090 #define PCI_SMBAR0                      0xa0    /* 8  bits */
0091 #define PCI_MSIZE0                      0xa1    /* 8  bits */
0092 #define PCI_PMBAR0                      0xa2    /* 8  bits */
0093 #define PCI_SMBAR1                      0xa4    /* 8  bits */
0094 #define PCI_MSIZE1                      0xa5    /* 8  bits */
0095 #define PCI_PMBAR1                      0xa6    /* 8  bits */
0096 #define PCI_SIBAR                       0xa8    /* 8  bits */
0097 #define   PCI_SIBAR_ADDRESS_MASK        0xf
0098 #define PCI_ISIZE                       0xa9    /* 8  bits */
0099 #define   PCI_ISIZE_16M                 0xf
0100 #define   PCI_ISIZE_32M                 0xe
0101 #define   PCI_ISIZE_64M                 0xc
0102 #define   PCI_ISIZE_128M                0x8
0103 #define   PCI_ISIZE_256M                0x0
0104 #define PCI_PIBAR                       0xaa    /* 8  bits */
0105 #define PCI_CPU_COUNTER_LIMIT_HI        0xac    /* 32 bits */
0106 #define PCI_CPU_COUNTER_LIMIT_LO        0xb0    /* 32 bits */
0107 #define PCI_CPU_COUNTER_LIMIT           0xb4    /* 32 bits */
0108 #define PCI_SYS_LIMIT                   0xb8    /* 32 bits */
0109 #define PCI_SYS_COUNTER                 0xbc    /* 32 bits */
0110 #define   PCI_SYS_COUNTER_OVERFLOW      (1<<31) /* Limit reached */
0111 #define PCI_SYS_LIMIT_PSEUDO            0xc0    /* 32 bits */
0112 #define PCI_USER_TIMER_CONTROL          0xc4    /* 8  bits */
0113 #define PCI_USER_TIMER_CONFIG           0xc5    /* 8  bits */
0114 #define PCI_COUNTER_IRQ                 0xc6    /* 8  bits */
0115 #define  PCI_COUNTER_IRQ_SET(sys_irq, cpu_irq)  ((((sys_irq) & 0xf) << 4) | \
0116                                                   ((cpu_irq) & 0xf))
0117 #define  PCI_COUNTER_IRQ_SYS(v)                 (((v) >> 4) & 0xf)
0118 #define  PCI_COUNTER_IRQ_CPU(v)                 ((v) & 0xf)
0119 #define PCI_PIO_ERROR_COMMAND           0xc7    /* 8  bits */
0120 #define PCI_PIO_ERROR_ADDRESS           0xc8    /* 32 bits */
0121 #define PCI_IOTLB_ERROR_ADDRESS         0xcc    /* 32 bits */
0122 #define PCI_SYS_STATUS                  0xd0    /* 8  bits */
0123 #define   PCI_SYS_STATUS_RESET_ENABLE           (1<<0)
0124 #define   PCI_SYS_STATUS_RESET                  (1<<1)
0125 #define   PCI_SYS_STATUS_WATCHDOG_RESET         (1<<4)
0126 #define   PCI_SYS_STATUS_PCI_RESET              (1<<5)
0127 #define   PCI_SYS_STATUS_PCI_RESET_ENABLE       (1<<6)
0128 #define   PCI_SYS_STATUS_PCI_SATTELITE_MODE     (1<<7)
0129
0130 #endif /* !(__SPARC_PCIC_H) */