include/asm/obio.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * obio.h:  Some useful locations in 0xFXXXXXXXX PA obio space on sun4d.
0004  *
0005  * Copyright (C) 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz>
0006  */
0007
0008 #ifndef _SPARC_OBIO_H
0009 #define _SPARC_OBIO_H
0010
0011 #include <asm/asi.h>
0012
0013 /* This weird monster likes to use the very upper parts of
0014    36bit PA for these things :) */
0015
0016 /* CSR space (for each XDBUS)
0017  *  ------------------------------------------------------------------------
0018  *  |   0xFE  |   DEVID    |                | XDBUS ID |                   |
0019  *  ------------------------------------------------------------------------
0020  *  35      28 27        20 19            10 9        8 7                 0
0021  */
0022
0023 #define CSR_BASE_ADDR       0xe0000000
0024 #define CSR_CPU_SHIFT       (32 - 4 - 5)
0025 #define CSR_XDBUS_SHIFT     8
0026
0027 #define CSR_BASE(cpu) (((CSR_BASE_ADDR >> CSR_CPU_SHIFT) + cpu) << CSR_CPU_SHIFT)
0028
0029 /* ECSR space (not for each XDBUS)
0030  *  ------------------------------------------------------------------------
0031  *  |   0xF  | DEVID[7:1] |                                    |
0032  *  ------------------------------------------------------------------------
0033  *  35     32 31        25 24                                 0
0034  */
0035
0036 #define ECSR_BASE_ADDR      0x00000000
0037 #define ECSR_CPU_SHIFT      (32 - 5)
0038 #define ECSR_DEV_SHIFT      (32 - 8)
0039
0040 #define ECSR_BASE(cpu) ((cpu) << ECSR_CPU_SHIFT)
0041 #define ECSR_DEV_BASE(devid) ((devid) << ECSR_DEV_SHIFT)
0042
0043 /* Bus Watcher */
0044 #define BW_LOCAL_BASE       0xfff00000
0045
0046 #define BW_CID          0x00000000
0047 #define BW_DBUS_CTRL        0x00000008
0048 #define BW_DBUS_DATA        0x00000010
0049 #define BW_CTRL         0x00001000
0050 #define BW_INTR_TABLE       0x00001040
0051 #define BW_INTR_TABLE_CLEAR 0x00001080
0052 #define BW_PRESCALER        0x000010c0
0053 #define BW_PTIMER_LIMIT     0x00002000
0054 #define BW_PTIMER_COUNTER2  0x00002004
0055 #define BW_PTIMER_NDLIMIT   0x00002008
0056 #define BW_PTIMER_CTRL      0x0000200c
0057 #define BW_PTIMER_COUNTER   0x00002010
0058 #define BW_TIMER_LIMIT      0x00003000
0059 #define BW_TIMER_COUNTER2   0x00003004
0060 #define BW_TIMER_NDLIMIT    0x00003008
0061 #define BW_TIMER_CTRL       0x0000300c
0062 #define BW_TIMER_COUNTER    0x00003010
0063
0064 /* BW Control */
0065 #define BW_CTRL_USER_TIMER  0x00000004  /* Is User Timer Free run enabled */
0066
0067 /* Boot Bus */
0068 #define BB_LOCAL_BASE       0xf0000000
0069
0070 #define BB_STAT1        0x00100000
0071 #define BB_STAT2        0x00120000
0072 #define BB_STAT3        0x00140000
0073 #define BB_LEDS         0x002e0000
0074
0075 /* Bits in BB_STAT2 */
0076 #define BB_STAT2_AC_INTR    0x04    /* Aiee! 5ms and power is gone... */
0077 #define BB_STAT2_TMP_INTR   0x10    /* My Penguins are burning. Are you able to smell it? */
0078 #define BB_STAT2_FAN_INTR   0x20    /* My fan refuses to work */
0079 #define BB_STAT2_PWR_INTR   0x40    /* On SC2000, one of the two ACs died. Ok, we go on... */
0080 #define BB_STAT2_MASK       (BB_STAT2_AC_INTR|BB_STAT2_TMP_INTR|BB_STAT2_FAN_INTR|BB_STAT2_PWR_INTR)
0081
0082 /* Cache Controller */
0083 #define CC_BASE     0x1F00000
0084 #define CC_DATSTREAM    0x1F00000  /* Data stream register */
0085 #define CC_DATSIZE  0x1F0003F  /* Size */
0086 #define CC_SRCSTREAM    0x1F00100  /* Source stream register */
0087 #define CC_DESSTREAM    0x1F00200  /* Destination stream register */
0088 #define CC_RMCOUNT  0x1F00300  /* Count of references and misses */
0089 #define CC_IPEN     0x1F00406  /* Pending Interrupts */
0090 #define CC_IMSK     0x1F00506  /* Interrupt Mask */
0091 #define CC_ICLR     0x1F00606  /* Clear pending Interrupts */
0092 #define CC_IGEN     0x1F00704  /* Generate Interrupt register */
0093 #define CC_STEST    0x1F00804  /* Internal self-test */
0094 #define CC_CREG     0x1F00A04  /* Control register */
0095 #define CC_SREG     0x1F00B00  /* Status register */
0096 #define CC_RREG     0x1F00C04  /* Reset register */
0097 #define CC_EREG     0x1F00E00  /* Error code register */
0098 #define CC_CID      0x1F00F04  /* Component ID */
0099
0100 #ifndef __ASSEMBLY__
0101
0102 static inline int bw_get_intr_mask(int sbus_level)
0103 {
0104     int mask;
0105
0106     __asm__ __volatile__ ("lduha [%1] %2, %0" :
0107                   "=r" (mask) :
0108                   "r" (BW_LOCAL_BASE + BW_INTR_TABLE + (sbus_level << 3)),
0109                   "i" (ASI_M_CTL));
0110     return mask;
0111 }
0112
0113 static inline void bw_clear_intr_mask(int sbus_level, int mask)
0114 {
0115     __asm__ __volatile__ ("stha %0, [%1] %2" : :
0116                   "r" (mask),
0117                   "r" (BW_LOCAL_BASE + BW_INTR_TABLE_CLEAR + (sbus_level << 3)),
0118                   "i" (ASI_M_CTL));
0119 }
0120
0121 static inline unsigned int bw_get_prof_limit(int cpu)
0122 {
0123     unsigned int limit;
0124
0125     __asm__ __volatile__ ("lda [%1] %2, %0" :
0126                   "=r" (limit) :
0127                   "r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT),
0128                   "i" (ASI_M_CTL));
0129     return limit;
0130 }
0131
0132 static inline void bw_set_prof_limit(int cpu, unsigned int limit)
0133 {
0134     __asm__ __volatile__ ("sta %0, [%1] %2" : :
0135                   "r" (limit),
0136                   "r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT),
0137                   "i" (ASI_M_CTL));
0138 }
0139
0140 static inline unsigned int bw_get_ctrl(int cpu)
0141 {
0142     unsigned int ctrl;
0143
0144     __asm__ __volatile__ ("lda [%1] %2, %0" :
0145                   "=r" (ctrl) :
0146                   "r" (CSR_BASE(cpu) + BW_CTRL),
0147                   "i" (ASI_M_CTL));
0148     return ctrl;
0149 }
0150
0151 static inline void bw_set_ctrl(int cpu, unsigned int ctrl)
0152 {
0153     __asm__ __volatile__ ("sta %0, [%1] %2" : :
0154                   "r" (ctrl),
0155                   "r" (CSR_BASE(cpu) + BW_CTRL),
0156                   "i" (ASI_M_CTL));
0157 }
0158
0159 static inline unsigned int cc_get_ipen(void)
0160 {
0161     unsigned int pending;
0162
0163     __asm__ __volatile__ ("lduha [%1] %2, %0" :
0164                   "=r" (pending) :
0165                   "r" (CC_IPEN),
0166                   "i" (ASI_M_MXCC));
0167     return pending;
0168 }
0169
0170 static inline void cc_set_iclr(unsigned int clear)
0171 {
0172     __asm__ __volatile__ ("stha %0, [%1] %2" : :
0173                   "r" (clear),
0174                   "r" (CC_ICLR),
0175                   "i" (ASI_M_MXCC));
0176 }
0177
0178 static inline unsigned int cc_get_imsk(void)
0179 {
0180     unsigned int mask;
0181
0182     __asm__ __volatile__ ("lduha [%1] %2, %0" :
0183                   "=r" (mask) :
0184                   "r" (CC_IMSK),
0185                   "i" (ASI_M_MXCC));
0186     return mask;
0187 }
0188
0189 static inline void cc_set_imsk(unsigned int mask)
0190 {
0191     __asm__ __volatile__ ("stha %0, [%1] %2" : :
0192                   "r" (mask),
0193                   "r" (CC_IMSK),
0194                   "i" (ASI_M_MXCC));
0195 }
0196
0197 static inline unsigned int cc_get_imsk_other(int cpuid)
0198 {
0199     unsigned int mask;
0200
0201     __asm__ __volatile__ ("lduha [%1] %2, %0" :
0202                   "=r" (mask) :
0203                   "r" (ECSR_BASE(cpuid) | CC_IMSK),
0204                   "i" (ASI_M_CTL));
0205     return mask;
0206 }
0207
0208 static inline void cc_set_imsk_other(int cpuid, unsigned int mask)
0209 {
0210     __asm__ __volatile__ ("stha %0, [%1] %2" : :
0211                   "r" (mask),
0212                   "r" (ECSR_BASE(cpuid) | CC_IMSK),
0213                   "i" (ASI_M_CTL));
0214 }
0215
0216 static inline void cc_set_igen(unsigned int gen)
0217 {
0218     __asm__ __volatile__ ("sta %0, [%1] %2" : :
0219                   "r" (gen),
0220                   "r" (CC_IGEN),
0221                   "i" (ASI_M_MXCC));
0222 }
0223
0224 #endif /* !__ASSEMBLY__ */
0225
0226 #endif /* !(_SPARC_OBIO_H) */