include/asm/ns87303.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* ns87303.h: Configuration Register Description for the
0003  *            National Semiconductor PC87303 (SuperIO).
0004  *
0005  * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
0006  */
0007
0008 #ifndef _SPARC_NS87303_H
0009 #define _SPARC_NS87303_H 1
0010
0011 /*
0012  * Control Register Index Values
0013  */
0014 #define FER 0x00
0015 #define FAR 0x01
0016 #define PTR 0x02
0017 #define FCR 0x03
0018 #define PCR 0x04
0019 #define KRR 0x05
0020 #define PMC 0x06
0021 #define TUP 0x07
0022 #define SID 0x08
0023 #define ASC 0x09
0024 #define CS0CF0  0x0a
0025 #define CS0CF1  0x0b
0026 #define CS1CF0  0x0c
0027 #define CS1CF1  0x0d
0028
0029 /* Function Enable Register (FER) bits */
0030 #define FER_EDM     0x10    /* Encoded Drive and Motor pin information   */
0031
0032 /* Function Address Register (FAR) bits */
0033 #define FAR_LPT_MASK    0x03
0034 #define FAR_LPTB    0x00
0035 #define FAR_LPTA    0x01
0036 #define FAR_LPTC    0x02
0037
0038 /* Power and Test Register (PTR) bits */
0039 #define PTR_LPTB_IRQ7   0x08
0040 #define PTR_LEVEL_IRQ   0x80    /* When not ECP/EPP: Use level IRQ           */
0041 #define PTR_LPT_REG_DIR 0x80    /* When ECP/EPP: LPT CTR controls direction */
0042                 /*               of the parallel port        */
0043
0044 /* Function Control Register (FCR) bits */
0045 #define FCR_LDE     0x10    /* Logical Drive Exchange                    */
0046 #define FCR_ZWS_ENA 0x20    /* Enable short host read/write in ECP/EPP   */
0047
0048 /* Printer Control Register (PCR) bits */
0049 #define PCR_EPP_ENABLE  0x01
0050 #define PCR_EPP_IEEE    0x02    /* Enable EPP Version 1.9 (IEEE 1284)        */
0051 #define PCR_ECP_ENABLE  0x04
0052 #define PCR_ECP_CLK_ENA 0x08    /* If 0 ECP Clock is stopped on Power down   */
0053 #define PCR_IRQ_POLAR   0x20    /* If 0 IRQ is level high or negative pulse, */
0054                 /* if 1 polarity is inverted                 */
0055 #define PCR_IRQ_ODRAIN  0x40    /* If 1, IRQ is open drain                   */
0056
0057 /* Tape UARTs and Parallel Port Config Register (TUP) bits */
0058 #define TUP_EPP_TIMO    0x02    /* Enable EPP timeout IRQ                    */
0059
0060 /* Advanced SuperIO Config Register (ASC) bits */
0061 #define ASC_LPT_IRQ7    0x01    /* Always use IRQ7 for LPT                  */
0062 #define ASC_DRV2_SEL    0x02    /* Logical Drive Exchange controlled by TDR  */
0063
0064 #define FER_RESERVED    0x00
0065 #define FAR_RESERVED    0x00
0066 #define PTR_RESERVED    0x73
0067 #define FCR_RESERVED    0xc4
0068 #define PCR_RESERVED    0x10
0069 #define KRR_RESERVED    0x00
0070 #define PMC_RESERVED    0x98
0071 #define TUP_RESERVED    0xfb
0072 #define SIP_RESERVED    0x00
0073 #define ASC_RESERVED    0x18
0074 #define CS0CF0_RESERVED 0x00
0075 #define CS0CF1_RESERVED 0x08
0076 #define CS1CF0_RESERVED 0x00
0077 #define CS1CF1_RESERVED 0x08
0078
0079 #ifdef __KERNEL__
0080
0081 #include <linux/spinlock.h>
0082
0083 #include <asm/io.h>
0084
0085 extern spinlock_t ns87303_lock;
0086
0087 static inline int ns87303_modify(unsigned long port, unsigned int index,
0088                      unsigned char clr, unsigned char set)
0089 {
0090     static unsigned char reserved[] = {
0091         FER_RESERVED, FAR_RESERVED, PTR_RESERVED, FCR_RESERVED,
0092         PCR_RESERVED, KRR_RESERVED, PMC_RESERVED, TUP_RESERVED,
0093         SIP_RESERVED, ASC_RESERVED, CS0CF0_RESERVED, CS0CF1_RESERVED,
0094         CS1CF0_RESERVED, CS1CF1_RESERVED
0095     };
0096     unsigned long flags;
0097     unsigned char value;
0098
0099     if (index > 0x0d)
0100         return -EINVAL;
0101
0102     spin_lock_irqsave(&ns87303_lock, flags);
0103
0104     outb(index, port);
0105     value = inb(port + 1);
0106     value &= ~(reserved[index] | clr);
0107     value |= set;
0108     outb(value, port + 1);
0109     outb(value, port + 1);
0110
0111     spin_unlock_irqrestore(&ns87303_lock, flags);
0112
0113     return 0;
0114 }
0115
0116 #endif /* __KERNEL__ */
0117
0118 #endif /* !(_SPARC_NS87303_H) */