include/asm/mxcc.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * mxcc.h:  Definitions of the Viking MXCC registers
0004  *
0005  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
0006  */
0007
0008 #ifndef _SPARC_MXCC_H
0009 #define _SPARC_MXCC_H
0010
0011 /* These registers are accessed through ASI 0x2. */
0012 #define MXCC_DATSTREAM       0x1C00000  /* Data stream register */
0013 #define MXCC_SRCSTREAM       0x1C00100  /* Source stream register */
0014 #define MXCC_DESSTREAM       0x1C00200  /* Destination stream register */
0015 #define MXCC_RMCOUNT         0x1C00300  /* Count of references and misses */
0016 #define MXCC_STEST           0x1C00804  /* Internal self-test */
0017 #define MXCC_CREG            0x1C00A04  /* Control register */
0018 #define MXCC_SREG            0x1C00B00  /* Status register */
0019 #define MXCC_RREG            0x1C00C04  /* Reset register */
0020 #define MXCC_EREG            0x1C00E00  /* Error code register */
0021 #define MXCC_PREG            0x1C00F04  /* Address port register */
0022
0023 /* Some MXCC constants. */
0024 #define MXCC_STREAM_SIZE     0x20       /* Size in bytes of one stream r/w */
0025
0026 /* The MXCC Control Register:
0027  *
0028  * ----------------------------------------------------------------------
0029  * |                                   | RRC | RSV |PRE|MCE|PARE|ECE|RSV|
0030  * ----------------------------------------------------------------------
0031  *  31                              10    9    8-6   5   4    3   2  1-0
0032  *
0033  * RRC: Controls what you read from MXCC_RMCOUNT reg.
0034  *      0=Misses 1=References
0035  * PRE: Prefetch enable
0036  * MCE: Multiple Command Enable
0037  * PARE: Parity enable
0038  * ECE: External cache enable
0039  */
0040
0041 #define MXCC_CTL_RRC   0x00000200
0042 #define MXCC_CTL_PRE   0x00000020
0043 #define MXCC_CTL_MCE   0x00000010
0044 #define MXCC_CTL_PARE  0x00000008
0045 #define MXCC_CTL_ECE   0x00000004
0046
0047 /* The MXCC Error Register:
0048  *
0049  * --------------------------------------------------------
0050  * |ME| RSV|CE|PEW|PEE|ASE|EIV| MOPC|ECODE|PRIV|RSV|HPADDR|
0051  * --------------------------------------------------------
0052  *  31   30 29  28  27  26  25 24-15  14-7   6  5-3   2-0
0053  *
0054  * ME: Multiple Errors have occurred
0055  * CE: Cache consistency Error
0056  * PEW: Parity Error during a Write operation
0057  * PEE: Parity Error involving the External cache
0058  * ASE: ASynchronous Error
0059  * EIV: This register is toast
0060  * MOPC: MXCC Operation Code for instance causing error
0061  * ECODE: The Error CODE
0062  * PRIV: A privileged mode error? 0=no 1=yes
0063  * HPADDR: High PhysicalADDRess bits (35-32)
0064  */
0065
0066 #define MXCC_ERR_ME     0x80000000
0067 #define MXCC_ERR_CE     0x20000000
0068 #define MXCC_ERR_PEW    0x10000000
0069 #define MXCC_ERR_PEE    0x08000000
0070 #define MXCC_ERR_ASE    0x04000000
0071 #define MXCC_ERR_EIV    0x02000000
0072 #define MXCC_ERR_MOPC   0x01FF8000
0073 #define MXCC_ERR_ECODE  0x00007F80
0074 #define MXCC_ERR_PRIV   0x00000040
0075 #define MXCC_ERR_HPADDR 0x0000000f
0076
0077 /* The MXCC Port register:
0078  *
0079  * -----------------------------------------------------
0080  * |                | MID |                            |
0081  * -----------------------------------------------------
0082  *  31            21 20-18 17                         0
0083  *
0084  * MID: The moduleID of the cpu your read this from.
0085  */
0086
0087 #ifndef __ASSEMBLY__
0088
0089 static inline void mxcc_set_stream_src(unsigned long *paddr)
0090 {
0091     unsigned long data0 = paddr[0];
0092     unsigned long data1 = paddr[1];
0093
0094     __asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
0095                   "or %%g0, %1, %%g3\n\t"
0096                   "stda %%g2, [%2] %3\n\t" : :
0097                   "r" (data0), "r" (data1),
0098                   "r" (MXCC_SRCSTREAM),
0099                   "i" (ASI_M_MXCC) : "g2", "g3");
0100 }
0101
0102 static inline void mxcc_set_stream_dst(unsigned long *paddr)
0103 {
0104     unsigned long data0 = paddr[0];
0105     unsigned long data1 = paddr[1];
0106
0107     __asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
0108                   "or %%g0, %1, %%g3\n\t"
0109                   "stda %%g2, [%2] %3\n\t" : :
0110                   "r" (data0), "r" (data1),
0111                   "r" (MXCC_DESSTREAM),
0112                   "i" (ASI_M_MXCC) : "g2", "g3");
0113 }
0114
0115 static inline unsigned long mxcc_get_creg(void)
0116 {
0117     unsigned long mxcc_control;
0118
0119     __asm__ __volatile__("set 0xffffffff, %%g2\n\t"
0120                  "set 0xffffffff, %%g3\n\t"
0121                  "stda %%g2, [%1] %2\n\t"
0122                  "lda [%3] %2, %0\n\t" :
0123                  "=r" (mxcc_control) :
0124                  "r" (MXCC_EREG), "i" (ASI_M_MXCC),
0125                  "r" (MXCC_CREG) : "g2", "g3");
0126     return mxcc_control;
0127 }
0128
0129 static inline void mxcc_set_creg(unsigned long mxcc_control)
0130 {
0131     __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
0132                  "r" (mxcc_control), "r" (MXCC_CREG),
0133                  "i" (ASI_M_MXCC));
0134 }
0135
0136 #endif /* !__ASSEMBLY__ */
0137
0138 #endif /* !(_SPARC_MXCC_H) */