include/asm/mmu_64.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __MMU_H
0003 #define __MMU_H
0004
0005 #include <linux/const.h>
0006 #include <asm/page.h>
0007 #include <asm/hypervisor.h>
0008
0009 #define CTX_NR_BITS     13
0010
0011 #define TAG_CONTEXT_BITS    ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))
0012
0013 /* UltraSPARC-III+ and later have a feature whereby you can
0014  * select what page size the various Data-TLB instances in the
0015  * chip.  In order to gracefully support this, we put the version
0016  * field in a spot outside of the areas of the context register
0017  * where this parameter is specified.
0018  */
0019 #define CTX_VERSION_SHIFT   22
0020 #define CTX_VERSION_MASK    ((~0UL) << CTX_VERSION_SHIFT)
0021
0022 #define CTX_PGSZ_8KB        _AC(0x0,UL)
0023 #define CTX_PGSZ_64KB       _AC(0x1,UL)
0024 #define CTX_PGSZ_512KB      _AC(0x2,UL)
0025 #define CTX_PGSZ_4MB        _AC(0x3,UL)
0026 #define CTX_PGSZ_BITS       _AC(0x7,UL)
0027 #define CTX_PGSZ0_NUC_SHIFT 61
0028 #define CTX_PGSZ1_NUC_SHIFT 58
0029 #define CTX_PGSZ0_SHIFT     16
0030 #define CTX_PGSZ1_SHIFT     19
0031 #define CTX_PGSZ_MASK       ((CTX_PGSZ_BITS << CTX_PGSZ0_SHIFT) | \
0032                  (CTX_PGSZ_BITS << CTX_PGSZ1_SHIFT))
0033
0034 #define CTX_PGSZ_BASE   CTX_PGSZ_8KB
0035 #define CTX_PGSZ_HUGE   CTX_PGSZ_4MB
0036 #define CTX_PGSZ_KERN   CTX_PGSZ_4MB
0037
0038 /* Thus, when running on UltraSPARC-III+ and later, we use the following
0039  * PRIMARY_CONTEXT register values for the kernel context.
0040  */
0041 #define CTX_CHEETAH_PLUS_NUC \
0042     ((CTX_PGSZ_KERN << CTX_PGSZ0_NUC_SHIFT) | \
0043      (CTX_PGSZ_BASE << CTX_PGSZ1_NUC_SHIFT))
0044
0045 #define CTX_CHEETAH_PLUS_CTX0 \
0046     ((CTX_PGSZ_KERN << CTX_PGSZ0_SHIFT) | \
0047      (CTX_PGSZ_BASE << CTX_PGSZ1_SHIFT))
0048
0049 /* If you want "the TLB context number" use CTX_NR_MASK.  If you
0050  * want "the bits I program into the context registers" use
0051  * CTX_HW_MASK.
0052  */
0053 #define CTX_NR_MASK     TAG_CONTEXT_BITS
0054 #define CTX_HW_MASK     (CTX_NR_MASK | CTX_PGSZ_MASK)
0055
0056 #define CTX_FIRST_VERSION   BIT(CTX_VERSION_SHIFT)
0057 #define CTX_VALID(__ctx)    \
0058      (!(((__ctx.sparc64_ctx_val) ^ tlb_context_cache) & CTX_VERSION_MASK))
0059 #define CTX_HWBITS(__ctx)   ((__ctx.sparc64_ctx_val) & CTX_HW_MASK)
0060 #define CTX_NRBITS(__ctx)   ((__ctx.sparc64_ctx_val) & CTX_NR_MASK)
0061
0062 #ifndef __ASSEMBLY__
0063
0064 #define TSB_ENTRY_ALIGNMENT 16
0065
0066 struct tsb {
0067     unsigned long tag;
0068     unsigned long pte;
0069 } __attribute__((aligned(TSB_ENTRY_ALIGNMENT)));
0070
0071 void __tsb_insert(unsigned long ent, unsigned long tag, unsigned long pte);
0072 void tsb_flush(unsigned long ent, unsigned long tag);
0073 void tsb_init(struct tsb *tsb, unsigned long size);
0074
0075 struct tsb_config {
0076     struct tsb      *tsb;
0077     unsigned long       tsb_rss_limit;
0078     unsigned long       tsb_nentries;
0079     unsigned long       tsb_reg_val;
0080     unsigned long       tsb_map_vaddr;
0081     unsigned long       tsb_map_pte;
0082 };
0083
0084 #define MM_TSB_BASE 0
0085
0086 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
0087 #define MM_TSB_HUGE 1
0088 #define MM_NUM_TSBS 2
0089 #else
0090 #define MM_NUM_TSBS 1
0091 #endif
0092
0093 /* ADI tags are stored when a page is swapped out and the storage for
0094  * tags is allocated dynamically. There is a tag storage descriptor
0095  * associated with each set of tag storage pages. Tag storage descriptors
0096  * are allocated dynamically. Since kernel will allocate a full page for
0097  * each tag storage descriptor, we can store up to
0098  * PAGE_SIZE/sizeof(tag storage descriptor) descriptors on that page.
0099  */
0100 typedef struct {
0101     unsigned long   start;      /* Start address for this tag storage */
0102     unsigned long   end;        /* Last address for tag storage */
0103     unsigned char   *tags;      /* Where the tags are */
0104     unsigned long   tag_users;  /* number of references to descriptor */
0105 } tag_storage_desc_t;
0106
0107 typedef struct {
0108     spinlock_t      lock;
0109     unsigned long       sparc64_ctx_val;
0110     unsigned long       hugetlb_pte_count;
0111     unsigned long       thp_pte_count;
0112     struct tsb_config   tsb_block[MM_NUM_TSBS];
0113     struct hv_tsb_descr tsb_descr[MM_NUM_TSBS];
0114     void            *vdso;
0115     bool            adi;
0116     tag_storage_desc_t  *tag_store;
0117     spinlock_t      tag_lock;
0118 } mm_context_t;
0119
0120 #endif /* !__ASSEMBLY__ */
0121
0122 #define TSB_CONFIG_TSB      0x00
0123 #define TSB_CONFIG_RSS_LIMIT    0x08
0124 #define TSB_CONFIG_NENTRIES 0x10
0125 #define TSB_CONFIG_REG_VAL  0x18
0126 #define TSB_CONFIG_MAP_VADDR    0x20
0127 #define TSB_CONFIG_MAP_PTE  0x28
0128
0129 #endif /* __MMU_H */