include/asm/mbus.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * mbus.h:  Various defines for MBUS modules.
0004  *
0005  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
0006  */
0007
0008 #ifndef _SPARC_MBUS_H
0009 #define _SPARC_MBUS_H
0010
0011 #include <asm/ross.h>    /* HyperSparc stuff */
0012 #include <asm/viking.h>  /* Ugh, bug city... */
0013
0014 enum mbus_module {
0015     HyperSparc        = 0,
0016     Swift_ok          = 4,
0017     Swift_bad_c       = 5,
0018     Swift_lots_o_bugs = 6,
0019     Tsunami           = 7,
0020     Viking_12         = 8,
0021     Viking_2x         = 9,
0022     Viking_30         = 10,
0023     Viking_35         = 11,
0024     Viking_new        = 12,
0025     TurboSparc    = 13,
0026     SRMMU_INVAL_MOD   = 14,
0027 };
0028
0029 extern enum mbus_module srmmu_modtype;
0030 extern unsigned int viking_rev, swift_rev, cypress_rev;
0031
0032 /* HW Mbus module bugs we have to deal with */
0033 #define HWBUG_COPYBACK_BROKEN        0x00000001
0034 #define HWBUG_ASIFLUSH_BROKEN        0x00000002
0035 #define HWBUG_VACFLUSH_BITROT        0x00000004
0036 #define HWBUG_KERN_ACCBROKEN         0x00000008
0037 #define HWBUG_KERN_CBITBROKEN        0x00000010
0038 #define HWBUG_MODIFIED_BITROT        0x00000020
0039 #define HWBUG_PC_BADFAULT_ADDR       0x00000040
0040 #define HWBUG_SUPERSCALAR_BAD        0x00000080
0041 #define HWBUG_PACINIT_BITROT         0x00000100
0042
0043 /* First the module type values. To find out which you have, just load
0044  * the mmu control register from ASI_M_MMUREG alternate address space and
0045  * shift the value right 28 bits.
0046  */
0047 /* IMPL field means the company which produced the chip. */
0048 #define MBUS_VIKING        0x4   /* bleech, Texas Instruments Module */
0049 #define MBUS_LSI           0x3   /* LSI Logics */
0050 #define MBUS_ROSS          0x1   /* Ross is nice */
0051 #define MBUS_FMI           0x0   /* Fujitsu Microelectronics/Swift */
0052
0053 /* Ross Module versions */
0054 #define ROSS_604_REV_CDE        0x0   /* revisions c, d, and e */
0055 #define ROSS_604_REV_F          0x1   /* revision f */
0056 #define ROSS_605                0xf   /* revision a, a.1, and a.2 */
0057 #define ROSS_605_REV_B          0xe   /* revision b */
0058
0059 /* TI Viking Module versions */
0060 #define VIKING_REV_12           0x1   /* Version 1.2 or SPARCclassic's CPU */
0061 #define VIKING_REV_2            0x2   /* Version 2.1, 2.2, 2.3, and 2.4 */
0062 #define VIKING_REV_30           0x3   /* Version 3.0 */
0063 #define VIKING_REV_35           0x4   /* Version 3.5 */
0064
0065 /* LSI Logics. */
0066 #define LSI_L64815      0x0
0067
0068 /* Fujitsu */
0069 #define FMI_AURORA      0x4   /* MB8690x, a Swift module... */
0070 #define FMI_TURBO       0x5   /* MB86907, a TurboSparc module... */
0071
0072 /* For multiprocessor support we need to be able to obtain the CPU id and
0073  * the MBUS Module id.
0074  */
0075
0076 /* The CPU ID is encoded in the trap base register, 20 bits to the left of
0077  * bit zero, with 2 bits being significant.
0078  */
0079 #define TBR_ID_SHIFT            20
0080
0081 static inline int get_cpuid(void)
0082 {
0083     register int retval;
0084     __asm__ __volatile__("rd %%tbr, %0\n\t"
0085                  "srl %0, %1, %0\n\t" :
0086                  "=r" (retval) :
0087                  "i" (TBR_ID_SHIFT));
0088     return (retval & 3);
0089 }
0090
0091 static inline int get_modid(void)
0092 {
0093     return (get_cpuid() | 0x8);
0094 }
0095
0096
0097 #endif /* !(_SPARC_MBUS_H) */