include/asm/irq_64.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* irq.h: IRQ registers on the 64-bit Sparc.
0003  *
0004  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
0005  * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
0006  */
0007
0008 #ifndef _SPARC64_IRQ_H
0009 #define _SPARC64_IRQ_H
0010
0011 #include <linux/linkage.h>
0012 #include <linux/kernel.h>
0013 #include <linux/errno.h>
0014 #include <linux/interrupt.h>
0015 #include <asm/pil.h>
0016 #include <asm/ptrace.h>
0017
0018 /* IMAP/ICLR register defines */
0019 #define IMAP_VALID      0x80000000UL    /* IRQ Enabled      */
0020 #define IMAP_TID_UPA        0x7c000000UL    /* UPA TargetID     */
0021 #define IMAP_TID_JBUS       0x7c000000UL    /* JBUS TargetID    */
0022 #define IMAP_TID_SHIFT      26
0023 #define IMAP_AID_SAFARI     0x7c000000UL    /* Safari AgentID   */
0024 #define IMAP_AID_SHIFT      26
0025 #define IMAP_NID_SAFARI     0x03e00000UL    /* Safari NodeID    */
0026 #define IMAP_NID_SHIFT      21
0027 #define IMAP_IGN        0x000007c0UL    /* IRQ Group Number */
0028 #define IMAP_INO        0x0000003fUL    /* IRQ Number       */
0029 #define IMAP_INR        0x000007ffUL    /* Full interrupt number*/
0030
0031 #define ICLR_IDLE       0x00000000UL    /* Idle state       */
0032 #define ICLR_TRANSMIT       0x00000001UL    /* Transmit state   */
0033 #define ICLR_PENDING        0x00000003UL    /* Pending state    */
0034
0035 /* The largest number of unique interrupt sources we support.
0036  * If this needs to ever be larger than 255, you need to change
0037  * the type of ino_bucket->irq as appropriate.
0038  *
0039  * ino_bucket->irq allocation is made during {sun4v_,}build_irq().
0040  */
0041 #define NR_IRQS     (2048)
0042
0043 void irq_install_pre_handler(int irq,
0044                  void (*func)(unsigned int, void *, void *),
0045                  void *arg1, void *arg2);
0046 #define irq_canonicalize(irq)   (irq)
0047 unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap);
0048 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino);
0049 unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino);
0050 unsigned int sun4v_build_msi(u32 devhandle, unsigned int *irq_p,
0051                  unsigned int msi_devino_start,
0052                  unsigned int msi_devino_end);
0053 void sun4v_destroy_msi(unsigned int irq);
0054 unsigned int sun4u_build_msi(u32 portid, unsigned int *irq_p,
0055                  unsigned int msi_devino_start,
0056                  unsigned int msi_devino_end,
0057                  unsigned long imap_base,
0058                  unsigned long iclr_base);
0059 void sun4u_destroy_msi(unsigned int irq);
0060
0061 unsigned int irq_alloc(unsigned int dev_handle, unsigned int dev_ino);
0062 void irq_free(unsigned int irq);
0063
0064 void __init init_IRQ(void);
0065 void fixup_irqs(void);
0066
0067 static inline void set_softint(unsigned long bits)
0068 {
0069     __asm__ __volatile__("wr    %0, 0x0, %%set_softint"
0070                  : /* No outputs */
0071                  : "r" (bits));
0072 }
0073
0074 static inline void clear_softint(unsigned long bits)
0075 {
0076     __asm__ __volatile__("wr    %0, 0x0, %%clear_softint"
0077                  : /* No outputs */
0078                  : "r" (bits));
0079 }
0080
0081 static inline unsigned long get_softint(void)
0082 {
0083     unsigned long retval;
0084
0085     __asm__ __volatile__("rd    %%softint, %0"
0086                  : "=r" (retval));
0087     return retval;
0088 }
0089
0090 void arch_trigger_cpumask_backtrace(const struct cpumask *mask,
0091                     bool exclude_self);
0092 #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
0093
0094 extern void *hardirq_stack[NR_CPUS];
0095 extern void *softirq_stack[NR_CPUS];
0096
0097 #define NO_IRQ      0xffffffff
0098
0099 #endif